/* Autogenerated file, DO NOT EDIT manually! generated by perf-metricset-codegen.py
 *
 * Copyright (c) 2018 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include <stddef.h>
#include <stdint.h>
#include <stdlib.h>
#include <stdbool.h>
#include <assert.h>

#include "i915_drm.h"

#include "i915_perf_metrics_acmgt2.h"
#include "i915_perf_equations.h"
#include "i915_perf_registers_acmgt2.h"

static bool acmgt2_render_basic_Sampler20Bottleneck_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_render_basic_Sampler20Busy_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_render_basic_SamplerBottleneck_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_render_basic_SamplersBusy_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_render_basic_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Render Metrics Basic - aggregation approximation";
    metric_set->symbol_name = "RenderBasic";
    metric_set->hw_config_guid = "0692a728-614d-4d12-8c03-7b3ffe961ef8";
    metric_set->counters = calloc(40, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_render_basic_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__render_basic__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__render_basic__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CS Threads Dispatched",
                .symbol_name = "CsThreads",
                .desc = "The total number of compute shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__render_basic__cs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "DS Threads Dispatched",
                .symbol_name = "DsThreads",
                .desc = "The total number of domain shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__render_basic__ds_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "Early Depth Test Fails",
                .symbol_name = "EarlyDepthTestFails",
                .desc = "The total number of pixels dropped on early depth test.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt2__render_basic__early_depth_test_fails__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_basic__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__render_basic__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__render_basic__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS Threads Dispatched",
                .symbol_name = "GsThreads",
                .desc = "The total number of geometry shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__render_basic__gs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "GTI Read Throughput",
                .symbol_name = "GtiReadThroughput",
                .desc = "The total number of GPU memory bytes read from GTI.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__render_basic__gti_read_throughput__read,
                .max_uint64 = acmgt2__render_basic__gti_read_throughput__max,
                .group = "Memory",
            },

            {
                .name = "GTI Write Throughput",
                .symbol_name = "GtiWriteThroughput",
                .desc = "The total number of GPU memory bytes written to GTI.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__render_basic__gti_write_throughput__read,
                .max_uint64 = acmgt2__render_basic__gti_write_throughput__max,
                .group = "Memory",
            },

            {
                .name = "Early Hi-Depth Test Fails",
                .symbol_name = "HiDepthTestFails",
                .desc = "The total number of pixels dropped on early hierarchical depth test.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt2__render_basic__hi_depth_test_fails__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
            },

            {
                .name = "HS Threads Dispatched",
                .symbol_name = "HsThreads",
                .desc = "The total number of hull shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__render_basic__hs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "Pixels Failing Tests",
                .symbol_name = "PixelsFailingPostPsTests",
                .desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt2__render_basic__pixels_failing_post_ps_tests__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
            },

            {
                .name = "FS EM Pipe Active",
                .symbol_name = "PsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a fragment shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_basic__ps_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "FS FPU Pipe Active",
                .symbol_name = "PsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a fragment shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_basic__ps_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "FS Send Pipe Active",
                .symbol_name = "PsSendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing a fragment shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_basic__ps_send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "FS Threads Dispatched",
                .symbol_name = "PsThreads",
                .desc = "The total number of fragment shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__render_basic__ps_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "Rasterized Pixels",
                .symbol_name = "RasterizedPixels",
                .desc = "The total number of rasterized pixels.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt2__render_basic__rasterized_pixels__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
            },

            {
                .name = "Sampler20 Bottleneck",
                .symbol_name = "Sampler20Bottleneck",
                .desc = "The percentage of time in which Slice2 Sampler0 has been slowing down the pipe when processing XVE requests.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_basic__sampler20_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_render_basic_Sampler20Bottleneck_availability,
            },

            {
                .name = "Sampler Slice2 Xe Core0 is busy",
                .symbol_name = "Sampler20Busy",
                .desc = "The percentage of time when sampler slice2 Xe core0 is busy",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_basic__sampler20_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_render_basic_Sampler20Busy_availability,
            },

            {
                .name = "Samplers Bottleneck",
                .symbol_name = "SamplerBottleneck",
                .desc = "The percentage of time in which samplers have been slowing down the pipe when processing XVE requests.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_basic__sampler_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_render_basic_SamplerBottleneck_availability,
            },

            {
                .name = "Sampler Texels Misses",
                .symbol_name = "SamplerTexelMisses",
                .desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_TEXELS,
                .read_uint64 = acmgt2__render_basic__sampler_texel_misses__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
            },

            {
                .name = "Sampler Texels",
                .symbol_name = "SamplerTexels",
                .desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_TEXELS,
                .read_uint64 = acmgt2__render_basic__sampler_texels__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
            },

            {
                .name = "Samplers Busy",
                .symbol_name = "SamplersBusy",
                .desc = "The percentage of time in which samplers or L1 cache are not idle.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_basic__samplers_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_render_basic_SamplersBusy_availability,
            },

            {
                .name = "Samples Blended",
                .symbol_name = "SamplesBlended",
                .desc = "The total number of blended samples or pixels written to all render targets.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt2__render_basic__samples_blended__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
            },

            {
                .name = "Samples Killed in FS",
                .symbol_name = "SamplesKilledInPs",
                .desc = "The total number of samples or pixels dropped in fragment shaders.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt2__render_basic__samples_killed_in_ps__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
            },

            {
                .name = "Samples Written",
                .symbol_name = "SamplesWritten",
                .desc = "The total number of samples or pixels written to all render targets.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt2__render_basic__samples_written__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
            },

            {
                .name = "Shader Atomic Memory Accesses",
                .symbol_name = "ShaderAtomics",
                .desc = "The total number of shader atomic memory accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt2__render_basic__shader_atomics__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "Shader Barrier Messages",
                .symbol_name = "ShaderBarriers",
                .desc = "The total number of shader barrier messages.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt2__render_basic__shader_barriers__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "Shader Memory Accesses",
                .symbol_name = "ShaderMemoryAccesses",
                .desc = "The total number of shader memory accesses to L3.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt2__render_basic__shader_memory_accesses__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "SLM Bytes Read",
                .symbol_name = "SlmReads",
                .desc = "The total number of reads from shared local memory.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt2__render_basic__slm_reads__read,
                .max_uint64 = acmgt2__render_basic__slm_reads__max,
                .group = "L1Cache",
            },

            {
                .name = "SLM Writes",
                .symbol_name = "SlmWrites",
                .desc = "The total number of writes into shared local memory.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt2__render_basic__slm_writes__read,
                .max_uint64 = acmgt2__render_basic__slm_writes__max,
                .group = "L1Cache",
            },

            {
                .name = "VS EM Pipe Active",
                .symbol_name = "VsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a vertex shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_basic__vs_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "VS FPU Pipe Active",
                .symbol_name = "VsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a vertex shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_basic__vs_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "VS Send Pipe Active",
                .symbol_name = "VsSendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing a vertex shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_basic__vs_send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "VS Threads Dispatched",
                .symbol_name = "VsThreads",
                .desc = "The total number of vertex shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__render_basic__vs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "XVE Active",
                .symbol_name = "XveActive",
                .desc = "The percentage of time in which the Execution Units were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_basic__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "EM And FPU Pipes Active",
                .symbol_name = "XveFpuEmActive",
                .desc = "The percentage of time in which XVE EM INT and FPU INT64 pipelines were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_basic__xve_fpu_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Stall",
                .symbol_name = "XveStall",
                .desc = "The percentage of time in which the Execution Units were stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_basic__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Thread Occupancy",
                .symbol_name = "XveThreadOccupancy",
                .desc = "The percentage of time in which hardware threads occupied XVEs.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_basic__xve_thread_occupancy__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 40);
}


static void
acmgt2_add_compute_basic_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Compute Metrics Basic";
    metric_set->symbol_name = "ComputeBasic";
    metric_set->hw_config_guid = "ccde9a29-a5c5-4a9e-b7f5-ec1092387e2a";
    metric_set->counters = calloc(27, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_compute_basic_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__compute_basic__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__compute_basic__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CS Threads Dispatched",
                .symbol_name = "CsThreads",
                .desc = "The total number of compute shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__compute_basic__cs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "EM Pipe Active",
                .symbol_name = "EmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__compute_basic__em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE FPU Pipe Active",
                .symbol_name = "FpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__compute_basic__fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__compute_basic__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__compute_basic__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__compute_basic__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GTI Read Throughput",
                .symbol_name = "GtiReadThroughput",
                .desc = "The total number of GPU memory bytes read from GTI.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__compute_basic__gti_read_throughput__read,
                .max_uint64 = acmgt2__compute_basic__gti_read_throughput__max,
                .group = "Memory",
            },

            {
                .name = "GTI Write Throughput",
                .symbol_name = "GtiWriteThroughput",
                .desc = "The total number of GPU memory bytes written to GTI.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__compute_basic__gti_write_throughput__read,
                .max_uint64 = acmgt2__compute_basic__gti_write_throughput__max,
                .group = "Memory",
            },

            {
                .name = "Sampler Texels Misses",
                .symbol_name = "SamplerTexelMisses",
                .desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_TEXELS,
                .read_uint64 = acmgt2__compute_basic__sampler_texel_misses__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
            },

            {
                .name = "Sampler Texels",
                .symbol_name = "SamplerTexels",
                .desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_TEXELS,
                .read_uint64 = acmgt2__compute_basic__sampler_texels__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
            },

            {
                .name = "Send Pipe Active",
                .symbol_name = "SendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__compute_basic__send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "Shader Atomic Memory Accesses",
                .symbol_name = "ShaderAtomics",
                .desc = "The total number of shader atomic memory accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt2__compute_basic__shader_atomics__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "Shader Barrier Messages",
                .symbol_name = "ShaderBarriers",
                .desc = "The total number of shader barrier messages.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt2__compute_basic__shader_barriers__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "Shader Memory Accesses",
                .symbol_name = "ShaderMemoryAccesses",
                .desc = "The total number of shader memory accesses to L3.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt2__compute_basic__shader_memory_accesses__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "SLM Bytes Read",
                .symbol_name = "SlmReads",
                .desc = "The total number of reads from shared local memory.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt2__compute_basic__slm_reads__read,
                .max_uint64 = acmgt2__compute_basic__slm_reads__max,
                .group = "L1Cache",
            },

            {
                .name = "SLM Writes",
                .symbol_name = "SlmWrites",
                .desc = "The total number of writes into shared local memory.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt2__compute_basic__slm_writes__read,
                .max_uint64 = acmgt2__compute_basic__slm_writes__max,
                .group = "L1Cache",
            },

            {
                .name = "XMX Pipe Active",
                .symbol_name = "XmxActive",
                .desc = "The percentage of time in which XVE XMX pipeline was actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__compute_basic__xmx_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Active",
                .symbol_name = "XveActive",
                .desc = "The percentage of time in which the Execution Units were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__compute_basic__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE AVG IPC Rate",
                .symbol_name = "XveAvgIpcRate",
                .desc = "The average rate of IPC calculated for 2 FPU pipelines.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NUMBER,
                .read_float = acmgt2__compute_basic__xve_avg_ipc_rate__read,
                .max_float = acmgt2__compute_basic__xve_avg_ipc_rate__max,
                .group = "VectorEngine",
            },

            {
                .name = "EM And FPU Pipes Active",
                .symbol_name = "XveFpuEmActive",
                .desc = "The percentage of time in which XVE EM INT and FPU INT64 pipelines were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__compute_basic__xve_fpu_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "FPU FLT16 Instruction",
                .symbol_name = "XveFpuFlt16",
                .desc = "The percentage of time in which FLT16 instruction were processed actively on FPU INT64 pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__compute_basic__xve_fpu_flt16__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "FPU FLT32 Instruction",
                .symbol_name = "XveFpuFlt32",
                .desc = "The percentage of time in which FLT32 instruction were processed actively on FPU INT64 pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__compute_basic__xve_fpu_flt32__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "FPU FLT64 Instruction",
                .symbol_name = "XveFpuFlt64",
                .desc = "The percentage of time in which FLT64 instruction were processed actively on FPU INT64 pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__compute_basic__xve_fpu_flt64__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XMX And FPU Pipes Active",
                .symbol_name = "XveFpuXmxActive",
                .desc = "The percentage of time in which XVE XMX and FPU INT64 pipelines were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__compute_basic__xve_fpu_xmx_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Stall",
                .symbol_name = "XveStall",
                .desc = "The percentage of time in which the Execution Units were stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__compute_basic__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Thread Occupancy",
                .symbol_name = "XveThreadOccupancy",
                .desc = "The percentage of time in which hardware threads occupied XVEs.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__compute_basic__xve_thread_occupancy__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 27);
}


static void
acmgt2_add_async_compute_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "AsyncCompute";
    metric_set->symbol_name = "AsyncCompute";
    metric_set->hw_config_guid = "e529d23d-d766-4391-84e2-68d43fd1f9b0";
    metric_set->counters = calloc(23, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_async_compute_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC CS EM Pipe Active",
                .symbol_name = "AsyncCsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a compute shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__async_compute__async_cs_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "ASYNC CS FPU Pipe Active",
                .symbol_name = "AsyncCsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a compute shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__async_compute__async_cs_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__async_compute__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__async_compute__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CS EM Pipe Active",
                .symbol_name = "CsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a compute shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__async_compute__cs_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "CS FPU Pipe Active",
                .symbol_name = "CsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a compute shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__async_compute__cs_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "CS Threads Dispatched",
                .symbol_name = "CsThreads",
                .desc = "The total number of compute shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__async_compute__cs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "DS Threads Dispatched",
                .symbol_name = "DsThreads",
                .desc = "The total number of domain shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__async_compute__ds_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "EM Pipe Active",
                .symbol_name = "EmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__async_compute__em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE FPU Pipe Active",
                .symbol_name = "FpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__async_compute__fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__async_compute__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__async_compute__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__async_compute__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS Threads Dispatched",
                .symbol_name = "GsThreads",
                .desc = "The total number of geometry shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__async_compute__gs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "HS Threads Dispatched",
                .symbol_name = "HsThreads",
                .desc = "The total number of hull shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__async_compute__hs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "FS EM Pipe Active",
                .symbol_name = "PsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a fragment shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__async_compute__ps_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "FS FPU Pipe Active",
                .symbol_name = "PsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a fragment shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__async_compute__ps_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "FS Threads Dispatched",
                .symbol_name = "PsThreads",
                .desc = "The total number of fragment shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__async_compute__ps_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "VS EM Pipe Active",
                .symbol_name = "VsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a vertex shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__async_compute__vs_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "VS FPU Pipe Active",
                .symbol_name = "VsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a vertex shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__async_compute__vs_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "VS Threads Dispatched",
                .symbol_name = "VsThreads",
                .desc = "The total number of vertex shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__async_compute__vs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "XVE Active",
                .symbol_name = "XveActive",
                .desc = "The percentage of time in which the Execution Units were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__async_compute__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Stall",
                .symbol_name = "XveStall",
                .desc = "The percentage of time in which the Execution Units were stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__async_compute__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Thread Occupancy",
                .symbol_name = "XveThreadOccupancy",
                .desc = "The percentage of time in which hardware threads occupied XVEs.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__async_compute__xve_thread_occupancy__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 23);
}


static void
acmgt2_add_xve_activity1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "XveActivity1";
    metric_set->symbol_name = "XveActivity1";
    metric_set->hw_config_guid = "0785f0af-8ae2-470c-bc7b-dd81154d4d24";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_xve_activity1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__xve_activity1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__xve_activity1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CS Send Pipe Active",
                .symbol_name = "CsSendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing a compute shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__xve_activity1__cs_send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "CS Threads Dispatched",
                .symbol_name = "CsThreads",
                .desc = "The total number of compute shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__xve_activity1__cs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "DS EM Pipe Active",
                .symbol_name = "DsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a domain shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__xve_activity1__ds_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "DS FPU Pipe Active",
                .symbol_name = "DsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a domain shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__xve_activity1__ds_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "DS Send Pipe Active",
                .symbol_name = "DsSendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing a domain shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__xve_activity1__ds_send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "DS Threads Dispatched",
                .symbol_name = "DsThreads",
                .desc = "The total number of domain shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__xve_activity1__ds_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__xve_activity1__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__xve_activity1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__xve_activity1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS EM Pipe Active",
                .symbol_name = "GsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a geometry shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__xve_activity1__gs_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "GS FPU Pipe Active",
                .symbol_name = "GsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a geometry shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__xve_activity1__gs_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "GS Send Pipe Active",
                .symbol_name = "GsSendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing a geometry shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__xve_activity1__gs_send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "GS Threads Dispatched",
                .symbol_name = "GsThreads",
                .desc = "The total number of geometry shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__xve_activity1__gs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "HS EM Pipe Active",
                .symbol_name = "HsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a hull shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__xve_activity1__hs_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "HS FPU Pipe Active",
                .symbol_name = "HsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a hull shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__xve_activity1__hs_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "HS Send Pipe Active",
                .symbol_name = "HsSendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing a hull shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__xve_activity1__hs_send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "HS Threads Dispatched",
                .symbol_name = "HsThreads",
                .desc = "The total number of hull shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__xve_activity1__hs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "FS Threads Dispatched",
                .symbol_name = "PsThreads",
                .desc = "The total number of fragment shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__xve_activity1__ps_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "VS Threads Dispatched",
                .symbol_name = "VsThreads",
                .desc = "The total number of vertex shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__xve_activity1__vs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}


static void
acmgt2_add_gpu_busyness_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "GpuBusyness";
    metric_set->symbol_name = "GpuBusyness";
    metric_set->hw_config_guid = "1a01365e-7c8d-4816-b69a-edb89731dcf9";
    metric_set->counters = calloc(23, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_gpu_busyness_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "Any compute engine busy",
                .symbol_name = "AnyComputeEngineBusy",
                .desc = "The percentage of time when any compute engine is busy",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__gpu_busyness__any_compute_engine_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__gpu_busyness__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__gpu_busyness__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "Blitter Ring Busy",
                .symbol_name = "BlitterBusy",
                .desc = "The percentage of time when blitter command streamer was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__gpu_busyness__blitter_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "ComputeEngine1 Ring Busy",
                .symbol_name = "ComputeEngine1Busy",
                .desc = "The percentage of time when compute command streamer 1 was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__gpu_busyness__compute_engine1_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "ComputeEngine2 Ring Busy",
                .symbol_name = "ComputeEngine2Busy",
                .desc = "The percentage of time when compute command streamer 2 was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__gpu_busyness__compute_engine2_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "CS Threads Dispatched",
                .symbol_name = "CsThreads",
                .desc = "The total number of compute shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__gpu_busyness__cs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "DS Threads Dispatched",
                .symbol_name = "DsThreads",
                .desc = "The total number of domain shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__gpu_busyness__ds_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__gpu_busyness__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__gpu_busyness__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__gpu_busyness__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS Threads Dispatched",
                .symbol_name = "GsThreads",
                .desc = "The total number of geometry shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__gpu_busyness__gs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "HS Threads Dispatched",
                .symbol_name = "HsThreads",
                .desc = "The total number of hull shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__gpu_busyness__hs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "FS Threads Dispatched",
                .symbol_name = "PsThreads",
                .desc = "The total number of fragment shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__gpu_busyness__ps_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "Render and any compute engines are simultaneously busy",
                .symbol_name = "RenderAndAnyComputeEngineBusy",
                .desc = "The percentage of time when render and any compute engines are simultaneously busy",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__gpu_busyness__render_and_any_compute_engine_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "Render Ring Busy",
                .symbol_name = "RenderBusy",
                .desc = "The percentage of time when render command streamer was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__gpu_busyness__render_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "Vdbox00 Ring Busy",
                .symbol_name = "Vdbox00Busy",
                .desc = "The percentage of time when vdbox00 command streamer was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__gpu_busyness__vdbox00_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "Media",
            },

            {
                .name = "Vdbox10 Ring Busy",
                .symbol_name = "Vdbox10Busy",
                .desc = "The percentage of time when vdbox10 command streamer was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__gpu_busyness__vdbox10_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "Media",
            },

            {
                .name = "Vebox0 Ring Busy",
                .symbol_name = "Vebox0Busy",
                .desc = "The percentage of time when vebox0 command streamer was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__gpu_busyness__vebox0_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "Media",
            },

            {
                .name = "Vebox1 Ring Busy",
                .symbol_name = "Vebox1Busy",
                .desc = "The percentage of time when vebox1 command streamer was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__gpu_busyness__vebox1_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "Media",
            },

            {
                .name = "VS Threads Dispatched",
                .symbol_name = "VsThreads",
                .desc = "The total number of vertex shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt2__gpu_busyness__vs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "XVE Active",
                .symbol_name = "XveActive",
                .desc = "The percentage of time in which the Execution Units were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__gpu_busyness__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Stall",
                .symbol_name = "XveStall",
                .desc = "The percentage of time in which the Execution Units were stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__gpu_busyness__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Thread Occupancy",
                .symbol_name = "XveThreadOccupancy",
                .desc = "The percentage of time in which hardware threads occupied XVEs.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__gpu_busyness__xve_thread_occupancy__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 23);
}


static void
acmgt2_add_render_pipe_profile1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Render Metrics for 3D Pipeline Profile";
    metric_set->symbol_name = "RenderPipeProfile1";
    metric_set->hw_config_guid = "9ca2b4be-4bd5-4873-9d59-9d6a5d9f8c29";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_render_pipe_profile1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__render_pipe_profile1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__render_pipe_profile1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "BC20 Bottleneck",
                .symbol_name = "Bc20Bottleneck",
                .desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile1__bc20_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Clipper2 Bottleneck",
                .symbol_name = "Cl2Bottleneck",
                .desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile1__cl2_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "CL2 Stall",
                .symbol_name = "Cl2Stall",
                .desc = "The percentage of time in which clipper pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile1__cl2_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS2 Bottleneck",
                .symbol_name = "Ds2Bottleneck",
                .desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile1__ds2_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS2 Stall",
                .symbol_name = "Ds2Stall",
                .desc = "The percentage of time in which domain shader pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile1__ds2_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile1__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__render_pipe_profile1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__render_pipe_profile1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS2 Bottleneck",
                .symbol_name = "Gs2Bottleneck",
                .desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile1__gs2_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Hi-Depth20 Bottleneck",
                .symbol_name = "HiDepth20Bottleneck",
                .desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile1__hi_depth20_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "HS2 Bottleneck",
                .symbol_name = "Hs2Bottleneck",
                .desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile1__hs2_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "HS2 Stall",
                .symbol_name = "Hs2Stall",
                .desc = "The percentage of time in which hull stall pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile1__hs2_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF2 Bottleneck",
                .symbol_name = "Sf2Bottleneck",
                .desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile1__sf2_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF2 Stall",
                .symbol_name = "Sf2Stall",
                .desc = "The percentage of time in which strip-fans pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile1__sf2_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO2 Bottleneck",
                .symbol_name = "So2Bottleneck",
                .desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile1__so2_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO2 Stall",
                .symbol_name = "So2Stall",
                .desc = "The percentage of time in which stream-output pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile1__so2_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VF2 Bottleneck",
                .symbol_name = "Vf2Bottleneck",
                .desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile1__vf2_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VS2 Bottleneck",
                .symbol_name = "Vs2Bottleneck",
                .desc = "The percentage of time in which VS2 pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile1__vs2_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}


static void
acmgt2_add_render_pipe_profile2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Render Metrics for 3D Pipeline Profile";
    metric_set->symbol_name = "RenderPipeProfile2";
    metric_set->hw_config_guid = "901cbc75-aa84-496c-a07d-c5db62b8dadb";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_render_pipe_profile2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__render_pipe_profile2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__render_pipe_profile2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "BC30 Bottleneck",
                .symbol_name = "Bc30Bottleneck",
                .desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile2__bc30_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Clipper3 Bottleneck",
                .symbol_name = "Cl3Bottleneck",
                .desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile2__cl3_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "CL3 Stall",
                .symbol_name = "Cl3Stall",
                .desc = "The percentage of time in which clipper pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile2__cl3_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS3 Bottleneck",
                .symbol_name = "Ds3Bottleneck",
                .desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile2__ds3_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS3 Stall",
                .symbol_name = "Ds3Stall",
                .desc = "The percentage of time in which domain shader pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile2__ds3_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile2__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__render_pipe_profile2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__render_pipe_profile2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS3 Bottleneck",
                .symbol_name = "Gs3Bottleneck",
                .desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile2__gs3_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Hi-Depth30 Bottleneck",
                .symbol_name = "HiDepth30Bottleneck",
                .desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile2__hi_depth30_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "HS3 Bottleneck",
                .symbol_name = "Hs3Bottleneck",
                .desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile2__hs3_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "HS3 Stall",
                .symbol_name = "Hs3Stall",
                .desc = "The percentage of time in which hull stall pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile2__hs3_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF3 Bottleneck",
                .symbol_name = "Sf3Bottleneck",
                .desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile2__sf3_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF3 Stall",
                .symbol_name = "Sf3Stall",
                .desc = "The percentage of time in which strip-fans pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile2__sf3_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO3 Bottleneck",
                .symbol_name = "So3Bottleneck",
                .desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile2__so3_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO3 Stall",
                .symbol_name = "So3Stall",
                .desc = "The percentage of time in which stream-output pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile2__so3_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VF3 Bottleneck",
                .symbol_name = "Vf3Bottleneck",
                .desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile2__vf3_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VS3 Bottleneck",
                .symbol_name = "Vs3Bottleneck",
                .desc = "The percentage of time in which VS3 pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile2__vs3_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}


static void
acmgt2_add_render_pipe_profile3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Render Metrics for 3D Pipeline Profile";
    metric_set->symbol_name = "RenderPipeProfile3";
    metric_set->hw_config_guid = "9afedc01-2ddf-46af-a5da-8310c1afed17";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_render_pipe_profile3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__render_pipe_profile3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__render_pipe_profile3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "BC40 Bottleneck",
                .symbol_name = "Bc40Bottleneck",
                .desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile3__bc40_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Clipper4 Bottleneck",
                .symbol_name = "Cl4Bottleneck",
                .desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile3__cl4_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "CL4 Stall",
                .symbol_name = "Cl4Stall",
                .desc = "The percentage of time in which clipper pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile3__cl4_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS4 Bottleneck",
                .symbol_name = "Ds4Bottleneck",
                .desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile3__ds4_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS4 Stall",
                .symbol_name = "Ds4Stall",
                .desc = "The percentage of time in which domain shader pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile3__ds4_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile3__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__render_pipe_profile3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__render_pipe_profile3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS4 Bottleneck",
                .symbol_name = "Gs4Bottleneck",
                .desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile3__gs4_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Hi-Depth40 Bottleneck",
                .symbol_name = "HiDepth40Bottleneck",
                .desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile3__hi_depth40_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "HS4 Bottleneck",
                .symbol_name = "Hs4Bottleneck",
                .desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile3__hs4_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "HS4 Stall",
                .symbol_name = "Hs4Stall",
                .desc = "The percentage of time in which hull stall pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile3__hs4_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF4 Bottleneck",
                .symbol_name = "Sf4Bottleneck",
                .desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile3__sf4_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF4 Stall",
                .symbol_name = "Sf4Stall",
                .desc = "The percentage of time in which strip-fans pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile3__sf4_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO4 Bottleneck",
                .symbol_name = "So4Bottleneck",
                .desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile3__so4_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO4 Stall",
                .symbol_name = "So4Stall",
                .desc = "The percentage of time in which stream-output pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile3__so4_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VF4 Bottleneck",
                .symbol_name = "Vf4Bottleneck",
                .desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile3__vf4_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VS4 Bottleneck",
                .symbol_name = "Vs4Bottleneck",
                .desc = "The percentage of time in which VS4 pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile3__vs4_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}


static void
acmgt2_add_render_pipe_profile4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Render Metrics for 3D Pipeline Profile";
    metric_set->symbol_name = "RenderPipeProfile4";
    metric_set->hw_config_guid = "89469a84-856d-4433-8962-773c68ce818b";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_render_pipe_profile4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__render_pipe_profile4__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__render_pipe_profile4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "BC50 Bottleneck",
                .symbol_name = "Bc50Bottleneck",
                .desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile4__bc50_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Clipper5 Bottleneck",
                .symbol_name = "Cl5Bottleneck",
                .desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile4__cl5_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "CL5 Stall",
                .symbol_name = "Cl5Stall",
                .desc = "The percentage of time in which clipper pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile4__cl5_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS5 Bottleneck",
                .symbol_name = "Ds5Bottleneck",
                .desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile4__ds5_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS5 Stall",
                .symbol_name = "Ds5Stall",
                .desc = "The percentage of time in which domain shader pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile4__ds5_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile4__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__render_pipe_profile4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__render_pipe_profile4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS5 Bottleneck",
                .symbol_name = "Gs5Bottleneck",
                .desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile4__gs5_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Hi-Depth50 Bottleneck",
                .symbol_name = "HiDepth50Bottleneck",
                .desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile4__hi_depth50_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "HS5 Bottleneck",
                .symbol_name = "Hs5Bottleneck",
                .desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile4__hs5_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "HS5 Stall",
                .symbol_name = "Hs5Stall",
                .desc = "The percentage of time in which hull stall pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile4__hs5_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF5 Bottleneck",
                .symbol_name = "Sf5Bottleneck",
                .desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile4__sf5_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF5 Stall",
                .symbol_name = "Sf5Stall",
                .desc = "The percentage of time in which strip-fans pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile4__sf5_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO5 Bottleneck",
                .symbol_name = "So5Bottleneck",
                .desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile4__so5_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO5 Stall",
                .symbol_name = "So5Stall",
                .desc = "The percentage of time in which stream-output pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile4__so5_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VF5 Bottleneck",
                .symbol_name = "Vf5Bottleneck",
                .desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile4__vf5_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VS5 Bottleneck",
                .symbol_name = "Vs5Bottleneck",
                .desc = "The percentage of time in which VS5 pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__render_pipe_profile4__vs5_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}


static void
acmgt2_add_l3_1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3_1";
    metric_set->symbol_name = "L3_1";
    metric_set->hw_config_guid = "2128b792-e30e-49ec-a64b-8a636364f728";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l3_1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l3_1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l3_1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_1__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l3_1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l3_1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Quad1 L3 Bank0 Input Available",
                .symbol_name = "L31Bank0InputAvailable",
                .desc = "The percentage of time in which Quad1 L3 bank0 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_1__l31_bank0_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank0 Output Ready",
                .symbol_name = "L31Bank0OutputReady",
                .desc = "The percentage of time in which quad1 L3 bank0 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_1__l31_bank0_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank1 Input Available",
                .symbol_name = "L31Bank1InputAvailable",
                .desc = "The percentage of time in which Quad1 L3 bank1 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_1__l31_bank1_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank1 Output Ready",
                .symbol_name = "L31Bank1OutputReady",
                .desc = "The percentage of time in which quad1 L3 bank1 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_1__l31_bank1_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank2 Input Available",
                .symbol_name = "L31Bank2InputAvailable",
                .desc = "The percentage of time in which Quad1 L3 bank2 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_1__l31_bank2_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank2 Output Ready",
                .symbol_name = "L31Bank2OutputReady",
                .desc = "The percentage of time in which quad1 L3 bank2 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_1__l31_bank2_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank3 Input Available",
                .symbol_name = "L31Bank3InputAvailable",
                .desc = "The percentage of time in which Quad1 L3 bank3 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_1__l31_bank3_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank3 Output Ready",
                .symbol_name = "L31Bank3OutputReady",
                .desc = "The percentage of time in which quad1 L3 bank3 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_1__l31_bank3_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank4 Input Available",
                .symbol_name = "L31Bank4InputAvailable",
                .desc = "The percentage of time in which Quad1 L3 bank4 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_1__l31_bank4_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank4 Output Ready",
                .symbol_name = "L31Bank4OutputReady",
                .desc = "The percentage of time in which quad1 L3 bank4 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_1__l31_bank4_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank5 Input Available",
                .symbol_name = "L31Bank5InputAvailable",
                .desc = "The percentage of time in which Quad1 L3 bank5 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_1__l31_bank5_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank5 Output Ready",
                .symbol_name = "L31Bank5OutputReady",
                .desc = "The percentage of time in which quad1 L3 bank5 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_1__l31_bank5_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank6 Input Available",
                .symbol_name = "L31Bank6InputAvailable",
                .desc = "The percentage of time in which Quad1 L3 bank6 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_1__l31_bank6_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank6 Output Ready",
                .symbol_name = "L31Bank6OutputReady",
                .desc = "The percentage of time in which quad1 L3 bank6 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_1__l31_bank6_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank7 Input Available",
                .symbol_name = "L31Bank7InputAvailable",
                .desc = "The percentage of time in which Quad1 L3 bank7 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_1__l31_bank7_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank7 Output Ready",
                .symbol_name = "L31Bank7OutputReady",
                .desc = "The percentage of time in which quad1 L3 bank7 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_1__l31_bank7_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}


static void
acmgt2_add_l3_2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3_2";
    metric_set->symbol_name = "L3_2";
    metric_set->hw_config_guid = "a70724fd-5214-4325-b32c-61b37f409efa";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l3_2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l3_2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l3_2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l3_2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l3_2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Quad2 L3 Bank0 Input Available",
                .symbol_name = "L32Bank0InputAvailable",
                .desc = "The percentage of time in which Quad2 L3 bank0 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_2__l32_bank0_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank0 Output Ready",
                .symbol_name = "L32Bank0OutputReady",
                .desc = "The percentage of time in which quad2 L3 bank0 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_2__l32_bank0_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank1 Input Available",
                .symbol_name = "L32Bank1InputAvailable",
                .desc = "The percentage of time in which Quad2 L3 bank1 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_2__l32_bank1_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank1 Output Ready",
                .symbol_name = "L32Bank1OutputReady",
                .desc = "The percentage of time in which quad2 L3 bank1 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_2__l32_bank1_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank2 Input Available",
                .symbol_name = "L32Bank2InputAvailable",
                .desc = "The percentage of time in which Quad2 L3 bank2 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_2__l32_bank2_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank2 Output Ready",
                .symbol_name = "L32Bank2OutputReady",
                .desc = "The percentage of time in which quad2 L3 bank2 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_2__l32_bank2_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank3 Input Available",
                .symbol_name = "L32Bank3InputAvailable",
                .desc = "The percentage of time in which Quad2 L3 bank3 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_2__l32_bank3_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank3 Output Ready",
                .symbol_name = "L32Bank3OutputReady",
                .desc = "The percentage of time in which quad2 L3 bank3 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_2__l32_bank3_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank4 Input Available",
                .symbol_name = "L32Bank4InputAvailable",
                .desc = "The percentage of time in which Quad2 L3 bank4 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_2__l32_bank4_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank4 Output Ready",
                .symbol_name = "L32Bank4OutputReady",
                .desc = "The percentage of time in which quad2 L3 bank4 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_2__l32_bank4_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank5 Input Available",
                .symbol_name = "L32Bank5InputAvailable",
                .desc = "The percentage of time in which Quad2 L3 bank5 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_2__l32_bank5_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank5 Output Ready",
                .symbol_name = "L32Bank5OutputReady",
                .desc = "The percentage of time in which quad2 L3 bank5 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_2__l32_bank5_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank6 Input Available",
                .symbol_name = "L32Bank6InputAvailable",
                .desc = "The percentage of time in which Quad2 L3 bank6 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_2__l32_bank6_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank6 Output Ready",
                .symbol_name = "L32Bank6OutputReady",
                .desc = "The percentage of time in which quad2 L3 bank6 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_2__l32_bank6_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank7 Input Available",
                .symbol_name = "L32Bank7InputAvailable",
                .desc = "The percentage of time in which Quad2 L3 bank7 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_2__l32_bank7_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank7 Output Ready",
                .symbol_name = "L32Bank7OutputReady",
                .desc = "The percentage of time in which quad2 L3 bank7 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_2__l32_bank7_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_sampler_1_Sampler20InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_1_Sampler20OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_1_Sampler21InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_1_Sampler21OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_1_Sampler22InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_1_Sampler22OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_1_Sampler23InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_1_Sampler23OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_1_Sampler30InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_1_Sampler30OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_1_Sampler31InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_1_Sampler31OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_1_Sampler32InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_1_Sampler32OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_1_Sampler33InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_1_Sampler33OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_sampler_1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Sampler_1";
    metric_set->symbol_name = "Sampler_1";
    metric_set->hw_config_guid = "167e0c1d-8ef2-44d3-b4fa-407b9a23eb5a";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_sampler_1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__sampler_1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__sampler_1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_1__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__sampler_1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__sampler_1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice2 Xe Core0 Input Available",
                .symbol_name = "Sampler20InputAvailable",
                .desc = "The percentage of time in which slice2 Xe core0 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_1__sampler20_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_1_Sampler20InputAvailable_availability,
            },

            {
                .name = "Slice2 Xe Core0 Sampler Output Ready",
                .symbol_name = "Sampler20OutputReady",
                .desc = "The percentage of time in which slice2 Xe core0 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_1__sampler20_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_1_Sampler20OutputReady_availability,
            },

            {
                .name = "Slice2 Xe Core1 Input Available",
                .symbol_name = "Sampler21InputAvailable",
                .desc = "The percentage of time in which slice2 Xe core1 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_1__sampler21_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_1_Sampler21InputAvailable_availability,
            },

            {
                .name = "Slice2 Xe Core1 Sampler Output Ready",
                .symbol_name = "Sampler21OutputReady",
                .desc = "The percentage of time in which slice2 Xe core1 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_1__sampler21_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_1_Sampler21OutputReady_availability,
            },

            {
                .name = "Slice2 Xe Core2 Input Available",
                .symbol_name = "Sampler22InputAvailable",
                .desc = "The percentage of time in which slice2 Xe core2 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_1__sampler22_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_1_Sampler22InputAvailable_availability,
            },

            {
                .name = "Slice2 Xe Core2 Sampler Output Ready",
                .symbol_name = "Sampler22OutputReady",
                .desc = "The percentage of time in which slice2 Xe core2 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_1__sampler22_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_1_Sampler22OutputReady_availability,
            },

            {
                .name = "Slice2 Xe Core3 Input Available",
                .symbol_name = "Sampler23InputAvailable",
                .desc = "The percentage of time in which slice2 Xe core3 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_1__sampler23_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_1_Sampler23InputAvailable_availability,
            },

            {
                .name = "Slice2 Xe Core3 Sampler Output Ready",
                .symbol_name = "Sampler23OutputReady",
                .desc = "The percentage of time in which slice2 Xe core3 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_1__sampler23_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_1_Sampler23OutputReady_availability,
            },

            {
                .name = "Slice3 Xe Core0 Input Available",
                .symbol_name = "Sampler30InputAvailable",
                .desc = "The percentage of time in which slice3 Xe core0 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_1__sampler30_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_1_Sampler30InputAvailable_availability,
            },

            {
                .name = "Slice3 Xe Core0 Sampler Output Ready",
                .symbol_name = "Sampler30OutputReady",
                .desc = "The percentage of time in which slice3 Xe core0 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_1__sampler30_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_1_Sampler30OutputReady_availability,
            },

            {
                .name = "Slice3 Xe Core1 Input Available",
                .symbol_name = "Sampler31InputAvailable",
                .desc = "The percentage of time in which slice3 Xe core1 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_1__sampler31_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_1_Sampler31InputAvailable_availability,
            },

            {
                .name = "Slice3 Xe Core1 Sampler Output Ready",
                .symbol_name = "Sampler31OutputReady",
                .desc = "The percentage of time in which slice3 Xe core1 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_1__sampler31_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_1_Sampler31OutputReady_availability,
            },

            {
                .name = "Slice3 Xe Core2 Input Available",
                .symbol_name = "Sampler32InputAvailable",
                .desc = "The percentage of time in which slice3 Xe core2 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_1__sampler32_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_1_Sampler32InputAvailable_availability,
            },

            {
                .name = "Slice3 Xe Core2 Sampler Output Ready",
                .symbol_name = "Sampler32OutputReady",
                .desc = "The percentage of time in which slice3 Xe core2 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_1__sampler32_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_1_Sampler32OutputReady_availability,
            },

            {
                .name = "Slice3 Xe Core3 Input Available",
                .symbol_name = "Sampler33InputAvailable",
                .desc = "The percentage of time in which slice3 Xe core3 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_1__sampler33_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_1_Sampler33InputAvailable_availability,
            },

            {
                .name = "Slice3 Xe Core3 Sampler Output Ready",
                .symbol_name = "Sampler33OutputReady",
                .desc = "The percentage of time in which slice3 Xe core3 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_1__sampler33_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_1_Sampler33OutputReady_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt2_sampler_2_Sampler40InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_2_Sampler40OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_2_Sampler41InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_2_Sampler41OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_2_Sampler42InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_2_Sampler42OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_2_Sampler43InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_2_Sampler43OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_2_Sampler50InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_2_Sampler50OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_2_Sampler51InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_2_Sampler51OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_2_Sampler52InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_2_Sampler52OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_2_Sampler53InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler_2_Sampler53OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_sampler_2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Sampler_2";
    metric_set->symbol_name = "Sampler_2";
    metric_set->hw_config_guid = "879e3747-17f6-40b8-9a7a-2c6752ff6d6c";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_sampler_2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__sampler_2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__sampler_2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_2__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__sampler_2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__sampler_2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice4 Xe Core0 Input Available",
                .symbol_name = "Sampler40InputAvailable",
                .desc = "The percentage of time in which slice4 Xe core0 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_2__sampler40_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_2_Sampler40InputAvailable_availability,
            },

            {
                .name = "Slice4 Xe Core0 Sampler Output Ready",
                .symbol_name = "Sampler40OutputReady",
                .desc = "The percentage of time in which slice4 Xe core0 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_2__sampler40_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_2_Sampler40OutputReady_availability,
            },

            {
                .name = "Slice4 Xe Core1 Input Available",
                .symbol_name = "Sampler41InputAvailable",
                .desc = "The percentage of time in which slice4 Xe core1 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_2__sampler41_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_2_Sampler41InputAvailable_availability,
            },

            {
                .name = "Slice4 Xe Core1 Sampler Output Ready",
                .symbol_name = "Sampler41OutputReady",
                .desc = "The percentage of time in which slice4 Xe core1 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_2__sampler41_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_2_Sampler41OutputReady_availability,
            },

            {
                .name = "Slice4 Xe Core2 Input Available",
                .symbol_name = "Sampler42InputAvailable",
                .desc = "The percentage of time in which slice4 Xe core2 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_2__sampler42_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_2_Sampler42InputAvailable_availability,
            },

            {
                .name = "Slice4 Xe Core2 Sampler Output Ready",
                .symbol_name = "Sampler42OutputReady",
                .desc = "The percentage of time in which slice4 Xe core2 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_2__sampler42_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_2_Sampler42OutputReady_availability,
            },

            {
                .name = "Slice4 Xe Core3 Input Available",
                .symbol_name = "Sampler43InputAvailable",
                .desc = "The percentage of time in which slice4 Xe core3 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_2__sampler43_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_2_Sampler43InputAvailable_availability,
            },

            {
                .name = "Slice4 Xe Core3 Sampler Output Ready",
                .symbol_name = "Sampler43OutputReady",
                .desc = "The percentage of time in which slice4 Xe core3 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_2__sampler43_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_2_Sampler43OutputReady_availability,
            },

            {
                .name = "Slice5 Xe Core0 Input Available",
                .symbol_name = "Sampler50InputAvailable",
                .desc = "The percentage of time in which slice5 Xe core0 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_2__sampler50_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_2_Sampler50InputAvailable_availability,
            },

            {
                .name = "Slice5 Xe Core0 Sampler Output Ready",
                .symbol_name = "Sampler50OutputReady",
                .desc = "The percentage of time in which slice5 Xe core0 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_2__sampler50_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_2_Sampler50OutputReady_availability,
            },

            {
                .name = "Slice5 Xe Core1 Input Available",
                .symbol_name = "Sampler51InputAvailable",
                .desc = "The percentage of time in which slice5 Xe core1 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_2__sampler51_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_2_Sampler51InputAvailable_availability,
            },

            {
                .name = "Slice5 Xe Core1 Sampler Output Ready",
                .symbol_name = "Sampler51OutputReady",
                .desc = "The percentage of time in which slice5 Xe core1 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_2__sampler51_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_2_Sampler51OutputReady_availability,
            },

            {
                .name = "Slice5 Xe Core2 Input Available",
                .symbol_name = "Sampler52InputAvailable",
                .desc = "The percentage of time in which slice5 Xe core2 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_2__sampler52_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_2_Sampler52InputAvailable_availability,
            },

            {
                .name = "Slice5 Xe Core2 Sampler Output Ready",
                .symbol_name = "Sampler52OutputReady",
                .desc = "The percentage of time in which slice5 Xe core2 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_2__sampler52_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_2_Sampler52OutputReady_availability,
            },

            {
                .name = "Slice5 Xe Core3 Input Available",
                .symbol_name = "Sampler53InputAvailable",
                .desc = "The percentage of time in which slice5 Xe core3 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_2__sampler53_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_2_Sampler53InputAvailable_availability,
            },

            {
                .name = "Slice5 Xe Core3 Sampler Output Ready",
                .symbol_name = "Sampler53OutputReady",
                .desc = "The percentage of time in which slice5 Xe core3 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler_2__sampler53_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler_2_Sampler53OutputReady_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt2_hdc_and_sf1_NonSamplerShader20AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_hdc_and_sf1_NonSamplerShader21AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_hdc_and_sf1_NonSamplerShader22AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_hdc_and_sf1_NonSamplerShader23AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_hdc_and_sf1_NonSamplerShader30AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_hdc_and_sf1_NonSamplerShader31AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_hdc_and_sf1_NonSamplerShader32AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_hdc_and_sf1_NonSamplerShader33AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_hdc_and_sf1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set HDCAndSF1";
    metric_set->symbol_name = "HDCAndSF1";
    metric_set->hw_config_guid = "55aebe75-d0e0-4d07-aa50-4b1e672341a7";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_hdc_and_sf1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__hdc_and_sf1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__hdc_and_sf1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf1__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__hdc_and_sf1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__hdc_and_sf1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice2 Xe Core0 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader20AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice2 Xe Core0)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf1__non_sampler_shader20_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_hdc_and_sf1_NonSamplerShader20AccessStalledOnL3_availability,
            },

            {
                .name = "Slice2 Xe Core1 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader21AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice2 Xe Core1)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf1__non_sampler_shader21_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_hdc_and_sf1_NonSamplerShader21AccessStalledOnL3_availability,
            },

            {
                .name = "Slice2 Xe Core2 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader22AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice2 Xe Core2)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf1__non_sampler_shader22_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_hdc_and_sf1_NonSamplerShader22AccessStalledOnL3_availability,
            },

            {
                .name = "Slice2 Xe Core3 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader23AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice2 Xe Core3)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf1__non_sampler_shader23_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_hdc_and_sf1_NonSamplerShader23AccessStalledOnL3_availability,
            },

            {
                .name = "Slice3 Xe Core0 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader30AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice3 Xe Core0)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf1__non_sampler_shader30_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_hdc_and_sf1_NonSamplerShader30AccessStalledOnL3_availability,
            },

            {
                .name = "Slice3 Xe Core1 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader31AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice3 Xe Core1)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf1__non_sampler_shader31_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_hdc_and_sf1_NonSamplerShader31AccessStalledOnL3_availability,
            },

            {
                .name = "Slice3 Xe Core2 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader32AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice3 Xe Core2)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf1__non_sampler_shader32_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_hdc_and_sf1_NonSamplerShader32AccessStalledOnL3_availability,
            },

            {
                .name = "Slice3 Xe Core3 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader33AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice3 Xe Core3)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf1__non_sampler_shader33_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_hdc_and_sf1_NonSamplerShader33AccessStalledOnL3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}


static void
acmgt2_add_hdc_and_sf2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set HDCAndSF2";
    metric_set->symbol_name = "HDCAndSF2";
    metric_set->hw_config_guid = "d9c30016-f7b6-4c66-81e1-cb75b68a2222";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_hdc_and_sf2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__hdc_and_sf2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__hdc_and_sf2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "SQ20 is full",
                .symbol_name = "GTRequestQueue20Full",
                .desc = "The percentage of time when IDI0 SQ20 is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf2__gt_request_queue20_full__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "SQ30 is full",
                .symbol_name = "GTRequestQueue30Full",
                .desc = "The percentage of time when IDI0 SQ30 is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf2__gt_request_queue30_full__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "SQ40 is full",
                .symbol_name = "GTRequestQueue40Full",
                .desc = "The percentage of time when IDI0 SQ40 is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf2__gt_request_queue40_full__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "SQ50 is full",
                .symbol_name = "GTRequestQueue50Full",
                .desc = "The percentage of time when IDI0 SQ50 is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf2__gt_request_queue50_full__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf2__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__hdc_and_sf2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__hdc_and_sf2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Polygon (Slice2) Data Ready",
                .symbol_name = "Poly2DataReady",
                .desc = "The percentage of time in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf2__poly2_data_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Polygon (Slice3) Data Ready",
                .symbol_name = "Poly3DataReady",
                .desc = "The percentage of time in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf2__poly3_data_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Polygon (Slice4) Data Ready",
                .symbol_name = "Poly4DataReady",
                .desc = "The percentage of time in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf2__poly4_data_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Polygon (Slice5) Data Ready",
                .symbol_name = "Poly5DataReady",
                .desc = "The percentage of time in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf2__poly5_data_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt2_hdc_and_sf3_NonSamplerShader40AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_hdc_and_sf3_NonSamplerShader41AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_hdc_and_sf3_NonSamplerShader42AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_hdc_and_sf3_NonSamplerShader43AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_hdc_and_sf3_NonSamplerShader50AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_hdc_and_sf3_NonSamplerShader51AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_hdc_and_sf3_NonSamplerShader52AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_hdc_and_sf3_NonSamplerShader53AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_hdc_and_sf3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "HDCAndSF3";
    metric_set->symbol_name = "HDCAndSF3";
    metric_set->hw_config_guid = "6357cd3a-3553-4a60-8c86-7c59347c3916";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_hdc_and_sf3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__hdc_and_sf3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__hdc_and_sf3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf3__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__hdc_and_sf3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__hdc_and_sf3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice4 Xe Core0 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader40AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice4 Xe Core0)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf3__non_sampler_shader40_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_hdc_and_sf3_NonSamplerShader40AccessStalledOnL3_availability,
            },

            {
                .name = "Slice4 Xe Core1 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader41AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice4 Xe Core1)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf3__non_sampler_shader41_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_hdc_and_sf3_NonSamplerShader41AccessStalledOnL3_availability,
            },

            {
                .name = "Slice4 Xe Core2 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader42AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice4 Xe Core2)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf3__non_sampler_shader42_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_hdc_and_sf3_NonSamplerShader42AccessStalledOnL3_availability,
            },

            {
                .name = "Slice4 Xe Core3 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader43AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice4 Xe Core3)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf3__non_sampler_shader43_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_hdc_and_sf3_NonSamplerShader43AccessStalledOnL3_availability,
            },

            {
                .name = "Slice5 Xe Core0 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader50AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice5 Xe Core0)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf3__non_sampler_shader50_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_hdc_and_sf3_NonSamplerShader50AccessStalledOnL3_availability,
            },

            {
                .name = "Slice5 Xe Core1 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader51AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice5 Xe Core1)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf3__non_sampler_shader51_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_hdc_and_sf3_NonSamplerShader51AccessStalledOnL3_availability,
            },

            {
                .name = "Slice5 Xe Core2 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader52AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice5 Xe Core2)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf3__non_sampler_shader52_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_hdc_and_sf3_NonSamplerShader52AccessStalledOnL3_availability,
            },

            {
                .name = "Slice5 Xe Core3 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader53AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice5 Xe Core3)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__hdc_and_sf3__non_sampler_shader53_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_hdc_and_sf3_NonSamplerShader53AccessStalledOnL3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt2_rasterizer_and_pixel_backend1_Rasterizer2InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_rasterizer_and_pixel_backend1_Rasterizer3OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_rasterizer_and_pixel_backend1_Rasterizer4InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_rasterizer_and_pixel_backend1_Rasterizer5OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_rasterizer_and_pixel_backend1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set RasterizerAndPixelBackend1";
    metric_set->symbol_name = "RasterizerAndPixelBackend1";
    metric_set->hw_config_guid = "031a7f13-0f25-4794-958d-38cea3050a32";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_rasterizer_and_pixel_backend1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend1__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__rasterizer_and_pixel_backend1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__rasterizer_and_pixel_backend1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice2 Pipe0 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData20Ready",
                .desc = "The percentage of time in which slice2  pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend1__pixel_data20_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice2 Pipe1 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData21Ready",
                .desc = "The percentage of time in which slice2  pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend1__pixel_data21_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice3 Pipe0 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData30Ready",
                .desc = "The percentage of time in which slice3  pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend1__pixel_data30_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice3 Pipe1 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData31Ready",
                .desc = "The percentage of time in which slice3  pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend1__pixel_data31_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice2 Rasterizer Input Available",
                .symbol_name = "Rasterizer2InputAvailable",
                .desc = "The percentage of time in which slice2 rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend1__rasterizer2_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt2_rasterizer_and_pixel_backend1_Rasterizer2InputAvailable_availability,
            },

            {
                .name = "Slice3 Rasterizer Output Ready",
                .symbol_name = "Rasterizer3OutputReady",
                .desc = "The percentage of time in which slice3 rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend1__rasterizer3_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt2_rasterizer_and_pixel_backend1_Rasterizer3OutputReady_availability,
            },

            {
                .name = "Slice4 Rasterizer Input Available",
                .symbol_name = "Rasterizer4InputAvailable",
                .desc = "The percentage of time in which slice4 rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend1__rasterizer4_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt2_rasterizer_and_pixel_backend1_Rasterizer4InputAvailable_availability,
            },

            {
                .name = "Slice5 Rasterizer Output Ready",
                .symbol_name = "Rasterizer5OutputReady",
                .desc = "The percentage of time in which slice5 rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend1__rasterizer5_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt2_rasterizer_and_pixel_backend1_Rasterizer5OutputReady_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt2_rasterizer_and_pixel_backend2_Rasterizer2OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_rasterizer_and_pixel_backend2_Rasterizer3InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_rasterizer_and_pixel_backend2_Rasterizer4OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_rasterizer_and_pixel_backend2_Rasterizer5InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_rasterizer_and_pixel_backend2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set RasterizerAndPixelBackend2";
    metric_set->symbol_name = "RasterizerAndPixelBackend2";
    metric_set->hw_config_guid = "2032fb37-ebc9-4eb6-8916-4550474edd5d";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_rasterizer_and_pixel_backend2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend2__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__rasterizer_and_pixel_backend2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__rasterizer_and_pixel_backend2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice4 Pipe0 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData40Ready",
                .desc = "The percentage of time in which slice4  pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend2__pixel_data40_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice4 Pipe1 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData41Ready",
                .desc = "The percentage of time in which slice4  pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend2__pixel_data41_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice5 Pipe0 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData50Ready",
                .desc = "The percentage of time in which slice5  pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend2__pixel_data50_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice5 Pipe1 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData51Ready",
                .desc = "The percentage of time in which slice5  pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend2__pixel_data51_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice2 Rasterizer Output Ready",
                .symbol_name = "Rasterizer2OutputReady",
                .desc = "The percentage of time in which slice2 rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend2__rasterizer2_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt2_rasterizer_and_pixel_backend2_Rasterizer2OutputReady_availability,
            },

            {
                .name = "Slice3 Rasterizer Input Available",
                .symbol_name = "Rasterizer3InputAvailable",
                .desc = "The percentage of time in which slice3 rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend2__rasterizer3_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt2_rasterizer_and_pixel_backend2_Rasterizer3InputAvailable_availability,
            },

            {
                .name = "Slice4 Rasterizer Output Ready",
                .symbol_name = "Rasterizer4OutputReady",
                .desc = "The percentage of time in which slice4 rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend2__rasterizer4_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt2_rasterizer_and_pixel_backend2_Rasterizer4OutputReady_availability,
            },

            {
                .name = "Slice5 Rasterizer Input Available",
                .symbol_name = "Rasterizer5InputAvailable",
                .desc = "The percentage of time in which slice5 rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend2__rasterizer5_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt2_rasterizer_and_pixel_backend2_Rasterizer5InputAvailable_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}


static void
acmgt2_add_rasterizer_and_pixel_backend3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RasterizerAndPixelBackend3";
    metric_set->symbol_name = "RasterizerAndPixelBackend3";
    metric_set->hw_config_guid = "51bc5454-ff6e-4033-b8b0-c9734975b3d4";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_rasterizer_and_pixel_backend3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__rasterizer_and_pixel_backend3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__rasterizer_and_pixel_backend3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__rasterizer_and_pixel_backend3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__rasterizer_and_pixel_backend3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PS10 Output Available",
                .symbol_name = "PSOutput10Available",
                .desc = "The percentage of time in which PS10 output is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend3__ps_output10_available__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "PS11 Output Available",
                .symbol_name = "PSOutput11Available",
                .desc = "The percentage of time in which PS11 output is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend3__ps_output11_available__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "PS20 Output Available",
                .symbol_name = "PSOutput20Available",
                .desc = "The percentage of time in which PS20 output is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend3__ps_output20_available__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "PS21 Output Available",
                .symbol_name = "PSOutput21Available",
                .desc = "The percentage of time in which PS21 output is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend3__ps_output21_available__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "Pixel Values 10 Ready",
                .symbol_name = "PixelValues10Ready",
                .desc = "The percentage of time in which pixel values 10 are ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend3__pixel_values10_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "Pixel Values 11 Ready",
                .symbol_name = "PixelValues11Ready",
                .desc = "The percentage of time in which pixel values 11 are ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend3__pixel_values11_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "Pixel Values 20 Ready",
                .symbol_name = "PixelValues20Ready",
                .desc = "The percentage of time in which pixel values 20 are ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend3__pixel_values20_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "Pixel Values 21 Ready",
                .symbol_name = "PixelValues21Ready",
                .desc = "The percentage of time in which pixel values 21 are ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer_and_pixel_backend3__pixel_values21_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_tdl1_NonPSThread20ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl1_NonPSThread21ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl1_NonPSThread22ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl1_NonPSThread23ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl1_NonPSThread30ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl1_NonPSThread31ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl1_NonPSThread32ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl1_NonPSThread33ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl1_ThreadHeader23ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl1_ThreadHeader23ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl1_ThreadHeader23ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl1_ThreadHeader23ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl1_ThreadHeader33ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl1_ThreadHeader33ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl1_ThreadHeader33ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl1_ThreadHeader33ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_tdl1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL1";
    metric_set->symbol_name = "TDL1";
    metric_set->hw_config_guid = "5b08d0b8-c976-4d7b-b770-8f538bee394a";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_tdl1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__tdl1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__tdl1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl1__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__tdl1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__tdl1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice2 Xe Core0 Thread Dispatcher",
                .symbol_name = "NonPSThread20ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice2 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl1__non_ps_thread20_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl1_NonPSThread20ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice2 Xe Core1 Thread Dispatcher",
                .symbol_name = "NonPSThread21ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice2 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl1__non_ps_thread21_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl1_NonPSThread21ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice2 Xe Core2 Thread Dispatcher",
                .symbol_name = "NonPSThread22ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice2 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl1__non_ps_thread22_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl1_NonPSThread22ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice2 Xe Core3 Thread Dispatcher",
                .symbol_name = "NonPSThread23ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice2 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl1__non_ps_thread23_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl1_NonPSThread23ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice3 Xe Core0 Thread Dispatcher",
                .symbol_name = "NonPSThread30ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice3 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl1__non_ps_thread30_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl1_NonPSThread30ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice3 Xe Core1 Thread Dispatcher",
                .symbol_name = "NonPSThread31ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice3 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl1__non_ps_thread31_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl1_NonPSThread31ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice3 Xe Core2 Thread Dispatcher",
                .symbol_name = "NonPSThread32ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice3 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl1__non_ps_thread32_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl1_NonPSThread32ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice3 Xe Core3 Thread Dispatcher",
                .symbol_name = "NonPSThread33ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice3 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl1__non_ps_thread33_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl1_NonPSThread33ReadyForDispatch_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader23ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl1__thread_header23_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl1_ThreadHeader23ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader23ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl1__thread_header23_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl1_ThreadHeader23ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader23ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl1__thread_header23_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl1_ThreadHeader23ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader23ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl1__thread_header23_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl1_ThreadHeader23ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader33ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl1__thread_header33_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl1_ThreadHeader33ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader33ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl1__thread_header33_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl1_ThreadHeader33ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader33ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl1__thread_header33_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl1_ThreadHeader33ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader33ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl1__thread_header33_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl1_ThreadHeader33ReadyPort3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt2_tdl2_PSThread20ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl2_PSThread21ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl2_PSThread22ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl2_PSThread23ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl2_PSThread30ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl2_PSThread31ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl2_PSThread32ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl2_PSThread33ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_tdl2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL2";
    metric_set->symbol_name = "TDL2";
    metric_set->hw_config_guid = "27ee6bcc-1378-4046-8922-124ea2115039";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_tdl2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__tdl2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__tdl2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl2__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__tdl2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__tdl2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice2 Xe Core0 Thread Dispatcher",
                .symbol_name = "PSThread20ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice2 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl2__ps_thread20_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl2_PSThread20ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice2 Xe Core1 Thread Dispatcher",
                .symbol_name = "PSThread21ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice2 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl2__ps_thread21_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl2_PSThread21ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice2 Xe Core2 Thread Dispatcher",
                .symbol_name = "PSThread22ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice2 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl2__ps_thread22_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl2_PSThread22ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice2 Xe Core3 Thread Dispatcher",
                .symbol_name = "PSThread23ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice2 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl2__ps_thread23_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl2_PSThread23ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice3 Xe Core0 Thread Dispatcher",
                .symbol_name = "PSThread30ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice3 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl2__ps_thread30_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl2_PSThread30ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice3 Xe Core1 Thread Dispatcher",
                .symbol_name = "PSThread31ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice3 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl2__ps_thread31_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl2_PSThread31ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice3 Xe Core2 Thread Dispatcher",
                .symbol_name = "PSThread32ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice3 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl2__ps_thread32_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl2_PSThread32ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice3 Xe Core3 Thread Dispatcher",
                .symbol_name = "PSThread33ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice3 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl2__ps_thread33_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl2_PSThread33ReadyForDispatch_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt2_tdl3_ThreadHeader20Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl3_ThreadHeader20ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl3_ThreadHeader20ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl3_ThreadHeader20ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl3_ThreadHeader20ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl3_ThreadHeader21Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl3_ThreadHeader21ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl3_ThreadHeader21ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl3_ThreadHeader21ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl3_ThreadHeader21ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl3_ThreadHeader22Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl3_ThreadHeader22ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl3_ThreadHeader22ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl3_ThreadHeader22ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl3_ThreadHeader22ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl3_ThreadHeader23Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_tdl3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL3";
    metric_set->symbol_name = "TDL3";
    metric_set->hw_config_guid = "dd909127-caff-408f-994f-e0f64a672918";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_tdl3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__tdl3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__tdl3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl3__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__tdl3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__tdl3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher",
                .symbol_name = "ThreadHeader20Ready",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl3__thread_header20_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl3_ThreadHeader20Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader20ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl3__thread_header20_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl3_ThreadHeader20ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader20ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl3__thread_header20_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl3_ThreadHeader20ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader20ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl3__thread_header20_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl3_ThreadHeader20ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader20ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl3__thread_header20_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl3_ThreadHeader20ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher",
                .symbol_name = "ThreadHeader21Ready",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl3__thread_header21_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl3_ThreadHeader21Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader21ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl3__thread_header21_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl3_ThreadHeader21ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader21ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl3__thread_header21_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl3_ThreadHeader21ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader21ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl3__thread_header21_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl3_ThreadHeader21ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader21ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl3__thread_header21_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl3_ThreadHeader21ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher",
                .symbol_name = "ThreadHeader22Ready",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl3__thread_header22_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl3_ThreadHeader22Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader22ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl3__thread_header22_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl3_ThreadHeader22ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader22ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl3__thread_header22_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl3_ThreadHeader22ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader22ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl3__thread_header22_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl3_ThreadHeader22ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader22ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl3__thread_header22_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl3_ThreadHeader22ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher",
                .symbol_name = "ThreadHeader23Ready",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl3__thread_header23_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl3_ThreadHeader23Ready_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt2_tdl4_ThreadHeader30Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl4_ThreadHeader30ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl4_ThreadHeader30ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl4_ThreadHeader30ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl4_ThreadHeader30ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl4_ThreadHeader31Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl4_ThreadHeader31ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl4_ThreadHeader31ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl4_ThreadHeader31ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl4_ThreadHeader31ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl4_ThreadHeader32Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl4_ThreadHeader32ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl4_ThreadHeader32ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl4_ThreadHeader32ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl4_ThreadHeader32ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl4_ThreadHeader33Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_tdl4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL4";
    metric_set->symbol_name = "TDL4";
    metric_set->hw_config_guid = "64fae233-cafe-4594-ab7b-fcbf5b442933";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_tdl4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__tdl4__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__tdl4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl4__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__tdl4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__tdl4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher",
                .symbol_name = "ThreadHeader30Ready",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl4__thread_header30_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl4_ThreadHeader30Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader30ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl4__thread_header30_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl4_ThreadHeader30ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader30ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl4__thread_header30_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl4_ThreadHeader30ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader30ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl4__thread_header30_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl4_ThreadHeader30ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader30ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl4__thread_header30_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl4_ThreadHeader30ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher",
                .symbol_name = "ThreadHeader31Ready",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl4__thread_header31_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl4_ThreadHeader31Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader31ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl4__thread_header31_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl4_ThreadHeader31ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader31ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl4__thread_header31_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl4_ThreadHeader31ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader31ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl4__thread_header31_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl4_ThreadHeader31ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader31ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl4__thread_header31_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl4_ThreadHeader31ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher",
                .symbol_name = "ThreadHeader32Ready",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl4__thread_header32_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl4_ThreadHeader32Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader32ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl4__thread_header32_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl4_ThreadHeader32ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader32ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl4__thread_header32_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl4_ThreadHeader32ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader32ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl4__thread_header32_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl4_ThreadHeader32ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader32ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl4__thread_header32_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl4_ThreadHeader32ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher",
                .symbol_name = "ThreadHeader33Ready",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl4__thread_header33_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl4_ThreadHeader33Ready_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt2_tdl5_NonPSThread40ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl5_NonPSThread41ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl5_NonPSThread42ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl5_NonPSThread43ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl5_NonPSThread50ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl5_NonPSThread51ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl5_NonPSThread52ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl5_NonPSThread53ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl5_ThreadHeader43ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl5_ThreadHeader43ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl5_ThreadHeader43ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl5_ThreadHeader43ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl5_ThreadHeader53ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl5_ThreadHeader53ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl5_ThreadHeader53ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl5_ThreadHeader53ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_tdl5_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL5";
    metric_set->symbol_name = "TDL5";
    metric_set->hw_config_guid = "063f5cea-f9ba-4c93-b7e8-22dc5c05060e";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_tdl5_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__tdl5__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__tdl5__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl5__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__tdl5__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__tdl5__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice4 Xe Core0 Thread Dispatcher",
                .symbol_name = "NonPSThread40ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice4 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl5__non_ps_thread40_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl5_NonPSThread40ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice4 Xe Core1 Thread Dispatcher",
                .symbol_name = "NonPSThread41ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice4 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl5__non_ps_thread41_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl5_NonPSThread41ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice4 Xe Core2 Thread Dispatcher",
                .symbol_name = "NonPSThread42ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice4 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl5__non_ps_thread42_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl5_NonPSThread42ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice4 Xe Core3 Thread Dispatcher",
                .symbol_name = "NonPSThread43ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice4 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl5__non_ps_thread43_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl5_NonPSThread43ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice5 Xe Core0 Thread Dispatcher",
                .symbol_name = "NonPSThread50ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice5 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl5__non_ps_thread50_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl5_NonPSThread50ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice5 Xe Core1 Thread Dispatcher",
                .symbol_name = "NonPSThread51ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice5 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl5__non_ps_thread51_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl5_NonPSThread51ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice5 Xe Core2 Thread Dispatcher",
                .symbol_name = "NonPSThread52ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice5 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl5__non_ps_thread52_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl5_NonPSThread52ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice5 Xe Core3 Thread Dispatcher",
                .symbol_name = "NonPSThread53ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice5 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl5__non_ps_thread53_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl5_NonPSThread53ReadyForDispatch_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core3 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader43ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core3 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl5__thread_header43_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl5_ThreadHeader43ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core3 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader43ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core3 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl5__thread_header43_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl5_ThreadHeader43ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core3 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader43ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core3 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl5__thread_header43_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl5_ThreadHeader43ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core3 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader43ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core3 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl5__thread_header43_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl5_ThreadHeader43ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core3 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader53ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core3 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl5__thread_header53_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl5_ThreadHeader53ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core3 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader53ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core3 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl5__thread_header53_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl5_ThreadHeader53ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core3 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader53ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core3 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl5__thread_header53_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl5_ThreadHeader53ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core3 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader53ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core3 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl5__thread_header53_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl5_ThreadHeader53ReadyPort3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt2_tdl6_PSThread40ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl6_PSThread41ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl6_PSThread42ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl6_PSThread43ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl6_PSThread50ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl6_PSThread51ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl6_PSThread52ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl6_PSThread53ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_tdl6_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL6";
    metric_set->symbol_name = "TDL6";
    metric_set->hw_config_guid = "4cba20e7-78ea-4aaf-bd5d-42b8647cf778";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_tdl6_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__tdl6__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__tdl6__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl6__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__tdl6__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__tdl6__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice4 Xe Core0 Thread Dispatcher",
                .symbol_name = "PSThread40ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice4 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl6__ps_thread40_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl6_PSThread40ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice4 Xe Core1 Thread Dispatcher",
                .symbol_name = "PSThread41ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice4 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl6__ps_thread41_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl6_PSThread41ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice4 Xe Core2 Thread Dispatcher",
                .symbol_name = "PSThread42ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice4 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl6__ps_thread42_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl6_PSThread42ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice4 Xe Core3 Thread Dispatcher",
                .symbol_name = "PSThread43ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice4 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl6__ps_thread43_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl6_PSThread43ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice5 Xe Core0 Thread Dispatcher",
                .symbol_name = "PSThread50ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice5 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl6__ps_thread50_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl6_PSThread50ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice5 Xe Core1 Thread Dispatcher",
                .symbol_name = "PSThread51ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice5 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl6__ps_thread51_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl6_PSThread51ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice5 Xe Core2 Thread Dispatcher",
                .symbol_name = "PSThread52ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice5 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl6__ps_thread52_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl6_PSThread52ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice5 Xe Core3 Thread Dispatcher",
                .symbol_name = "PSThread53ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice5 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl6__ps_thread53_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl6_PSThread53ReadyForDispatch_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt2_tdl7_ThreadHeader40Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl7_ThreadHeader40ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl7_ThreadHeader40ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl7_ThreadHeader40ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl7_ThreadHeader40ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl7_ThreadHeader41Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl7_ThreadHeader41ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl7_ThreadHeader41ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl7_ThreadHeader41ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl7_ThreadHeader41ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl7_ThreadHeader42Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl7_ThreadHeader42ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl7_ThreadHeader42ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl7_ThreadHeader42ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl7_ThreadHeader42ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl7_ThreadHeader43Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_tdl7_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL7";
    metric_set->symbol_name = "TDL7";
    metric_set->hw_config_guid = "f76dee3e-b215-4780-9c83-7a1dfb1a6e63";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_tdl7_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__tdl7__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__tdl7__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl7__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__tdl7__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__tdl7__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core0 Thread Dispatcher",
                .symbol_name = "ThreadHeader40Ready",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl7__thread_header40_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl7_ThreadHeader40Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core0 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader40ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core0 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl7__thread_header40_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl7_ThreadHeader40ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core0 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader40ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core0 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl7__thread_header40_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl7_ThreadHeader40ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core0 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader40ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core0 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl7__thread_header40_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl7_ThreadHeader40ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core0 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader40ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core0 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl7__thread_header40_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl7_ThreadHeader40ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core1 Thread Dispatcher",
                .symbol_name = "ThreadHeader41Ready",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl7__thread_header41_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl7_ThreadHeader41Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core1 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader41ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core1 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl7__thread_header41_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl7_ThreadHeader41ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core1 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader41ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core1 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl7__thread_header41_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl7_ThreadHeader41ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core1 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader41ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core1 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl7__thread_header41_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl7_ThreadHeader41ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core1 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader41ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core1 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl7__thread_header41_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl7_ThreadHeader41ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core2 Thread Dispatcher",
                .symbol_name = "ThreadHeader42Ready",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl7__thread_header42_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl7_ThreadHeader42Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core2 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader42ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core2 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl7__thread_header42_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl7_ThreadHeader42ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core2 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader42ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core2 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl7__thread_header42_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl7_ThreadHeader42ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core2 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader42ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core2 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl7__thread_header42_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl7_ThreadHeader42ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core2 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader42ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core2 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl7__thread_header42_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl7_ThreadHeader42ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core3 Thread Dispatcher",
                .symbol_name = "ThreadHeader43Ready",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl7__thread_header43_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl7_ThreadHeader43Ready_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt2_tdl8_ThreadHeader50Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl8_ThreadHeader50ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl8_ThreadHeader50ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl8_ThreadHeader50ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl8_ThreadHeader50ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl8_ThreadHeader51Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl8_ThreadHeader51ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl8_ThreadHeader51ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl8_ThreadHeader51ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl8_ThreadHeader51ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl8_ThreadHeader52Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl8_ThreadHeader52ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl8_ThreadHeader52ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl8_ThreadHeader52ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl8_ThreadHeader52ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_tdl8_ThreadHeader53Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_tdl8_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL8";
    metric_set->symbol_name = "TDL8";
    metric_set->hw_config_guid = "70a8e39e-5244-43ea-b922-bd7024baf879";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_tdl8_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__tdl8__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__tdl8__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl8__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__tdl8__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__tdl8__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core0 Thread Dispatcher",
                .symbol_name = "ThreadHeader50Ready",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl8__thread_header50_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl8_ThreadHeader50Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core0 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader50ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core0 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl8__thread_header50_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl8_ThreadHeader50ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core0 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader50ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core0 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl8__thread_header50_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl8_ThreadHeader50ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core0 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader50ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core0 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl8__thread_header50_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl8_ThreadHeader50ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core0 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader50ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core0 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl8__thread_header50_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl8_ThreadHeader50ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core1 Thread Dispatcher",
                .symbol_name = "ThreadHeader51Ready",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl8__thread_header51_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl8_ThreadHeader51Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core1 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader51ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core1 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl8__thread_header51_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl8_ThreadHeader51ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core1 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader51ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core1 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl8__thread_header51_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl8_ThreadHeader51ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core1 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader51ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core1 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl8__thread_header51_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl8_ThreadHeader51ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core1 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader51ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core1 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl8__thread_header51_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl8_ThreadHeader51ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core2 Thread Dispatcher",
                .symbol_name = "ThreadHeader52Ready",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl8__thread_header52_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl8_ThreadHeader52Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core2 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader52ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core2 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl8__thread_header52_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl8_ThreadHeader52ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core2 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader52ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core2 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl8__thread_header52_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl8_ThreadHeader52ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core2 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader52ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core2 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl8__thread_header52_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl8_ThreadHeader52ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core2 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader52ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core2 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl8__thread_header52_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl8_ThreadHeader52ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core3 Thread Dispatcher",
                .symbol_name = "ThreadHeader53Ready",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__tdl8__thread_header53_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_tdl8_ThreadHeader53Ready_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}


static void
acmgt2_add_test_oa_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set TestOa";
    metric_set->symbol_name = "TestOa";
    metric_set->hw_config_guid = "cfac9130-4f6a-4a2a-aafc-9e88751ce983";
    metric_set->counters = calloc(13, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_test_oa_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__test_oa__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__test_oa__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "TestCounter0",
                .symbol_name = "Counter0",
                .desc = "HW test counter 0. Factor: 0.0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__test_oa__counter0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter1",
                .symbol_name = "Counter1",
                .desc = "HW test counter 1. Factor: 1.0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__test_oa__counter1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter2",
                .symbol_name = "Counter2",
                .desc = "HW test counter 2. Factor: 1.0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__test_oa__counter2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter3",
                .symbol_name = "Counter3",
                .desc = "HW test counter 3. Factor: 0.5",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__test_oa__counter3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter4",
                .symbol_name = "Counter4",
                .desc = "HW test counter 4. Factor: 0.3333",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__test_oa__counter4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter5",
                .symbol_name = "Counter5",
                .desc = "HW test counter 5. Factor: 0.3333",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__test_oa__counter5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter6",
                .symbol_name = "Counter6",
                .desc = "HW test counter 6. Factor: 0.16666",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__test_oa__counter6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter7",
                .symbol_name = "Counter7",
                .desc = "HW test counter 7. Factor: 0.6666",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__test_oa__counter7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter8",
                .symbol_name = "Counter8",
                .desc = "HW test counter 8. Should be equal to 1 in IOStream or in OAG query mode",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__test_oa__counter8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter9 - OAR enable",
                .symbol_name = "Counter9",
                .desc = "HW test counter 9. Should be equal to 1 in query.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__test_oa__counter9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__test_oa__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__test_oa__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 13);
}

static bool acmgt2_amfs1_AMFS_4X4_SHADING_REQUEST_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs1_AMFS_CACHE_HIT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs1_AMFS_CACHE_MISS_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs1_AMFS_STALL_ALL_INPUT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs1_AMFS_STALL_ANY_INPUT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_amfs1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "AMFS1";
    metric_set->symbol_name = "AMFS1";
    metric_set->hw_config_guid = "7bb51d65-bc5c-4e23-904c-e7ad932d162e";
    metric_set->counters = calloc(8, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_amfs1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS 4X4 SHADING REQUEST SLICE0",
                .symbol_name = "AMFS_4X4_SHADING_REQUEST_SLICE0",
                .desc = "Number of Shading Request (evaluate) messages processed by AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__amfs1__amfs_4_x4_shading_request_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt2_amfs1_AMFS_4X4_SHADING_REQUEST_SLICE0_availability,
            },

            {
                .name = "AMFS CACHE HIT SLICE0",
                .symbol_name = "AMFS_CACHE_HIT_SLICE0",
                .desc = "Number of hits in the AMFS cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__amfs1__amfs_cache_hit_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt2_amfs1_AMFS_CACHE_HIT_SLICE0_availability,
            },

            {
                .name = "AMFS CACHE MISS SLICE0",
                .symbol_name = "AMFS_CACHE_MISS_SLICE0",
                .desc = "Number of cache misses in AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__amfs1__amfs_cache_miss_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt2_amfs1_AMFS_CACHE_MISS_SLICE0_availability,
            },

            {
                .name = "AMFS STALL ALL INPUT SLICE0",
                .symbol_name = "AMFS_STALL_ALL_INPUT_SLICE0",
                .desc = "Percentage of time in which AMFS stalls at both of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__amfs1__amfs_stall_all_input_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt2_amfs1_AMFS_STALL_ALL_INPUT_SLICE0_availability,
            },

            {
                .name = "AMFS STALL ANY INPUT SLICE0",
                .symbol_name = "AMFS_STALL_ANY_INPUT_SLICE0",
                .desc = "Percentage of time in which AMFS stalls at any of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__amfs1__amfs_stall_any_input_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt2_amfs1_AMFS_STALL_ANY_INPUT_SLICE0_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__amfs1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__amfs1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__amfs1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__amfs1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 8);
}

static bool acmgt2_amfs2_AMFS_4X4_SHADING_REQUEST_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs2_AMFS_CACHE_HIT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs2_AMFS_CACHE_MISS_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs2_AMFS_STALL_ALL_INPUT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs2_AMFS_STALL_ANY_INPUT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_amfs2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "AMFS2";
    metric_set->symbol_name = "AMFS2";
    metric_set->hw_config_guid = "b4899455-a030-400a-a66b-ea270f7722fd";
    metric_set->counters = calloc(8, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_amfs2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS 4X4 SHADING REQUEST SLICE1",
                .symbol_name = "AMFS_4X4_SHADING_REQUEST_SLICE1",
                .desc = "Number of Shading Request (evaluate) messages processed by AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__amfs2__amfs_4_x4_shading_request_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt2_amfs2_AMFS_4X4_SHADING_REQUEST_SLICE1_availability,
            },

            {
                .name = "AMFS CACHE HIT SLICE1",
                .symbol_name = "AMFS_CACHE_HIT_SLICE1",
                .desc = "Number of hits in the AMFS cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__amfs2__amfs_cache_hit_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt2_amfs2_AMFS_CACHE_HIT_SLICE1_availability,
            },

            {
                .name = "AMFS CACHE MISS SLICE1",
                .symbol_name = "AMFS_CACHE_MISS_SLICE1",
                .desc = "Number of cache misses in AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__amfs2__amfs_cache_miss_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt2_amfs2_AMFS_CACHE_MISS_SLICE1_availability,
            },

            {
                .name = "AMFS STALL ALL INPUT SLICE1",
                .symbol_name = "AMFS_STALL_ALL_INPUT_SLICE1",
                .desc = "Percentage of time in which AMFS stalls at both of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__amfs2__amfs_stall_all_input_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt2_amfs2_AMFS_STALL_ALL_INPUT_SLICE1_availability,
            },

            {
                .name = "AMFS STALL ANY INPUT SLICE1",
                .symbol_name = "AMFS_STALL_ANY_INPUT_SLICE1",
                .desc = "Percentage of time in which AMFS stalls at any of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__amfs2__amfs_stall_any_input_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt2_amfs2_AMFS_STALL_ANY_INPUT_SLICE1_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__amfs2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__amfs2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__amfs2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__amfs2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 8);
}

static bool acmgt2_amfs3_AMFS_4X4_SHADING_REQUEST_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs3_AMFS_CACHE_HIT_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs3_AMFS_CACHE_MISS_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs3_AMFS_STALL_ALL_INPUT_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs3_AMFS_STALL_ANY_INPUT_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_amfs3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "AMFS3";
    metric_set->symbol_name = "AMFS3";
    metric_set->hw_config_guid = "cb47ffdf-f1a9-45f2-8ee6-21e0fb8111dd";
    metric_set->counters = calloc(8, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_amfs3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS 4X4 SHADING REQUEST SLICE2",
                .symbol_name = "AMFS_4X4_SHADING_REQUEST_SLICE2",
                .desc = "Number of Shading Request (evaluate) messages processed by AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__amfs3__amfs_4_x4_shading_request_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt2_amfs3_AMFS_4X4_SHADING_REQUEST_SLICE2_availability,
            },

            {
                .name = "AMFS CACHE HIT SLICE2",
                .symbol_name = "AMFS_CACHE_HIT_SLICE2",
                .desc = "Number of hits in the AMFS cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__amfs3__amfs_cache_hit_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt2_amfs3_AMFS_CACHE_HIT_SLICE2_availability,
            },

            {
                .name = "AMFS CACHE MISS SLICE2",
                .symbol_name = "AMFS_CACHE_MISS_SLICE2",
                .desc = "Number of cache misses in AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__amfs3__amfs_cache_miss_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt2_amfs3_AMFS_CACHE_MISS_SLICE2_availability,
            },

            {
                .name = "AMFS STALL ALL INPUT SLICE2",
                .symbol_name = "AMFS_STALL_ALL_INPUT_SLICE2",
                .desc = "Percentage of time in which AMFS stalls at both of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__amfs3__amfs_stall_all_input_slice2__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt2_amfs3_AMFS_STALL_ALL_INPUT_SLICE2_availability,
            },

            {
                .name = "AMFS STALL ANY INPUT SLICE2",
                .symbol_name = "AMFS_STALL_ANY_INPUT_SLICE2",
                .desc = "Percentage of time in which AMFS stalls at any of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__amfs3__amfs_stall_any_input_slice2__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt2_amfs3_AMFS_STALL_ANY_INPUT_SLICE2_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__amfs3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__amfs3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__amfs3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__amfs3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 8);
}

static bool acmgt2_amfs4_AMFS_4X4_SHADING_REQUEST_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs4_AMFS_CACHE_HIT_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs4_AMFS_CACHE_MISS_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs4_AMFS_STALL_ALL_INPUT_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs4_AMFS_STALL_ANY_INPUT_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_amfs4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "AMFS4";
    metric_set->symbol_name = "AMFS4";
    metric_set->hw_config_guid = "2e296498-77db-42ad-8f34-9cda1ff4dcd8";
    metric_set->counters = calloc(8, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_amfs4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS 4X4 SHADING REQUEST SLICE3",
                .symbol_name = "AMFS_4X4_SHADING_REQUEST_SLICE3",
                .desc = "Number of Shading Request (evaluate) messages processed by AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__amfs4__amfs_4_x4_shading_request_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt2_amfs4_AMFS_4X4_SHADING_REQUEST_SLICE3_availability,
            },

            {
                .name = "AMFS CACHE HIT SLICE3",
                .symbol_name = "AMFS_CACHE_HIT_SLICE3",
                .desc = "Number of hits in the AMFS cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__amfs4__amfs_cache_hit_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt2_amfs4_AMFS_CACHE_HIT_SLICE3_availability,
            },

            {
                .name = "AMFS CACHE MISS SLICE3",
                .symbol_name = "AMFS_CACHE_MISS_SLICE3",
                .desc = "Number of cache misses in AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__amfs4__amfs_cache_miss_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt2_amfs4_AMFS_CACHE_MISS_SLICE3_availability,
            },

            {
                .name = "AMFS STALL ALL INPUT SLICE3",
                .symbol_name = "AMFS_STALL_ALL_INPUT_SLICE3",
                .desc = "Percentage of time in which AMFS stalls at both of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__amfs4__amfs_stall_all_input_slice3__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt2_amfs4_AMFS_STALL_ALL_INPUT_SLICE3_availability,
            },

            {
                .name = "AMFS STALL ANY INPUT SLICE3",
                .symbol_name = "AMFS_STALL_ANY_INPUT_SLICE3",
                .desc = "Percentage of time in which AMFS stalls at any of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__amfs4__amfs_stall_any_input_slice3__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt2_amfs4_AMFS_STALL_ANY_INPUT_SLICE3_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__amfs4__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__amfs4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__amfs4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__amfs4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 8);
}

static bool acmgt2_amfs5_AMFS_L3_ACCESS_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs5_AMFS_L3_ACCESS_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs5_AMFS_L3_ACCESS_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs5_AMFS_L3_ACCESS_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs5_AMFS_L3_ATOMIC_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs5_AMFS_L3_ATOMIC_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs5_AMFS_L3_ATOMIC_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs5_AMFS_L3_ATOMIC_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs5_AMFS_L3_WRITE_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs5_AMFS_L3_WRITE_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs5_AMFS_L3_WRITE_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_amfs5_AMFS_L3_WRITE_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_amfs5_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "AMFS5";
    metric_set->symbol_name = "AMFS5";
    metric_set->hw_config_guid = "ef47f98a-fb5f-426d-922e-8ae13cedb198";
    metric_set->counters = calloc(15, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_amfs5_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS L3 ACCESS SLICE0",
                .symbol_name = "AMFS_L3_ACCESS_SLICE0",
                .desc = "Number of AMFS accesses to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__amfs5__amfs_l3_access_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt2_amfs5_AMFS_L3_ACCESS_SLICE0_availability,
            },

            {
                .name = "AMFS L3 ACCESS SLICE1",
                .symbol_name = "AMFS_L3_ACCESS_SLICE1",
                .desc = "Number of AMFS accesses to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__amfs5__amfs_l3_access_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt2_amfs5_AMFS_L3_ACCESS_SLICE1_availability,
            },

            {
                .name = "AMFS L3 ACCESS SLICE2",
                .symbol_name = "AMFS_L3_ACCESS_SLICE2",
                .desc = "Number of AMFS accesses to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__amfs5__amfs_l3_access_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt2_amfs5_AMFS_L3_ACCESS_SLICE2_availability,
            },

            {
                .name = "AMFS L3 ACCESS SLICE3",
                .symbol_name = "AMFS_L3_ACCESS_SLICE3",
                .desc = "Number of AMFS accesses to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__amfs5__amfs_l3_access_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt2_amfs5_AMFS_L3_ACCESS_SLICE3_availability,
            },

            {
                .name = "AMFS L3 ATOMIC SLICE0",
                .symbol_name = "AMFS_L3_ATOMIC_SLICE0",
                .desc = "Number of AMFS atomics to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__amfs5__amfs_l3_atomic_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt2_amfs5_AMFS_L3_ATOMIC_SLICE0_availability,
            },

            {
                .name = "AMFS L3 ATOMIC SLICE1",
                .symbol_name = "AMFS_L3_ATOMIC_SLICE1",
                .desc = "Number of AMFS atomics to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__amfs5__amfs_l3_atomic_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt2_amfs5_AMFS_L3_ATOMIC_SLICE1_availability,
            },

            {
                .name = "AMFS L3 ATOMIC SLICE2",
                .symbol_name = "AMFS_L3_ATOMIC_SLICE2",
                .desc = "Number of AMFS atomics to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__amfs5__amfs_l3_atomic_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt2_amfs5_AMFS_L3_ATOMIC_SLICE2_availability,
            },

            {
                .name = "AMFS L3 ATOMIC SLICE3",
                .symbol_name = "AMFS_L3_ATOMIC_SLICE3",
                .desc = "Number of AMFS atomics to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__amfs5__amfs_l3_atomic_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt2_amfs5_AMFS_L3_ATOMIC_SLICE3_availability,
            },

            {
                .name = "AMFS L3 WRITE SLICE0",
                .symbol_name = "AMFS_L3_WRITE_SLICE0",
                .desc = "Number of AMFS writes to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__amfs5__amfs_l3_write_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt2_amfs5_AMFS_L3_WRITE_SLICE0_availability,
            },

            {
                .name = "AMFS L3 WRITE SLICE1",
                .symbol_name = "AMFS_L3_WRITE_SLICE1",
                .desc = "Number of AMFS writes to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__amfs5__amfs_l3_write_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt2_amfs5_AMFS_L3_WRITE_SLICE1_availability,
            },

            {
                .name = "AMFS L3 WRITE SLICE2",
                .symbol_name = "AMFS_L3_WRITE_SLICE2",
                .desc = "Number of AMFS writes to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__amfs5__amfs_l3_write_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt2_amfs5_AMFS_L3_WRITE_SLICE2_availability,
            },

            {
                .name = "AMFS L3 WRITE SLICE3",
                .symbol_name = "AMFS_L3_WRITE_SLICE3",
                .desc = "Number of AMFS writes to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__amfs5__amfs_l3_write_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt2_amfs5_AMFS_L3_WRITE_SLICE3_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__amfs5__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__amfs5__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__amfs5__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__amfs5__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 15);
}

static bool acmgt2_color_pipe1_RENDER_CACHE_HIT_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe1_RENDER_CACHE_HIT_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe1_RENDER_CACHE_HIT_L3NODE2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe1_RENDER_CACHE_INPUT_AVAILABLE_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe1_RENDER_CACHE_INPUT_AVAILABLE_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe1_RENDER_CACHE_INPUT_AVAILABLE_L3NODE2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe1_RENDER_CACHE_OUTPUT_READY_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe1_RENDER_CACHE_OUTPUT_READY_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe1_RENDER_CACHE_OUTPUT_READY_L3NODE2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe1_RENDER_CACHE_READ_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe1_RENDER_CACHE_READ_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe1_RENDER_CACHE_READ_L3NODE2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe1_RENDER_CACHE_WRITE_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe1_RENDER_CACHE_WRITE_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe1_RENDER_CACHE_WRITE_L3NODE2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_color_pipe1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ColorPipe1";
    metric_set->symbol_name = "ColorPipe1";
    metric_set->hw_config_guid = "ec2c2ae9-a41e-4ff4-99f1-118959c94bfb";
    metric_set->counters = calloc(18, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_color_pipe1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__color_pipe1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__color_pipe1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__color_pipe1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__color_pipe1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RENDER CACHE HIT L3NODE0",
                .symbol_name = "RENDER_CACHE_HIT_L3NODE0",
                .desc = "Number of Render Cache hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__color_pipe1__render_cache_hit_l3_node0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe1_RENDER_CACHE_HIT_L3NODE0_availability,
            },

            {
                .name = "RENDER CACHE HIT L3NODE1",
                .symbol_name = "RENDER_CACHE_HIT_L3NODE1",
                .desc = "Number of Render Cache hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__color_pipe1__render_cache_hit_l3_node1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe1_RENDER_CACHE_HIT_L3NODE1_availability,
            },

            {
                .name = "RENDER CACHE HIT L3NODE2",
                .symbol_name = "RENDER_CACHE_HIT_L3NODE2",
                .desc = "Number of Render Cache hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__color_pipe1__render_cache_hit_l3_node2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe1_RENDER_CACHE_HIT_L3NODE2_availability,
            },

            {
                .name = "RENDER_CACHE_INPUT_AVAILABLE _L3NODE0",
                .symbol_name = "RENDER_CACHE_INPUT_AVAILABLE_L3NODE0",
                .desc = "Percentage of time when render cache input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe1__render_cache_input_available_l3_node0__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe1_RENDER_CACHE_INPUT_AVAILABLE_L3NODE0_availability,
            },

            {
                .name = "RENDER_CACHE_INPUT_AVAILABLE _L3NODE1",
                .symbol_name = "RENDER_CACHE_INPUT_AVAILABLE_L3NODE1",
                .desc = "Percentage of time when render cache input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe1__render_cache_input_available_l3_node1__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe1_RENDER_CACHE_INPUT_AVAILABLE_L3NODE1_availability,
            },

            {
                .name = "RENDER_CACHE_INPUT_AVAILABLE _L3NODE2",
                .symbol_name = "RENDER_CACHE_INPUT_AVAILABLE_L3NODE2",
                .desc = "Percentage of time when render cache input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe1__render_cache_input_available_l3_node2__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe1_RENDER_CACHE_INPUT_AVAILABLE_L3NODE2_availability,
            },

            {
                .name = "RENDER_CACHE_OUTPUT_READY _L3NODE0",
                .symbol_name = "RENDER_CACHE_OUTPUT_READY_L3NODE0",
                .desc = "Percentage of time when render cache output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe1__render_cache_output_ready_l3_node0__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe1_RENDER_CACHE_OUTPUT_READY_L3NODE0_availability,
            },

            {
                .name = "RENDER_CACHE_OUTPUT_READY _L3NODE1",
                .symbol_name = "RENDER_CACHE_OUTPUT_READY_L3NODE1",
                .desc = "Percentage of time when render cache output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe1__render_cache_output_ready_l3_node1__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe1_RENDER_CACHE_OUTPUT_READY_L3NODE1_availability,
            },

            {
                .name = "RENDER_CACHE_OUTPUT_READY _L3NODE2",
                .symbol_name = "RENDER_CACHE_OUTPUT_READY_L3NODE2",
                .desc = "Percentage of time when render cache output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe1__render_cache_output_ready_l3_node2__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe1_RENDER_CACHE_OUTPUT_READY_L3NODE2_availability,
            },

            {
                .name = "RENDER CACHE READ L3NODE0",
                .symbol_name = "RENDER_CACHE_READ_L3NODE0",
                .desc = "Number of Render Cache reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__color_pipe1__render_cache_read_l3_node0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe1_RENDER_CACHE_READ_L3NODE0_availability,
            },

            {
                .name = "RENDER CACHE READ L3NODE1",
                .symbol_name = "RENDER_CACHE_READ_L3NODE1",
                .desc = "Number of Render Cache reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__color_pipe1__render_cache_read_l3_node1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe1_RENDER_CACHE_READ_L3NODE1_availability,
            },

            {
                .name = "RENDER CACHE READ L3NODE2",
                .symbol_name = "RENDER_CACHE_READ_L3NODE2",
                .desc = "Number of Render Cache reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__color_pipe1__render_cache_read_l3_node2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe1_RENDER_CACHE_READ_L3NODE2_availability,
            },

            {
                .name = "RENDER CACHE WRITE L3NODE0",
                .symbol_name = "RENDER_CACHE_WRITE_L3NODE0",
                .desc = "Number of Render Cache writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__color_pipe1__render_cache_write_l3_node0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe1_RENDER_CACHE_WRITE_L3NODE0_availability,
            },

            {
                .name = "RENDER CACHE WRITE L3NODE1",
                .symbol_name = "RENDER_CACHE_WRITE_L3NODE1",
                .desc = "Number of Render Cache writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__color_pipe1__render_cache_write_l3_node1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe1_RENDER_CACHE_WRITE_L3NODE1_availability,
            },

            {
                .name = "RENDER CACHE WRITE L3NODE2",
                .symbol_name = "RENDER_CACHE_WRITE_L3NODE2",
                .desc = "Number of Render Cache writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__color_pipe1__render_cache_write_l3_node2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe1_RENDER_CACHE_WRITE_L3NODE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 18);
}

static bool acmgt2_color_pipe2_RENDER_CACHE_HIT_L3NODE3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe2_RENDER_CACHE_INPUT_AVAILABLE_L3NODE3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe2_RENDER_CACHE_OUTPUT_READY_L3NODE3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe2_RENDER_CACHE_READ_L3NODE3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe2_RENDER_CACHE_WRITE_L3NODE3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_color_pipe2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ColorPipe2";
    metric_set->symbol_name = "ColorPipe2";
    metric_set->hw_config_guid = "d7862a6d-902e-4d1f-9f39-e0f94aa4346e";
    metric_set->counters = calloc(8, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_color_pipe2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__color_pipe2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__color_pipe2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__color_pipe2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__color_pipe2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RENDER CACHE HIT L3NODE3",
                .symbol_name = "RENDER_CACHE_HIT_L3NODE3",
                .desc = "Number of Render Cache hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__color_pipe2__render_cache_hit_l3_node3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe2_RENDER_CACHE_HIT_L3NODE3_availability,
            },

            {
                .name = "RENDER_CACHE_INPUT_AVAILABLE _L3NODE3",
                .symbol_name = "RENDER_CACHE_INPUT_AVAILABLE_L3NODE3",
                .desc = "Percentage of time when render cache input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe2__render_cache_input_available_l3_node3__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe2_RENDER_CACHE_INPUT_AVAILABLE_L3NODE3_availability,
            },

            {
                .name = "RENDER_CACHE_OUTPUT_READY _L3NODE3",
                .symbol_name = "RENDER_CACHE_OUTPUT_READY_L3NODE3",
                .desc = "Percentage of time when render cache output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe2__render_cache_output_ready_l3_node3__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe2_RENDER_CACHE_OUTPUT_READY_L3NODE3_availability,
            },

            {
                .name = "RENDER CACHE READ L3NODE3",
                .symbol_name = "RENDER_CACHE_READ_L3NODE3",
                .desc = "Number of Render Cache reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__color_pipe2__render_cache_read_l3_node3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe2_RENDER_CACHE_READ_L3NODE3_availability,
            },

            {
                .name = "RENDER CACHE WRITE L3NODE3",
                .symbol_name = "RENDER_CACHE_WRITE_L3NODE3",
                .desc = "Number of Render Cache writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__color_pipe2__render_cache_write_l3_node3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe2_RENDER_CACHE_WRITE_L3NODE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 8);
}

static bool acmgt2_color_pipe3_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe3_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe3_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe3_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe3_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe3_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe3_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe3_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe3_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe3_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe3_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe3_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe3_PS_OUTPUT_AVAILABLE_CPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe3_PS_OUTPUT_AVAILABLE_CPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_color_pipe3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ColorPipe3";
    metric_set->symbol_name = "ColorPipe3";
    metric_set->hw_config_guid = "f00094e7-2baa-4bb9-807b-d77bb1c72eba";
    metric_set->counters = calloc(17, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_color_pipe3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__color_pipe3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__color_pipe3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE0",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE0",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe3__color_pipe_cache_latency1_stall_cpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe3_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE0_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE1",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE1",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe3__color_pipe_cache_latency1_stall_cpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe3_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE1_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE2",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE2",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe3__color_pipe_cache_latency1_stall_cpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe3_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE2_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE3",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE3",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe3__color_pipe_cache_latency1_stall_cpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe3_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE3_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE4",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE4",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe3__color_pipe_cache_latency1_stall_cpipe4__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe3_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE4_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE5",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE5",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe3__color_pipe_cache_latency1_stall_cpipe5__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe3_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE5_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE6",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE6",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe3__color_pipe_cache_latency1_stall_cpipe6__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe3_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE6_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE7",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE7",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe3__color_pipe_cache_latency1_stall_cpipe7__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe3_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE7_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY2 STALL L3NODE0",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE0",
                .desc = "Percentage of time in which Color Pipeline stalled due to Render Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe3__color_pipe_cache_latency2_stall_l3_node0__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe3_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE0_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY2 STALL L3NODE1",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE1",
                .desc = "Percentage of time in which Color Pipeline stalled due to Render Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe3__color_pipe_cache_latency2_stall_l3_node1__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe3_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE1_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY2 STALL L3NODE2",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE2",
                .desc = "Percentage of time in which Color Pipeline stalled due to Render Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe3__color_pipe_cache_latency2_stall_l3_node2__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe3_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE2_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY2 STALL L3NODE3",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE3",
                .desc = "Percentage of time in which Color Pipeline stalled due to Render Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe3__color_pipe_cache_latency2_stall_l3_node3__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe3_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__color_pipe3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__color_pipe3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE0",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE0",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe3__ps_output_available_cpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe3_PS_OUTPUT_AVAILABLE_CPIPE0_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE1",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE1",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe3__ps_output_available_cpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe3_PS_OUTPUT_AVAILABLE_CPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 17);
}

static bool acmgt2_color_pipe4_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe4_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_color_pipe4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ColorPipe4";
    metric_set->symbol_name = "ColorPipe4";
    metric_set->hw_config_guid = "341991a5-3457-4201-a48e-d368a979f01d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_color_pipe4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__color_pipe4__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__color_pipe4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__color_pipe4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__color_pipe4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE0",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE0",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe4__pixel_post_process_input_available_cpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe4_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE0_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE1",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE1",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe4__pixel_post_process_input_available_cpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe4_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_color_pipe5_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe5_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_color_pipe5_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ColorPipe5";
    metric_set->symbol_name = "ColorPipe5";
    metric_set->hw_config_guid = "34664510-6687-48d0-adc5-b7a60069de8d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_color_pipe5_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__color_pipe5__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__color_pipe5__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__color_pipe5__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__color_pipe5__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE2",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE2",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe5__pixel_post_process_input_available_cpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe5_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE2_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE3",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE3",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe5__pixel_post_process_input_available_cpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe5_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_color_pipe6_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe6_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_color_pipe6_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ColorPipe6";
    metric_set->symbol_name = "ColorPipe6";
    metric_set->hw_config_guid = "1c9a3218-c1ee-402f-b483-6263a0757515";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_color_pipe6_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__color_pipe6__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__color_pipe6__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__color_pipe6__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__color_pipe6__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE4",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE4",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe6__pixel_post_process_input_available_cpipe4__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe6_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE4_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE5",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE5",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe6__pixel_post_process_input_available_cpipe5__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe6_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_color_pipe7_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe7_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_color_pipe7_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ColorPipe7";
    metric_set->symbol_name = "ColorPipe7";
    metric_set->hw_config_guid = "d85dc73b-5121-44c8-87b2-df05b1eecdf3";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_color_pipe7_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__color_pipe7__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__color_pipe7__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__color_pipe7__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__color_pipe7__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE6",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE6",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe7__pixel_post_process_input_available_cpipe6__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe7_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE6_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE7",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE7",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe7__pixel_post_process_input_available_cpipe7__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe7_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_color_pipe8_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe8_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe8_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe8_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe8_PS_OUTPUT_AVAILABLE_CPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe8_PS_OUTPUT_AVAILABLE_CPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe8_PS_OUTPUT_AVAILABLE_CPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe8_PS_OUTPUT_AVAILABLE_CPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe8_PS_OUTPUT_AVAILABLE_CPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe8_PS_OUTPUT_AVAILABLE_CPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_color_pipe8_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ColorPipe8";
    metric_set->symbol_name = "ColorPipe8";
    metric_set->hw_config_guid = "4695a23b-b2b0-48f5-8bf1-743255be3e2e";
    metric_set->counters = calloc(13, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_color_pipe8_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__color_pipe8__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__color_pipe8__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__color_pipe8__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__color_pipe8__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE0",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE0",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe8__pixel_post_process_output_ready_cpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe8_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE0_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE1",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE1",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe8__pixel_post_process_output_ready_cpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe8_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE1_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE2",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE2",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe8__pixel_post_process_output_ready_cpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe8_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE2_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE3",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE3",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe8__pixel_post_process_output_ready_cpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe8_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE3_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE2",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE2",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe8__ps_output_available_cpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe8_PS_OUTPUT_AVAILABLE_CPIPE2_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE3",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE3",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe8__ps_output_available_cpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe8_PS_OUTPUT_AVAILABLE_CPIPE3_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE4",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE4",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe8__ps_output_available_cpipe4__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe8_PS_OUTPUT_AVAILABLE_CPIPE4_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE5",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE5",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe8__ps_output_available_cpipe5__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe8_PS_OUTPUT_AVAILABLE_CPIPE5_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE6",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE6",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe8__ps_output_available_cpipe6__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe8_PS_OUTPUT_AVAILABLE_CPIPE6_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE7",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE7",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe8__ps_output_available_cpipe7__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe8_PS_OUTPUT_AVAILABLE_CPIPE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 13);
}

static bool acmgt2_color_pipe9_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe9_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe9_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe9_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe9_RENDER_CACHE_ALLOC_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe9_RENDER_CACHE_ALLOC_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe9_RENDER_CACHE_ALLOC_L3NODE2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_color_pipe9_RENDER_CACHE_ALLOC_L3NODE3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_color_pipe9_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ColorPipe9";
    metric_set->symbol_name = "ColorPipe9";
    metric_set->hw_config_guid = "73b4fa16-fd16-4c45-bb66-a733308a8b57";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_color_pipe9_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__color_pipe9__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__color_pipe9__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__color_pipe9__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__color_pipe9__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE4",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE4",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe9__pixel_post_process_output_ready_cpipe4__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe9_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE4_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE5",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE5",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe9__pixel_post_process_output_ready_cpipe5__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe9_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE5_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE6",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE6",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe9__pixel_post_process_output_ready_cpipe6__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe9_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE6_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE7",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE7",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__color_pipe9__pixel_post_process_output_ready_cpipe7__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe9_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE7_availability,
            },

            {
                .name = "RENDER CACHE ALLOC L3NODE0",
                .symbol_name = "RENDER_CACHE_ALLOC_L3NODE0",
                .desc = "Number of Render Cache allocations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__color_pipe9__render_cache_alloc_l3_node0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe9_RENDER_CACHE_ALLOC_L3NODE0_availability,
            },

            {
                .name = "RENDER CACHE ALLOC L3NODE1",
                .symbol_name = "RENDER_CACHE_ALLOC_L3NODE1",
                .desc = "Number of Render Cache allocations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__color_pipe9__render_cache_alloc_l3_node1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe9_RENDER_CACHE_ALLOC_L3NODE1_availability,
            },

            {
                .name = "RENDER CACHE ALLOC L3NODE2",
                .symbol_name = "RENDER_CACHE_ALLOC_L3NODE2",
                .desc = "Number of Render Cache allocations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__color_pipe9__render_cache_alloc_l3_node2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe9_RENDER_CACHE_ALLOC_L3NODE2_availability,
            },

            {
                .name = "RENDER CACHE ALLOC L3NODE3",
                .symbol_name = "RENDER_CACHE_ALLOC_L3NODE3",
                .desc = "Number of Render Cache allocations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__color_pipe9__render_cache_alloc_l3_node3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe9_RENDER_CACHE_ALLOC_L3NODE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_color_pipe10_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_color_pipe10_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ColorPipe10";
    metric_set->symbol_name = "ColorPipe10";
    metric_set->hw_config_guid = "41a973fd-a067-4760-be3a-ccac78e0eadb";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_color_pipe10_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__color_pipe10__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__color_pipe10__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__color_pipe10__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__color_pipe10__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE0",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE0",
                .desc = "Number of promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__color_pipe10__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe10_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_color_pipe11_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_color_pipe11_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ColorPipe11";
    metric_set->symbol_name = "ColorPipe11";
    metric_set->hw_config_guid = "a42ec42b-53d5-40b2-8950-9aabe714601a";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_color_pipe11_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__color_pipe11__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__color_pipe11__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__color_pipe11__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__color_pipe11__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE1",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE1",
                .desc = "Number of promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__color_pipe11__pixel_2x2_lit_post_rasterizer_early_depth_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe11_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_color_pipe12_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_color_pipe12_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ColorPipe12";
    metric_set->symbol_name = "ColorPipe12";
    metric_set->hw_config_guid = "4682628b-6cc3-4b22-b818-ca5347cd7bf3";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_color_pipe12_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__color_pipe12__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__color_pipe12__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__color_pipe12__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__color_pipe12__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE2",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE2",
                .desc = "Number of promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__color_pipe12__pixel_2x2_lit_post_rasterizer_early_depth_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe12_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_color_pipe13_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_color_pipe13_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ColorPipe13";
    metric_set->symbol_name = "ColorPipe13";
    metric_set->hw_config_guid = "76fcf17c-a3ad-474c-a2fb-58a1517c28f4";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_color_pipe13_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__color_pipe13__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__color_pipe13__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__color_pipe13__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__color_pipe13__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE3",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE3",
                .desc = "Number of promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__color_pipe13__pixel_2x2_lit_post_rasterizer_early_depth_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe13_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_color_pipe14_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_color_pipe14_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ColorPipe14";
    metric_set->symbol_name = "ColorPipe14";
    metric_set->hw_config_guid = "6708cf0b-dd77-4fb7-aad1-909ffea99aea";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_color_pipe14_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__color_pipe14__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__color_pipe14__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__color_pipe14__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__color_pipe14__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE0",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE0",
                .desc = "Number of non-promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__color_pipe14__pixel_2x2_lit_post_rasterizer_late_depth_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe14_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_color_pipe15_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_color_pipe15_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ColorPipe15";
    metric_set->symbol_name = "ColorPipe15";
    metric_set->hw_config_guid = "cb36baf7-85bd-4ce3-a0d7-4d296c5932a7";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_color_pipe15_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__color_pipe15__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__color_pipe15__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__color_pipe15__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__color_pipe15__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE1",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE1",
                .desc = "Number of non-promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__color_pipe15__pixel_2x2_lit_post_rasterizer_late_depth_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe15_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_color_pipe16_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_color_pipe16_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ColorPipe16";
    metric_set->symbol_name = "ColorPipe16";
    metric_set->hw_config_guid = "f1e33629-b9d8-4033-a791-2afb70f5bf8d";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_color_pipe16_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__color_pipe16__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__color_pipe16__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__color_pipe16__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__color_pipe16__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE2",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE2",
                .desc = "Number of non-promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__color_pipe16__pixel_2x2_lit_post_rasterizer_late_depth_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe16_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_color_pipe17_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_color_pipe17_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ColorPipe17";
    metric_set->symbol_name = "ColorPipe17";
    metric_set->hw_config_guid = "fb67c9e2-4acb-4775-b715-ffc4b743d9e8";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_color_pipe17_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__color_pipe17__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__color_pipe17__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__color_pipe17__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__color_pipe17__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE3",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE3",
                .desc = "Number of non-promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__color_pipe17__pixel_2x2_lit_post_rasterizer_late_depth_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt2_color_pipe17_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_dataport1_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport1_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport1_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport1_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport1_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport1_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport1_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport1_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport1";
    metric_set->symbol_name = "Dataport1";
    metric_set->hw_config_guid = "e0466349-b62f-474c-88f9-3a9b62a3274a";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE0",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport1__xve_dataport_atomic_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport1_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE1",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport1__xve_dataport_atomic_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport1_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE0",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport1__xve_dataport_fence_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport1_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE1",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport1__xve_dataport_fence_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport1_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE0",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport1__xve_dataport_read_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport1_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE1",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport1__xve_dataport_read_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport1_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE0",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport1__xve_dataport_write_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport1_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE1",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport1__xve_dataport_write_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport1_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_dataport2_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport2_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport2_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport2_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport2_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport2_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport2_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport2_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport2";
    metric_set->symbol_name = "Dataport2";
    metric_set->hw_config_guid = "28e63e4a-ae68-4913-9f28-ae9269aadf2b";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE2",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport2__xve_dataport_atomic_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport2_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE3",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport2__xve_dataport_atomic_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport2_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE3_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE2",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport2__xve_dataport_fence_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport2_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE3",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport2__xve_dataport_fence_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport2_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE3_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE2",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport2__xve_dataport_read_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport2_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE3",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport2__xve_dataport_read_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport2_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE3_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE2",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport2__xve_dataport_write_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport2_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE3",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport2__xve_dataport_write_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport2_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_dataport3_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport3_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport3_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport3_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport3_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport3_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport3_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport3_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport3";
    metric_set->symbol_name = "Dataport3";
    metric_set->hw_config_guid = "f9dd355a-29ce-4f78-9ea4-e2f0f799876d";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE4",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport3__xve_dataport_atomic_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport3_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE5",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport3__xve_dataport_atomic_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport3_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE4",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport3__xve_dataport_fence_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport3_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE5",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport3__xve_dataport_fence_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport3_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE4",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport3__xve_dataport_read_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport3_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE5",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport3__xve_dataport_read_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport3_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE4",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport3__xve_dataport_write_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport3_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE5",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport3__xve_dataport_write_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport3_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_dataport4_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport4_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport4_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport4_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport4_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport4_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport4_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport4_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport4";
    metric_set->symbol_name = "Dataport4";
    metric_set->hw_config_guid = "d79af0bc-b6e9-4057-8eb8-f61fad6efe55";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport4__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE6",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport4__xve_dataport_atomic_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport4_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE7",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport4__xve_dataport_atomic_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport4_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE7_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE6",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport4__xve_dataport_fence_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport4_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE7",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport4__xve_dataport_fence_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport4_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE7_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE6",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport4__xve_dataport_read_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport4_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE7",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport4__xve_dataport_read_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport4_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE7_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE6",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport4__xve_dataport_write_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport4_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE7",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport4__xve_dataport_write_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport4_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_dataport5_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport5_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport5_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport5_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport5_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport5_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport5_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport5_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport5_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport5";
    metric_set->symbol_name = "Dataport5";
    metric_set->hw_config_guid = "8890d6d6-bac2-4830-9abb-e38e1da08e0b";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport5_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport5__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport5__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport5__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport5__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE8",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE8",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport5__xve_dataport_atomic_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport5_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE9",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE9",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport5__xve_dataport_atomic_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport5_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE9_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE8",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE8",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport5__xve_dataport_fence_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport5_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE9",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE9",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport5__xve_dataport_fence_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport5_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE9_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE8",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE8",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport5__xve_dataport_read_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport5_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE9",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE9",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport5__xve_dataport_read_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport5_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE9_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE8",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE8",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport5__xve_dataport_write_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport5_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE9",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE9",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport5__xve_dataport_write_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport5_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_dataport6_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport6_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport6_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport6_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport6_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport6_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport6_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport6_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport6_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport6";
    metric_set->symbol_name = "Dataport6";
    metric_set->hw_config_guid = "c181f521-7c29-4ac6-a44e-d398043d1c41";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport6_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport6__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport6__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport6__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport6__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE10",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE10",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport6__xve_dataport_atomic_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport6_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE11",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE11",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport6__xve_dataport_atomic_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport6_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE11_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE10",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE10",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport6__xve_dataport_fence_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport6_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE11",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE11",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport6__xve_dataport_fence_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport6_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE11_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE10",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE10",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport6__xve_dataport_read_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport6_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE11",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE11",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport6__xve_dataport_read_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport6_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE11_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE10",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE10",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport6__xve_dataport_write_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport6_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE11",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE11",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport6__xve_dataport_write_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport6_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_dataport7_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport7_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport7_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport7_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport7_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport7_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport7_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport7_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport7_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport7";
    metric_set->symbol_name = "Dataport7";
    metric_set->hw_config_guid = "b83732c6-e9b4-4449-90df-3d3518bcc6a2";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport7_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport7__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport7__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport7__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport7__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE12",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE12",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport7__xve_dataport_atomic_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport7_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE13",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE13",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport7__xve_dataport_atomic_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport7_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE13_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE12",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE12",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport7__xve_dataport_fence_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport7_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE13",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE13",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport7__xve_dataport_fence_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport7_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE13_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE12",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE12",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport7__xve_dataport_read_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport7_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE13",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE13",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport7__xve_dataport_read_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport7_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE13_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE12",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE12",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport7__xve_dataport_write_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport7_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE13",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE13",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport7__xve_dataport_write_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport7_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_dataport8_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport8_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport8_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport8_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport8_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport8_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport8_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport8_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport8_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport8";
    metric_set->symbol_name = "Dataport8";
    metric_set->hw_config_guid = "a82addb0-e73f-43a4-9b0a-89df6b2ad267";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport8_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport8__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport8__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport8__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport8__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE14",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE14",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport8__xve_dataport_atomic_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport8_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE15",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE15",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport8__xve_dataport_atomic_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport8_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE15_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE14",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE14",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport8__xve_dataport_fence_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport8_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE15",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE15",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport8__xve_dataport_fence_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport8_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE15_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE14",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE14",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport8__xve_dataport_read_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport8_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE15",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE15",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport8__xve_dataport_read_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport8_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE15_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE14",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE14",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport8__xve_dataport_write_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport8_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE15",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE15",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport8__xve_dataport_write_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport8_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_dataport9_DATAPORT_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport9_DATAPORT_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport9_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport9";
    metric_set->symbol_name = "Dataport9";
    metric_set->hw_config_guid = "91d91417-69c7-458d-bb48-d1c83871d61a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport9_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport9__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport9__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE0",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport9__dataport_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport9_DATAPORT_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE1",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport9__dataport_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport9_DATAPORT_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport9__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport9__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_dataport10_DATAPORT_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport10_DATAPORT_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport10_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport10";
    metric_set->symbol_name = "Dataport10";
    metric_set->hw_config_guid = "7bb38598-cd33-4e49-957c-cbe7ab599120";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport10_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport10__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport10__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE2",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport10__dataport_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport10_DATAPORT_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE3",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport10__dataport_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport10_DATAPORT_INPUT_AVAILABLE_XECORE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport10__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport10__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_dataport11_DATAPORT_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport11_DATAPORT_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport11_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport11";
    metric_set->symbol_name = "Dataport11";
    metric_set->hw_config_guid = "8108a31f-3d5d-46f3-8cd0-6c9b2c3e0038";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport11_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport11__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport11__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE4",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport11__dataport_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport11_DATAPORT_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE5",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport11__dataport_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport11_DATAPORT_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport11__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport11__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_dataport12_DATAPORT_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport12_DATAPORT_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport12_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport12";
    metric_set->symbol_name = "Dataport12";
    metric_set->hw_config_guid = "c7acfa27-136c-4527-8e81-517c6a2aa724";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport12_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport12__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport12__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE6",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport12__dataport_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport12_DATAPORT_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE7",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport12__dataport_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport12_DATAPORT_INPUT_AVAILABLE_XECORE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport12__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport12__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_dataport13_DATAPORT_INPUT_AVAILABLE_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport13_DATAPORT_INPUT_AVAILABLE_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport13_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport13";
    metric_set->symbol_name = "Dataport13";
    metric_set->hw_config_guid = "10c1bda5-f032-4e6e-8597-741046aa81c4";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport13_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport13__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport13__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE8",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE8",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport13__dataport_input_available_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport13_DATAPORT_INPUT_AVAILABLE_XECORE8_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE9",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE9",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport13__dataport_input_available_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport13_DATAPORT_INPUT_AVAILABLE_XECORE9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport13__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport13__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_dataport14_DATAPORT_INPUT_AVAILABLE_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport14_DATAPORT_INPUT_AVAILABLE_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport14_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport14";
    metric_set->symbol_name = "Dataport14";
    metric_set->hw_config_guid = "9e026386-432e-42ce-8bb8-c833127dbbe7";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport14_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport14__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport14__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE10",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE10",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport14__dataport_input_available_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport14_DATAPORT_INPUT_AVAILABLE_XECORE10_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE11",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE11",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport14__dataport_input_available_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport14_DATAPORT_INPUT_AVAILABLE_XECORE11_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport14__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport14__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_dataport15_DATAPORT_INPUT_AVAILABLE_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport15_DATAPORT_INPUT_AVAILABLE_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport15_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport15";
    metric_set->symbol_name = "Dataport15";
    metric_set->hw_config_guid = "51c4a645-0ffe-4dc2-bc5c-30075c771f71";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport15_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport15__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport15__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE12",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE12",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport15__dataport_input_available_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport15_DATAPORT_INPUT_AVAILABLE_XECORE12_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE13",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE13",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport15__dataport_input_available_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport15_DATAPORT_INPUT_AVAILABLE_XECORE13_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport15__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport15__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_dataport16_DATAPORT_INPUT_AVAILABLE_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport16_DATAPORT_INPUT_AVAILABLE_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport16_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport16";
    metric_set->symbol_name = "Dataport16";
    metric_set->hw_config_guid = "4699e9f0-8029-44dc-9f86-23ee43b2592e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport16_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport16__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport16__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE14",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE14",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport16__dataport_input_available_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport16_DATAPORT_INPUT_AVAILABLE_XECORE14_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE15",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE15",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport16__dataport_input_available_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport16_DATAPORT_INPUT_AVAILABLE_XECORE15_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport16__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport16__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_dataport17_DATAPORT_OUTPUT_READY_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport17_DATAPORT_OUTPUT_READY_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport17_DATAPORT_OUTPUT_READY_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport17_DATAPORT_OUTPUT_READY_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport17_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport17";
    metric_set->symbol_name = "Dataport17";
    metric_set->hw_config_guid = "eae3432b-6340-4d86-bae1-3d6da5d6f9c7";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport17_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport17__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport17__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE0",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE0",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport17__dataport_output_ready_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport17_DATAPORT_OUTPUT_READY_XECORE0_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE1",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE1",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport17__dataport_output_ready_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport17_DATAPORT_OUTPUT_READY_XECORE1_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE2",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE2",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport17__dataport_output_ready_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport17_DATAPORT_OUTPUT_READY_XECORE2_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE3",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE3",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport17__dataport_output_ready_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport17_DATAPORT_OUTPUT_READY_XECORE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport17__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport17__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_dataport18_DATAPORT_OUTPUT_READY_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport18_DATAPORT_OUTPUT_READY_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport18_DATAPORT_OUTPUT_READY_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport18_DATAPORT_OUTPUT_READY_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport18_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport18";
    metric_set->symbol_name = "Dataport18";
    metric_set->hw_config_guid = "fc5c5c04-55ea-4094-92fc-1d40f7f132b0";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport18_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport18__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport18__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE4",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE4",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport18__dataport_output_ready_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport18_DATAPORT_OUTPUT_READY_XECORE4_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE5",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE5",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport18__dataport_output_ready_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport18_DATAPORT_OUTPUT_READY_XECORE5_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE6",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE6",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport18__dataport_output_ready_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport18_DATAPORT_OUTPUT_READY_XECORE6_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE7",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE7",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport18__dataport_output_ready_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport18_DATAPORT_OUTPUT_READY_XECORE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport18__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport18__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_dataport19_DATAPORT_OUTPUT_READY_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport19_DATAPORT_OUTPUT_READY_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport19_DATAPORT_OUTPUT_READY_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport19_DATAPORT_OUTPUT_READY_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport19_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport19";
    metric_set->symbol_name = "Dataport19";
    metric_set->hw_config_guid = "66cc68bd-b460-42ec-b815-2531dc145a33";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport19_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport19__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport19__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE10",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE10",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport19__dataport_output_ready_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport19_DATAPORT_OUTPUT_READY_XECORE10_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE11",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE11",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport19__dataport_output_ready_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport19_DATAPORT_OUTPUT_READY_XECORE11_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE8",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE8",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport19__dataport_output_ready_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport19_DATAPORT_OUTPUT_READY_XECORE8_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE9",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE9",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport19__dataport_output_ready_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport19_DATAPORT_OUTPUT_READY_XECORE9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport19__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport19__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_dataport20_DATAPORT_OUTPUT_READY_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport20_DATAPORT_OUTPUT_READY_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport20_DATAPORT_OUTPUT_READY_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport20_DATAPORT_OUTPUT_READY_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport20_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport20";
    metric_set->symbol_name = "Dataport20";
    metric_set->hw_config_guid = "c3f17ea7-bdba-4ce6-971e-9920ae779870";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport20_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport20__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport20__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE12",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE12",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport20__dataport_output_ready_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport20_DATAPORT_OUTPUT_READY_XECORE12_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE13",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE13",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport20__dataport_output_ready_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport20_DATAPORT_OUTPUT_READY_XECORE13_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE14",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE14",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport20__dataport_output_ready_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport20_DATAPORT_OUTPUT_READY_XECORE14_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE15",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE15",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__dataport20__dataport_output_ready_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt2_dataport20_DATAPORT_OUTPUT_READY_XECORE15_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport20__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport20__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_dataport21_DATAPORT_BYTE_READ_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport21_DATAPORT_BYTE_READ_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport21_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport21";
    metric_set->symbol_name = "Dataport21";
    metric_set->hw_config_guid = "fe3d6064-fb8d-4c1c-8375-65c1b2d23287";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport21_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport21__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport21__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE0",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE0",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport21__dataport_byte_read_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport21_DATAPORT_BYTE_READ_XECORE0_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE1",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE1",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport21__dataport_byte_read_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport21_DATAPORT_BYTE_READ_XECORE1_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport21__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport21__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_dataport22_DATAPORT_BYTE_READ_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport22_DATAPORT_BYTE_READ_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport22_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport22";
    metric_set->symbol_name = "Dataport22";
    metric_set->hw_config_guid = "ca29a63a-9e93-4631-befe-cb0985365d3b";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport22_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport22__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport22__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE2",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE2",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport22__dataport_byte_read_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport22_DATAPORT_BYTE_READ_XECORE2_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE3",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE3",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport22__dataport_byte_read_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport22_DATAPORT_BYTE_READ_XECORE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport22__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport22__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_dataport23_DATAPORT_BYTE_READ_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport23_DATAPORT_BYTE_READ_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport23_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport23";
    metric_set->symbol_name = "Dataport23";
    metric_set->hw_config_guid = "f194891f-8915-4c9d-978e-4ef91c44d5d1";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport23_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport23__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport23__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE4",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE4",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport23__dataport_byte_read_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport23_DATAPORT_BYTE_READ_XECORE4_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE5",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE5",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport23__dataport_byte_read_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport23_DATAPORT_BYTE_READ_XECORE5_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport23__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport23__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_dataport24_DATAPORT_BYTE_READ_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport24_DATAPORT_BYTE_READ_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport24_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport24";
    metric_set->symbol_name = "Dataport24";
    metric_set->hw_config_guid = "62bac6fb-20ca-4fbf-b821-cd80ecdcb57b";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport24_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport24__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport24__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE6",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE6",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport24__dataport_byte_read_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport24_DATAPORT_BYTE_READ_XECORE6_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE7",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE7",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport24__dataport_byte_read_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport24_DATAPORT_BYTE_READ_XECORE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport24__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport24__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_dataport25_DATAPORT_BYTE_READ_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport25_DATAPORT_BYTE_READ_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport25_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport25";
    metric_set->symbol_name = "Dataport25";
    metric_set->hw_config_guid = "7a2a2ce5-0e00-429b-9d96-ce5c030378e2";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport25_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport25__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport25__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE8",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE8",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport25__dataport_byte_read_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport25_DATAPORT_BYTE_READ_XECORE8_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE9",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE9",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport25__dataport_byte_read_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport25_DATAPORT_BYTE_READ_XECORE9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport25__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport25__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_dataport26_DATAPORT_BYTE_READ_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport26_DATAPORT_BYTE_READ_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport26_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport26";
    metric_set->symbol_name = "Dataport26";
    metric_set->hw_config_guid = "d6169119-c923-4d10-b16e-6439fa5e150d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport26_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport26__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport26__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE10",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE10",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport26__dataport_byte_read_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport26_DATAPORT_BYTE_READ_XECORE10_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE11",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE11",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport26__dataport_byte_read_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport26_DATAPORT_BYTE_READ_XECORE11_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport26__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport26__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_dataport27_DATAPORT_BYTE_READ_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport27_DATAPORT_BYTE_READ_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport27_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport27";
    metric_set->symbol_name = "Dataport27";
    metric_set->hw_config_guid = "703a8fb1-96b2-4c89-ad1b-f721efa0fade";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport27_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport27__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport27__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE12",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE12",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport27__dataport_byte_read_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport27_DATAPORT_BYTE_READ_XECORE12_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE13",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE13",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport27__dataport_byte_read_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport27_DATAPORT_BYTE_READ_XECORE13_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport27__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport27__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_dataport28_DATAPORT_BYTE_READ_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport28_DATAPORT_BYTE_READ_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport28_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport28";
    metric_set->symbol_name = "Dataport28";
    metric_set->hw_config_guid = "7d3ea8fa-f0e2-4436-bfed-2cfd5d42e3fa";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport28_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport28__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport28__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE14",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE14",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport28__dataport_byte_read_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport28_DATAPORT_BYTE_READ_XECORE14_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE15",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE15",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport28__dataport_byte_read_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport28_DATAPORT_BYTE_READ_XECORE15_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport28__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport28__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport29_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport29";
    metric_set->symbol_name = "Dataport29";
    metric_set->hw_config_guid = "f42d9eaa-4a36-4b10-a96e-6794cbbdc43a";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport29_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport29__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport29__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE0",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE0",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport29__dataport_byte_write_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE0_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE1",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE1",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport29__dataport_byte_write_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE1_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE10",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE10",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport29__dataport_byte_write_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE10_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE11",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE11",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport29__dataport_byte_write_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE11_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE12",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE12",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport29__dataport_byte_write_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE12_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE13",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE13",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport29__dataport_byte_write_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE13_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE14",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE14",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport29__dataport_byte_write_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE14_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE15",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE15",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport29__dataport_byte_write_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE15_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE2",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE2",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport29__dataport_byte_write_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE2_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE3",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE3",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport29__dataport_byte_write_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE3_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE4",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE4",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport29__dataport_byte_write_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE4_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE5",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE5",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport29__dataport_byte_write_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE5_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE6",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE6",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport29__dataport_byte_write_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE6_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE7",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE7",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport29__dataport_byte_write_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE7_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE8",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE8",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport29__dataport_byte_write_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE8_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE9",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE9",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__dataport29__dataport_byte_write_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport29_DATAPORT_BYTE_WRITE_XECORE9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport29__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport29__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_dataport30_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport30_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport30_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport30_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport30_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport30_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport30_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport30_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport30_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport30";
    metric_set->symbol_name = "Dataport30";
    metric_set->hw_config_guid = "6805565e-e6aa-41a8-b486-4f1ca91c11c9";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport30_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport30__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport30__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport30__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport30__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE0",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE0",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport30__xve_dataport_register_request_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport30_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE1",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE1",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport30__xve_dataport_register_request_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport30_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE2",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE2",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport30__xve_dataport_register_request_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport30_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE3",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE3",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport30__xve_dataport_register_request_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport30_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE3_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE4",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE4",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport30__xve_dataport_register_request_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport30_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE5",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE5",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport30__xve_dataport_register_request_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport30_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE6",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE6",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport30__xve_dataport_register_request_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport30_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE7",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE7",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport30__xve_dataport_register_request_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport30_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_dataport31_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport31_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport31_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport31_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport31_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport31_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport31_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport31_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport31_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport31";
    metric_set->symbol_name = "Dataport31";
    metric_set->hw_config_guid = "c4d2235c-1d4b-44b7-b746-a11016520ffd";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport31_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport31__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport31__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport31__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport31__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE10",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE10",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport31__xve_dataport_register_request_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport31_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE11",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE11",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport31__xve_dataport_register_request_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport31_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE11_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE12",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE12",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport31__xve_dataport_register_request_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport31_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE13",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE13",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport31__xve_dataport_register_request_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport31_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE13_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE14",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE14",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport31__xve_dataport_register_request_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport31_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE15",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE15",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport31__xve_dataport_register_request_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport31_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE15_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE8",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE8",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport31__xve_dataport_register_request_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport31_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE9",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE9",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport31__xve_dataport_register_request_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport31_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_dataport32_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport32_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport32_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport32";
    metric_set->symbol_name = "Dataport32";
    metric_set->hw_config_guid = "1f7d4994-5397-410c-98ed-5e1bc3d44ceb";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport32_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport32__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport32__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport32__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport32__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE0",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE0",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport32__xve_dataport_register_response_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport32_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE1",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE1",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt2__dataport32__xve_dataport_register_response_count_xecore1__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport32_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_dataport33_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport33_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport33_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport33";
    metric_set->symbol_name = "Dataport33";
    metric_set->hw_config_guid = "42d54580-601f-4dcb-9c91-c5bd37782f65";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport33_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport33__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport33__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport33__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport33__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE2",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE2",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt2__dataport33__xve_dataport_register_response_count_xecore2__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport33_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE3",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE3",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt2__dataport33__xve_dataport_register_response_count_xecore3__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport33_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_dataport34_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport34_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport34_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport34";
    metric_set->symbol_name = "Dataport34";
    metric_set->hw_config_guid = "0ce98a1c-8516-4412-b1ce-b0eeaca989df";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport34_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport34__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport34__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport34__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport34__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE4",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE4",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt2__dataport34__xve_dataport_register_response_count_xecore4__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport34_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE5",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE5",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt2__dataport34__xve_dataport_register_response_count_xecore5__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport34_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_dataport35_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport35_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport35_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport35";
    metric_set->symbol_name = "Dataport35";
    metric_set->hw_config_guid = "857f49c7-71b4-4fa0-86f0-55f817676cff";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport35_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport35__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport35__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport35__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport35__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE6",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE6",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt2__dataport35__xve_dataport_register_response_count_xecore6__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport35_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE7",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE7",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt2__dataport35__xve_dataport_register_response_count_xecore7__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport35_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_dataport36_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport36_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport36_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport36";
    metric_set->symbol_name = "Dataport36";
    metric_set->hw_config_guid = "dde58e8e-e867-4144-9782-4464798e7c63";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport36_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport36__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport36__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport36__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport36__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE8",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE8",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt2__dataport36__xve_dataport_register_response_count_xecore8__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport36_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE9",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE9",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt2__dataport36__xve_dataport_register_response_count_xecore9__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport36_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_dataport37_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport37_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport37_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport37";
    metric_set->symbol_name = "Dataport37";
    metric_set->hw_config_guid = "fd0e95c3-0a28-4911-80d7-dad9716739c3";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport37_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport37__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport37__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport37__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport37__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE10",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE10",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt2__dataport37__xve_dataport_register_response_count_xecore10__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport37_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE11",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE11",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt2__dataport37__xve_dataport_register_response_count_xecore11__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport37_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_dataport38_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport38_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport38_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport38";
    metric_set->symbol_name = "Dataport38";
    metric_set->hw_config_guid = "ac3fa7ef-1963-4643-917f-9f9b6161ee62";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport38_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport38__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport38__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport38__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport38__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE12",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE12",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt2__dataport38__xve_dataport_register_response_count_xecore12__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport38_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE13",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE13",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt2__dataport38__xve_dataport_register_response_count_xecore13__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport38_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_dataport39_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport39_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport39_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport39";
    metric_set->symbol_name = "Dataport39";
    metric_set->hw_config_guid = "ca4e1039-7322-4606-b3cc-7f33dcb93301";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport39_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport39__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport39__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport39__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport39__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE14",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE14",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt2__dataport39__xve_dataport_register_response_count_xecore14__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport39_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE15",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE15",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt2__dataport39__xve_dataport_register_response_count_xecore15__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport39_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport40_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport40";
    metric_set->symbol_name = "Dataport40";
    metric_set->hw_config_guid = "3712af1f-03c7-48e3-b2a5-6d9ac64b3122";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport40_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport40__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport40__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE0",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE0",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport40__dataport_texture_cache_access_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE0_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE1",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE1",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport40__dataport_texture_cache_access_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE1_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE10",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE10",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport40__dataport_texture_cache_access_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE10_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE11",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE11",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport40__dataport_texture_cache_access_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE11_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE12",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE12",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport40__dataport_texture_cache_access_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE12_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE13",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE13",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport40__dataport_texture_cache_access_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE13_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE14",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE14",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport40__dataport_texture_cache_access_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE14_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE15",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE15",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport40__dataport_texture_cache_access_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE15_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE2",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE2",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport40__dataport_texture_cache_access_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE2_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE3",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE3",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport40__dataport_texture_cache_access_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE3_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE4",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE4",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport40__dataport_texture_cache_access_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE4_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE5",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE5",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport40__dataport_texture_cache_access_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE5_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE6",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE6",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport40__dataport_texture_cache_access_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE6_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE7",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE7",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport40__dataport_texture_cache_access_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE7_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE8",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE8",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport40__dataport_texture_cache_access_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE8_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE9",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE9",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport40__dataport_texture_cache_access_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport40_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport40__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport40__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_dataport41_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Dataport41";
    metric_set->symbol_name = "Dataport41";
    metric_set->hw_config_guid = "3df5cfc4-865d-4314-a53a-379d76aac638";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_dataport41_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__dataport41__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__dataport41__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE0",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE0",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport41__dataport_texture_cache_hit_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE0_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE1",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE1",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport41__dataport_texture_cache_hit_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE1_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE10",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE10",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport41__dataport_texture_cache_hit_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE10_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE11",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE11",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport41__dataport_texture_cache_hit_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE11_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE12",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE12",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport41__dataport_texture_cache_hit_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE12_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE13",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE13",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport41__dataport_texture_cache_hit_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE13_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE14",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE14",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport41__dataport_texture_cache_hit_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE14_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE15",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE15",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport41__dataport_texture_cache_hit_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE15_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE2",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE2",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport41__dataport_texture_cache_hit_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE2_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE3",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE3",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport41__dataport_texture_cache_hit_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE3_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE4",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE4",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport41__dataport_texture_cache_hit_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE4_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE5",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE5",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport41__dataport_texture_cache_hit_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE5_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE6",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE6",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport41__dataport_texture_cache_hit_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE6_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE7",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE7",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport41__dataport_texture_cache_hit_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE7_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE8",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE8",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport41__dataport_texture_cache_hit_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE8_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE9",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE9",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__dataport41__dataport_texture_cache_hit_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt2_dataport41_DATAPORT_TEXTURE_CACHE_HIT_XECORE9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__dataport41__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__dataport41__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_depth_pipe1_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe1_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe1";
    metric_set->symbol_name = "DepthPipe1";
    metric_set->hw_config_guid = "33168209-e5ab-4330-856c-0d4a1b95dce3";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE0",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE0",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__depth_pipe1__early_depth_stencil_test_fail_np_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe1_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE0_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE0",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE0",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__depth_pipe1__early_depth_stencil_test_fail_p_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe1_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE0_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_depth_pipe2_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe2_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe2";
    metric_set->symbol_name = "DepthPipe2";
    metric_set->hw_config_guid = "ada82722-0eaf-4903-96f0-3c8ed2227c7f";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE1",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE1",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__depth_pipe2__early_depth_stencil_test_fail_np_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe2_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE1_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE1",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE1",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__depth_pipe2__early_depth_stencil_test_fail_p_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe2_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE1_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_depth_pipe3_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe3_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe3";
    metric_set->symbol_name = "DepthPipe3";
    metric_set->hw_config_guid = "359bdac8-5929-4e54-a5e5-526b28a487ab";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE2",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE2",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__depth_pipe3__early_depth_stencil_test_fail_np_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe3_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE2_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE2",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE2",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__depth_pipe3__early_depth_stencil_test_fail_p_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe3_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE2_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_depth_pipe4_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe4_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe4";
    metric_set->symbol_name = "DepthPipe4";
    metric_set->hw_config_guid = "1b8e5aa0-be13-4c87-9ad0-f0d4f7d7f2a5";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe4__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE3",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE3",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__depth_pipe4__early_depth_stencil_test_fail_np_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe4_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE3_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE3",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE3",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__depth_pipe4__early_depth_stencil_test_fail_p_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe4_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_depth_pipe5_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe5_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe5_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe5";
    metric_set->symbol_name = "DepthPipe5";
    metric_set->hw_config_guid = "b192f113-23af-494e-82e7-b9a81810c75d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe5_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe5__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe5__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE4",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE4",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__depth_pipe5__early_depth_stencil_test_fail_np_zpipe4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe5_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE4_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE4",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE4",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__depth_pipe5__early_depth_stencil_test_fail_p_zpipe4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe5_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE4_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe5__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe5__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_depth_pipe6_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe6_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe6_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe6";
    metric_set->symbol_name = "DepthPipe6";
    metric_set->hw_config_guid = "f617db06-51cc-447d-989c-0811dc7c7b38";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe6_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe6__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe6__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE5",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE5",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__depth_pipe6__early_depth_stencil_test_fail_np_zpipe5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe6_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE5_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE5",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE5",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__depth_pipe6__early_depth_stencil_test_fail_p_zpipe5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe6_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE5_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe6__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe6__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_depth_pipe7_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe7_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe7_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe7";
    metric_set->symbol_name = "DepthPipe7";
    metric_set->hw_config_guid = "bd2422a2-0a56-476d-a52d-b4aa15a5d842";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe7_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe7__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe7__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE6",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE6",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__depth_pipe7__early_depth_stencil_test_fail_np_zpipe6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe7_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE6_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE6",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE6",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__depth_pipe7__early_depth_stencil_test_fail_p_zpipe6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe7_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE6_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe7__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe7__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_depth_pipe8_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe8_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe8_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe8";
    metric_set->symbol_name = "DepthPipe8";
    metric_set->hw_config_guid = "7856d434-02e6-4a06-b585-e45e7616f1d5";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe8_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe8__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe8__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE7",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE7",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__depth_pipe8__early_depth_stencil_test_fail_np_zpipe7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe8_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE7_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE7",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE7",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__depth_pipe8__early_depth_stencil_test_fail_p_zpipe7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe8_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe8__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe8__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_depth_pipe9_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe9_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe9";
    metric_set->symbol_name = "DepthPipe9";
    metric_set->hw_config_guid = "60b56817-8e14-488e-917d-29bffd9fefbb";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe9_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe9__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe9__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe9__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe9__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE0",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE0",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe9__hiz_depth_test_ambig_np_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe9_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe10_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe10_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe10";
    metric_set->symbol_name = "DepthPipe10";
    metric_set->hw_config_guid = "8dff928f-699b-4f34-a297-cf46c9519662";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe10_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe10__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe10__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe10__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe10__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE1",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE1",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe10__hiz_depth_test_ambig_np_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe10_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe11_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe11_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe11";
    metric_set->symbol_name = "DepthPipe11";
    metric_set->hw_config_guid = "fa8e2ae9-3507-4eed-9a02-b18c396a21b1";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe11_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe11__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe11__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe11__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe11__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE2",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE2",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe11__hiz_depth_test_ambig_np_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe11_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe12_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe12_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe12";
    metric_set->symbol_name = "DepthPipe12";
    metric_set->hw_config_guid = "4736a783-c2f3-4f67-931f-eca0fdddf57f";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe12_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe12__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe12__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe12__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe12__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE3",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE3",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe12__hiz_depth_test_ambig_np_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe12_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe13_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe13_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe13";
    metric_set->symbol_name = "DepthPipe13";
    metric_set->hw_config_guid = "a305b93f-dba5-4318-89ba-051192cbe1be";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe13_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe13__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe13__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe13__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe13__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE4",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE4",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe13__hiz_depth_test_ambig_np_zpipe4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe13_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe14_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe14_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe14";
    metric_set->symbol_name = "DepthPipe14";
    metric_set->hw_config_guid = "dcfc3d88-b9bd-424b-b3ca-854f2e2d4863";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe14_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe14__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe14__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe14__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe14__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE5",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE5",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe14__hiz_depth_test_ambig_np_zpipe5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe14_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe15_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe15_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe15";
    metric_set->symbol_name = "DepthPipe15";
    metric_set->hw_config_guid = "d706dc1e-e6c8-4fe0-b6ed-ea99cdc41673";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe15_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe15__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe15__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe15__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe15__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE6",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE6",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe15__hiz_depth_test_ambig_np_zpipe6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe15_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe16_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe16_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe16";
    metric_set->symbol_name = "DepthPipe16";
    metric_set->hw_config_guid = "de4874a3-6881-43a8-9243-6af156af44e5";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe16_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe16__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe16__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe16__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe16__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE7",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE7",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe16__hiz_depth_test_ambig_np_zpipe7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe16_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe17_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe17_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe17";
    metric_set->symbol_name = "DepthPipe17";
    metric_set->hw_config_guid = "c3d18c22-f267-4f8a-8b4e-b26abd1d1660";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe17_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe17__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe17__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe17__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe17__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE0",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE0",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe17__hiz_depth_test_ambig_p_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe17_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe18_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe18_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe18";
    metric_set->symbol_name = "DepthPipe18";
    metric_set->hw_config_guid = "0fa14813-96d3-424b-8935-b70b4e24ea85";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe18_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe18__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe18__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe18__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe18__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE1",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE1",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe18__hiz_depth_test_ambig_p_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe18_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe19_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe19_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe19";
    metric_set->symbol_name = "DepthPipe19";
    metric_set->hw_config_guid = "4e741dfb-12e7-4a31-8bed-1d587c0cafc5";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe19_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe19__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe19__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe19__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe19__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE2",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE2",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe19__hiz_depth_test_ambig_p_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe19_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe20_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe20_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe20";
    metric_set->symbol_name = "DepthPipe20";
    metric_set->hw_config_guid = "66117e26-8834-4f72-b8f3-162bafb24232";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe20_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe20__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe20__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe20__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe20__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE3",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE3",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe20__hiz_depth_test_ambig_p_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe20_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe21_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe21_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe21";
    metric_set->symbol_name = "DepthPipe21";
    metric_set->hw_config_guid = "4b9e649c-1392-4856-abe6-9e67bb06ac5e";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe21_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe21__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe21__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe21__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe21__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE4",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE4",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe21__hiz_depth_test_ambig_p_zpipe4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe21_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe22_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe22_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe22";
    metric_set->symbol_name = "DepthPipe22";
    metric_set->hw_config_guid = "ced7882f-f88d-431c-9dad-8f3016a64777";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe22_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe22__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe22__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe22__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe22__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE5",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE5",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe22__hiz_depth_test_ambig_p_zpipe5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe22_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe23_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe23_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe23";
    metric_set->symbol_name = "DepthPipe23";
    metric_set->hw_config_guid = "17ba725c-bcfb-444c-8725-fe9bc1a99c5b";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe23_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe23__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe23__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe23__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe23__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE6",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE6",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe23__hiz_depth_test_ambig_p_zpipe6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe23_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe24_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe24_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe24";
    metric_set->symbol_name = "DepthPipe24";
    metric_set->hw_config_guid = "efdfcd4f-8bc6-4251-b956-dfd351f8632e";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe24_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe24__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe24__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe24__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe24__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE7",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE7",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe24__hiz_depth_test_ambig_p_zpipe7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe24_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe25_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe25_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe25";
    metric_set->symbol_name = "DepthPipe25";
    metric_set->hw_config_guid = "bad6c158-57f6-471f-a9e3-cad9e779d211";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe25_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe25__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe25__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe25__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe25__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE0",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE0",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe25__hiz_depth_test_fail_np_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe25_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe26_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe26_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe26";
    metric_set->symbol_name = "DepthPipe26";
    metric_set->hw_config_guid = "4a7b11ce-2d9e-4905-99c4-ededa640b342";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe26_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe26__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe26__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe26__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe26__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE1",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE1",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe26__hiz_depth_test_fail_np_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe26_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe27_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe27_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe27";
    metric_set->symbol_name = "DepthPipe27";
    metric_set->hw_config_guid = "8c0a8f9b-3e97-4b6d-adb1-fbecb395ec00";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe27_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe27__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe27__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe27__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe27__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE2",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE2",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe27__hiz_depth_test_fail_np_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe27_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe28_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe28_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe28";
    metric_set->symbol_name = "DepthPipe28";
    metric_set->hw_config_guid = "b7471c18-89e6-4e6d-826c-5f0ca0791154";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe28_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe28__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe28__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe28__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe28__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE3",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE3",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe28__hiz_depth_test_fail_np_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe28_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe29_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe29_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe29";
    metric_set->symbol_name = "DepthPipe29";
    metric_set->hw_config_guid = "36d7c5ca-28e3-41c8-8e2b-f67beba4b23f";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe29_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe29__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe29__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe29__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe29__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE4",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE4",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe29__hiz_depth_test_fail_np_zpipe4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe29_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe30_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe30_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe30";
    metric_set->symbol_name = "DepthPipe30";
    metric_set->hw_config_guid = "1bfbb150-1614-49a3-973b-7972bf7c9a91";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe30_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe30__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe30__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe30__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe30__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE5",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE5",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe30__hiz_depth_test_fail_np_zpipe5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe30_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe31_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe31_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe31";
    metric_set->symbol_name = "DepthPipe31";
    metric_set->hw_config_guid = "80d75f6a-6c5b-46c9-a3a7-1911e2cba86e";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe31_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe31__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe31__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe31__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe31__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE6",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE6",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe31__hiz_depth_test_fail_np_zpipe6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe31_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe32_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe32_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe32";
    metric_set->symbol_name = "DepthPipe32";
    metric_set->hw_config_guid = "3368bfa2-0680-4282-aaf1-9ec1a1713b82";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe32_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe32__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe32__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe32__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe32__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE7",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE7",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe32__hiz_depth_test_fail_np_zpipe7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe32_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe33_HIZ_DEPTH_TEST_FAIL_P_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe33_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe33";
    metric_set->symbol_name = "DepthPipe33";
    metric_set->hw_config_guid = "101b4d80-895b-4957-9f24-18456078793a";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe33_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe33__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe33__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe33__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe33__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE0",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE0",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe33__hiz_depth_test_fail_p_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe33_HIZ_DEPTH_TEST_FAIL_P_ZPIPE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe34_HIZ_DEPTH_TEST_FAIL_P_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe34_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe34";
    metric_set->symbol_name = "DepthPipe34";
    metric_set->hw_config_guid = "342e501a-0038-412c-9e8a-a9ed02b7b9ef";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe34_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe34__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe34__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe34__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe34__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE1",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE1",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe34__hiz_depth_test_fail_p_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe34_HIZ_DEPTH_TEST_FAIL_P_ZPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe35_HIZ_DEPTH_TEST_FAIL_P_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe35_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe35";
    metric_set->symbol_name = "DepthPipe35";
    metric_set->hw_config_guid = "5c4a1a1c-3df5-43af-adb0-9cd78dd944f8";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe35_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe35__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe35__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe35__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe35__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE2",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE2",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe35__hiz_depth_test_fail_p_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe35_HIZ_DEPTH_TEST_FAIL_P_ZPIPE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe36_HIZ_DEPTH_TEST_FAIL_P_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe36_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe36";
    metric_set->symbol_name = "DepthPipe36";
    metric_set->hw_config_guid = "f19a51db-ff00-40c0-a13f-1c404e80652e";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe36_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe36__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe36__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe36__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe36__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE3",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE3",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe36__hiz_depth_test_fail_p_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe36_HIZ_DEPTH_TEST_FAIL_P_ZPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe37_HIZ_DEPTH_TEST_FAIL_P_ZPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe37_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe37";
    metric_set->symbol_name = "DepthPipe37";
    metric_set->hw_config_guid = "6f269feb-2743-4953-a8b4-7e4b000901bc";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe37_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe37__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe37__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe37__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe37__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE4",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE4",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe37__hiz_depth_test_fail_p_zpipe4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe37_HIZ_DEPTH_TEST_FAIL_P_ZPIPE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe38_HIZ_DEPTH_TEST_FAIL_P_ZPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe38_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe38";
    metric_set->symbol_name = "DepthPipe38";
    metric_set->hw_config_guid = "7b9d22cb-7c4e-4885-be22-833c310e7fd4";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe38_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe38__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe38__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe38__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe38__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE5",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE5",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe38__hiz_depth_test_fail_p_zpipe5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe38_HIZ_DEPTH_TEST_FAIL_P_ZPIPE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe39_HIZ_DEPTH_TEST_FAIL_P_ZPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe39_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe39";
    metric_set->symbol_name = "DepthPipe39";
    metric_set->hw_config_guid = "482c20b4-68c5-4656-8de2-039b2ca8a0f9";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe39_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe39__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe39__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe39__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe39__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE6",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE6",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe39__hiz_depth_test_fail_p_zpipe6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe39_HIZ_DEPTH_TEST_FAIL_P_ZPIPE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe40_HIZ_DEPTH_TEST_FAIL_P_ZPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe40_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe40";
    metric_set->symbol_name = "DepthPipe40";
    metric_set->hw_config_guid = "743ffcbc-c6d5-4b28-b58c-1d23d1ea8fff";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe40_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe40__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe40__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe40__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe40__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE7",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE7",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe40__hiz_depth_test_fail_p_zpipe7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe40_HIZ_DEPTH_TEST_FAIL_P_ZPIPE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe41_HIZ_DEPTH_TEST_PASS_P_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe41_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe41";
    metric_set->symbol_name = "DepthPipe41";
    metric_set->hw_config_guid = "f809a7a3-2248-480c-b851-1b23f3d6e7f2";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe41_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe41__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe41__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe41__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe41__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE0",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE0",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe41__hiz_depth_test_pass_p_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe41_HIZ_DEPTH_TEST_PASS_P_ZPIPE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe42_HIZ_DEPTH_TEST_PASS_P_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe42_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe42";
    metric_set->symbol_name = "DepthPipe42";
    metric_set->hw_config_guid = "effaccd8-6f1c-4a50-b39b-3a0f75eebf66";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe42_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe42__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe42__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe42__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe42__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE1",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE1",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe42__hiz_depth_test_pass_p_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe42_HIZ_DEPTH_TEST_PASS_P_ZPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe43_HIZ_DEPTH_TEST_PASS_P_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe43_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe43";
    metric_set->symbol_name = "DepthPipe43";
    metric_set->hw_config_guid = "39b392ed-3513-4c3f-9b22-bde5a9ee725c";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe43_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe43__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe43__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe43__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe43__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE2",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE2",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe43__hiz_depth_test_pass_p_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe43_HIZ_DEPTH_TEST_PASS_P_ZPIPE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe44_HIZ_DEPTH_TEST_PASS_P_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe44_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe44";
    metric_set->symbol_name = "DepthPipe44";
    metric_set->hw_config_guid = "adb868c4-97f3-420f-b766-073244232afb";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe44_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe44__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe44__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe44__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe44__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE3",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE3",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe44__hiz_depth_test_pass_p_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe44_HIZ_DEPTH_TEST_PASS_P_ZPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe45_HIZ_DEPTH_TEST_PASS_P_ZPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe45_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe45";
    metric_set->symbol_name = "DepthPipe45";
    metric_set->hw_config_guid = "71825303-a777-4079-85e0-69ee3f3caad3";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe45_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe45__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe45__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe45__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe45__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE4",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE4",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe45__hiz_depth_test_pass_p_zpipe4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe45_HIZ_DEPTH_TEST_PASS_P_ZPIPE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe46_HIZ_DEPTH_TEST_PASS_P_ZPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe46_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe46";
    metric_set->symbol_name = "DepthPipe46";
    metric_set->hw_config_guid = "2e086ff4-e74f-45bd-82d7-599a27a9aaba";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe46_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe46__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe46__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe46__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe46__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE5",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE5",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe46__hiz_depth_test_pass_p_zpipe5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe46_HIZ_DEPTH_TEST_PASS_P_ZPIPE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe47_HIZ_DEPTH_TEST_PASS_P_ZPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe47_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe47";
    metric_set->symbol_name = "DepthPipe47";
    metric_set->hw_config_guid = "b0b33553-4e1c-445d-8e40-c03873ef1d5e";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe47_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe47__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe47__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe47__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe47__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE6",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE6",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe47__hiz_depth_test_pass_p_zpipe6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe47_HIZ_DEPTH_TEST_PASS_P_ZPIPE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe48_HIZ_DEPTH_TEST_PASS_P_ZPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe48_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe48";
    metric_set->symbol_name = "DepthPipe48";
    metric_set->hw_config_guid = "154e627a-ce2c-4d36-a441-dae9e8317fba";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe48_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe48__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe48__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe48__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe48__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE7",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE7",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__depth_pipe48__hiz_depth_test_pass_p_zpipe7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe48_HIZ_DEPTH_TEST_PASS_P_ZPIPE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_depth_pipe49_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe49_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe49_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe49_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe49_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe49_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe49_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe49_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe49_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe49_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe49_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe49_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe49_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe49_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe49_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe49_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe49_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe49";
    metric_set->symbol_name = "DepthPipe49";
    metric_set->hw_config_guid = "8d79b860-44be-4e17-bd33-eb95a7d6ad47";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe49_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe49__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe49__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe49__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe49__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE0",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__depth_pipe49__hiz_subspan_latency_fifofull_zpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe49_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE1",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__depth_pipe49__hiz_subspan_latency_fifofull_zpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe49_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE2",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__depth_pipe49__hiz_subspan_latency_fifofull_zpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe49_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE3",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__depth_pipe49__hiz_subspan_latency_fifofull_zpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe49_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE4",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE4",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__depth_pipe49__hiz_subspan_latency_fifofull_zpipe4__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe49_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE4_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE5",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE5",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__depth_pipe49__hiz_subspan_latency_fifofull_zpipe5__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe49_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE5_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE6",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE6",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__depth_pipe49__hiz_subspan_latency_fifofull_zpipe6__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe49_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE6_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE7",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE7",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__depth_pipe49__hiz_subspan_latency_fifofull_zpipe7__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe49_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE7_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE0",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__depth_pipe49__iz_subspan_latency_fifofull_zpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe49_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE1",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__depth_pipe49__iz_subspan_latency_fifofull_zpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe49_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE2",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__depth_pipe49__iz_subspan_latency_fifofull_zpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe49_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE3",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__depth_pipe49__iz_subspan_latency_fifofull_zpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe49_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE4",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE4",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__depth_pipe49__iz_subspan_latency_fifofull_zpipe4__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe49_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE4_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE5",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE5",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__depth_pipe49__iz_subspan_latency_fifofull_zpipe5__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe49_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE5_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE6",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE6",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__depth_pipe49__iz_subspan_latency_fifofull_zpipe6__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe49_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE6_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE7",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE7",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__depth_pipe49__iz_subspan_latency_fifofull_zpipe7__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe49_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_depth_pipe50_IZ_OUTPUT_READY_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe50_IZ_OUTPUT_READY_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe50_IZ_OUTPUT_READY_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe50_IZ_OUTPUT_READY_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe50_IZ_OUTPUT_READY_ZPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe50_IZ_OUTPUT_READY_ZPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe50_IZ_OUTPUT_READY_ZPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_depth_pipe50_IZ_OUTPUT_READY_ZPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_depth_pipe50_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DepthPipe50";
    metric_set->symbol_name = "DepthPipe50";
    metric_set->hw_config_guid = "980f1b68-a258-493e-aad2-8b40a0923a67";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_depth_pipe50_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__depth_pipe50__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__depth_pipe50__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__depth_pipe50__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__depth_pipe50__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "IZ OUTPUT READY ZPIPE0",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE0",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__depth_pipe50__iz_output_ready_zpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe50_IZ_OUTPUT_READY_ZPIPE0_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE1",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE1",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__depth_pipe50__iz_output_ready_zpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe50_IZ_OUTPUT_READY_ZPIPE1_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE2",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE2",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__depth_pipe50__iz_output_ready_zpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe50_IZ_OUTPUT_READY_ZPIPE2_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE3",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE3",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__depth_pipe50__iz_output_ready_zpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe50_IZ_OUTPUT_READY_ZPIPE3_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE4",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE4",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__depth_pipe50__iz_output_ready_zpipe4__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe50_IZ_OUTPUT_READY_ZPIPE4_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE5",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE5",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__depth_pipe50__iz_output_ready_zpipe5__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe50_IZ_OUTPUT_READY_ZPIPE5_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE6",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE6",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__depth_pipe50__iz_output_ready_zpipe6__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe50_IZ_OUTPUT_READY_ZPIPE6_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE7",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE7",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__depth_pipe50__iz_output_ready_zpipe7__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt2_depth_pipe50_IZ_OUTPUT_READY_ZPIPE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}


static void
acmgt2_add_front_end1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "FrontEnd1";
    metric_set->symbol_name = "FrontEnd1";
    metric_set->hw_config_guid = "502ad763-3720-4e28-93c2-6d9e4383c8b2";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_front_end1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__front_end1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__front_end1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE BUSY",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_BUSY",
                .desc = "Percentage of time in which there is a context loaded and active on the compute queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__front_end1__command_parser_compute_engine_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE BUSY CCS0",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_BUSY_CCS0",
                .desc = "Percentage of time in which there is a context loaded and active on the compute queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__front_end1__command_parser_compute_engine_busy_ccs0__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE BUSY CCS1",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_BUSY_CCS1",
                .desc = "Percentage of time in which there is a context loaded and active on the compute queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__front_end1__command_parser_compute_engine_busy_ccs1__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_DISPATCH_KERNEL_COUNT",
                .desc = "Number of compute walker commands parsed on the compute engine",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__front_end1__command_parser_compute_engine_dispatch_kernel_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS0",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_DISPATCH_KERNEL_COUNT_CCS0",
                .desc = "Number of compute walker commands parsed on the compute engine",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__front_end1__command_parser_compute_engine_dispatch_kernel_count_ccs0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS1",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_DISPATCH_KERNEL_COUNT_CCS1",
                .desc = "Number of compute walker commands parsed on the compute engine",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__front_end1__command_parser_compute_engine_dispatch_kernel_count_ccs1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER COPY ENGINE BUSY",
                .symbol_name = "COMMAND_PARSER_COPY_ENGINE_BUSY",
                .desc = "Percentage of time in which there is a context loaded and active on the copy queue.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__front_end1__command_parser_copy_engine_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER FLUSH COUNT",
                .symbol_name = "COMMAND_PARSER_FLUSH_COUNT",
                .desc = "Number of Stalling flushes at the top of the pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__front_end1__command_parser_flush_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER RENDER ENGINE BUSY",
                .symbol_name = "COMMAND_PARSER_RENDER_ENGINE_BUSY",
                .desc = "Percentage of time in which there is a context loaded and active on the 3D queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__front_end1__command_parser_render_engine_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER RENDER ENGINE DISPATCH KERNEL COUNT",
                .symbol_name = "COMMAND_PARSER_RENDER_ENGINE_DISPATCH_KERNEL_COUNT",
                .desc = "Number of compute walker commands parsed on the 3D engine",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__front_end1__command_parser_render_engine_dispatch_kernel_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER RENDER ENGINE DRAW COUNT",
                .symbol_name = "COMMAND_PARSER_RENDER_ENGINE_DRAW_COUNT",
                .desc = "Number of DRAW and MESH commands parsed on the 3D engine",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__front_end1__command_parser_render_engine_draw_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER VIDEO ENGINE BUSY",
                .symbol_name = "COMMAND_PARSER_VIDEO_ENGINE_BUSY",
                .desc = "Percentage of time in which there is a context loaded and active on the media queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__front_end1__command_parser_video_engine_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER VIDEO ENGINE BUSY VDBOX0",
                .symbol_name = "COMMAND_PARSER_VIDEO_ENGINE_BUSY_VDBOX0",
                .desc = "Percentage of time in which there is a context loaded and active on the media queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__front_end1__command_parser_video_engine_busy_vdbox0__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER VIDEO ENGINE BUSY VDBOX1",
                .symbol_name = "COMMAND_PARSER_VIDEO_ENGINE_BUSY_VDBOX1",
                .desc = "Percentage of time in which there is a context loaded and active on the media queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__front_end1__command_parser_video_engine_busy_vdbox1__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER VIDEO ENHANCEMENT ENGINE BUSY",
                .symbol_name = "COMMAND_PARSER_VIDEO_ENHANCEMENT_ENGINE_BUSY",
                .desc = "Percentage of time in which there is a context loaded and active on the video enhancement queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__front_end1__command_parser_video_enhancement_engine_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER VIDEO ENHANCEMENT ENGINE BUSY VEBOX0",
                .symbol_name = "COMMAND_PARSER_VIDEO_ENHANCEMENT_ENGINE_BUSY_VEBOX0",
                .desc = "Percentage of time in which there is a context loaded and active on the video enhancement queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__front_end1__command_parser_video_enhancement_engine_busy_vebox0__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER VIDEO ENHANCEMENT ENGINE BUSY VEBOX1",
                .symbol_name = "COMMAND_PARSER_VIDEO_ENHANCEMENT_ENGINE_BUSY_VEBOX1",
                .desc = "Percentage of time in which there is a context loaded and active on the video enhancement queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__front_end1__command_parser_video_enhancement_engine_busy_vebox1__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__front_end1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__front_end1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt2_geometry1_CLIPPER_INPUT_VERTEX_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry1_CLIPPER_INPUT_VERTEX_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry1_CLIPPER_INPUT_VERTEX_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry1_CLIPPER_INPUT_VERTEX_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry1_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry1_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry1_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry1_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_geometry1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Geometry1";
    metric_set->symbol_name = "Geometry1";
    metric_set->hw_config_guid = "f655036b-8302-4327-880e-014cffa29448";
    metric_set->counters = calloc(9, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_geometry1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "CLIPPER INPUT VERTEX SLICE0",
                .symbol_name = "CLIPPER_INPUT_VERTEX_SLICE0",
                .desc = "Number of Clipper input vertices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry1__clipper_input_vertex_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry1_CLIPPER_INPUT_VERTEX_SLICE0_availability,
            },

            {
                .name = "CLIPPER INPUT VERTEX SLICE1",
                .symbol_name = "CLIPPER_INPUT_VERTEX_SLICE1",
                .desc = "Number of Clipper input vertices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry1__clipper_input_vertex_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry1_CLIPPER_INPUT_VERTEX_SLICE1_availability,
            },

            {
                .name = "CLIPPER INPUT VERTEX SLICE2",
                .symbol_name = "CLIPPER_INPUT_VERTEX_SLICE2",
                .desc = "Number of Clipper input vertices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry1__clipper_input_vertex_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry1_CLIPPER_INPUT_VERTEX_SLICE2_availability,
            },

            {
                .name = "CLIPPER INPUT VERTEX SLICE3",
                .symbol_name = "CLIPPER_INPUT_VERTEX_SLICE3",
                .desc = "Number of Clipper input vertices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry1__clipper_input_vertex_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry1_CLIPPER_INPUT_VERTEX_SLICE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__geometry1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "STREAMOUT OUTPUT VERTEX COUNT SLICE0",
                .symbol_name = "STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE0",
                .desc = "Number of vertices written by SOL",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry1__streamout_output_vertex_count_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry1_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE0_availability,
            },

            {
                .name = "STREAMOUT OUTPUT VERTEX COUNT SLICE1",
                .symbol_name = "STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE1",
                .desc = "Number of vertices written by SOL",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry1__streamout_output_vertex_count_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry1_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE1_availability,
            },

            {
                .name = "STREAMOUT OUTPUT VERTEX COUNT SLICE2",
                .symbol_name = "STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE2",
                .desc = "Number of vertices written by SOL",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry1__streamout_output_vertex_count_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry1_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE2_availability,
            },

            {
                .name = "STREAMOUT OUTPUT VERTEX COUNT SLICE3",
                .symbol_name = "STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE3",
                .desc = "Number of vertices written by SOL",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry1__streamout_output_vertex_count_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry1_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 9);
}

static bool acmgt2_geometry2_CLIPPER_INPUT_AVAILABLE_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry2_CLIPPER_INPUT_AVAILABLE_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry2_CLIPPER_INPUT_AVAILABLE_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry2_CLIPPER_INPUT_AVAILABLE_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry2_CLIPPER_OUTPUT_READY_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry2_CLIPPER_OUTPUT_READY_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry2_CLIPPER_OUTPUT_READY_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry2_CLIPPER_OUTPUT_READY_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry2_VERTEX_FETCH_INPUT_AVAILABLE_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry2_VERTEX_FETCH_INPUT_AVAILABLE_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry2_VERTEX_FETCH_INPUT_AVAILABLE_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry2_VERTEX_FETCH_INPUT_AVAILABLE_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry2_VERTEX_FETCH_OUTPUT_READY_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry2_VERTEX_FETCH_OUTPUT_READY_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry2_VERTEX_FETCH_OUTPUT_READY_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry2_VERTEX_FETCH_OUTPUT_READY_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_geometry2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Geometry2";
    metric_set->symbol_name = "Geometry2";
    metric_set->hw_config_guid = "80abe21d-174e-4d5f-a64f-34eea53e8c59";
    metric_set->counters = calloc(17, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_geometry2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "CLIPPER INPUT AVAILABLE SLICE0",
                .symbol_name = "CLIPPER_INPUT_AVAILABLE_SLICE0",
                .desc = "Percentage of time in which Clipper has input available (from Vertex Shader or SOL)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__geometry2__clipper_input_available_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt2_geometry2_CLIPPER_INPUT_AVAILABLE_SLICE0_availability,
            },

            {
                .name = "CLIPPER INPUT AVAILABLE SLICE1",
                .symbol_name = "CLIPPER_INPUT_AVAILABLE_SLICE1",
                .desc = "Percentage of time in which Clipper has input available (from Vertex Shader or SOL)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__geometry2__clipper_input_available_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt2_geometry2_CLIPPER_INPUT_AVAILABLE_SLICE1_availability,
            },

            {
                .name = "CLIPPER INPUT AVAILABLE SLICE2",
                .symbol_name = "CLIPPER_INPUT_AVAILABLE_SLICE2",
                .desc = "Percentage of time in which Clipper has input available (from Vertex Shader or SOL)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__geometry2__clipper_input_available_slice2__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt2_geometry2_CLIPPER_INPUT_AVAILABLE_SLICE2_availability,
            },

            {
                .name = "CLIPPER INPUT AVAILABLE SLICE3",
                .symbol_name = "CLIPPER_INPUT_AVAILABLE_SLICE3",
                .desc = "Percentage of time in which Clipper has input available (from Vertex Shader or SOL)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__geometry2__clipper_input_available_slice3__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt2_geometry2_CLIPPER_INPUT_AVAILABLE_SLICE3_availability,
            },

            {
                .name = "CLIPPER OUTPUT READY SLICE0",
                .symbol_name = "CLIPPER_OUTPUT_READY_SLICE0",
                .desc = "Percentage of time in which Clipper output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__geometry2__clipper_output_ready_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt2_geometry2_CLIPPER_OUTPUT_READY_SLICE0_availability,
            },

            {
                .name = "CLIPPER OUTPUT READY SLICE1",
                .symbol_name = "CLIPPER_OUTPUT_READY_SLICE1",
                .desc = "Percentage of time in which Clipper output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__geometry2__clipper_output_ready_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt2_geometry2_CLIPPER_OUTPUT_READY_SLICE1_availability,
            },

            {
                .name = "CLIPPER OUTPUT READY SLICE2",
                .symbol_name = "CLIPPER_OUTPUT_READY_SLICE2",
                .desc = "Percentage of time in which Clipper output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__geometry2__clipper_output_ready_slice2__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt2_geometry2_CLIPPER_OUTPUT_READY_SLICE2_availability,
            },

            {
                .name = "CLIPPER OUTPUT READY SLICE3",
                .symbol_name = "CLIPPER_OUTPUT_READY_SLICE3",
                .desc = "Percentage of time in which Clipper output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__geometry2__clipper_output_ready_slice3__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt2_geometry2_CLIPPER_OUTPUT_READY_SLICE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__geometry2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "VERTEX FETCH INPUT AVAILABLE SLICE0",
                .symbol_name = "VERTEX_FETCH_INPUT_AVAILABLE_SLICE0",
                .desc = "Percentage of time in which Vertex Fetch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__geometry2__vertex_fetch_input_available_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt2_geometry2_VERTEX_FETCH_INPUT_AVAILABLE_SLICE0_availability,
            },

            {
                .name = "VERTEX FETCH INPUT AVAILABLE SLICE1",
                .symbol_name = "VERTEX_FETCH_INPUT_AVAILABLE_SLICE1",
                .desc = "Percentage of time in which Vertex Fetch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__geometry2__vertex_fetch_input_available_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt2_geometry2_VERTEX_FETCH_INPUT_AVAILABLE_SLICE1_availability,
            },

            {
                .name = "VERTEX FETCH INPUT AVAILABLE SLICE2",
                .symbol_name = "VERTEX_FETCH_INPUT_AVAILABLE_SLICE2",
                .desc = "Percentage of time in which Vertex Fetch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__geometry2__vertex_fetch_input_available_slice2__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt2_geometry2_VERTEX_FETCH_INPUT_AVAILABLE_SLICE2_availability,
            },

            {
                .name = "VERTEX FETCH INPUT AVAILABLE SLICE3",
                .symbol_name = "VERTEX_FETCH_INPUT_AVAILABLE_SLICE3",
                .desc = "Percentage of time in which Vertex Fetch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__geometry2__vertex_fetch_input_available_slice3__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt2_geometry2_VERTEX_FETCH_INPUT_AVAILABLE_SLICE3_availability,
            },

            {
                .name = "VERTEX FETCH OUTPUT READY SLICE0",
                .symbol_name = "VERTEX_FETCH_OUTPUT_READY_SLICE0",
                .desc = "Percentage of time in which Vertex Fetch output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__geometry2__vertex_fetch_output_ready_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt2_geometry2_VERTEX_FETCH_OUTPUT_READY_SLICE0_availability,
            },

            {
                .name = "VERTEX FETCH OUTPUT READY SLICE1",
                .symbol_name = "VERTEX_FETCH_OUTPUT_READY_SLICE1",
                .desc = "Percentage of time in which Vertex Fetch output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__geometry2__vertex_fetch_output_ready_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt2_geometry2_VERTEX_FETCH_OUTPUT_READY_SLICE1_availability,
            },

            {
                .name = "VERTEX FETCH OUTPUT READY SLICE2",
                .symbol_name = "VERTEX_FETCH_OUTPUT_READY_SLICE2",
                .desc = "Percentage of time in which Vertex Fetch output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__geometry2__vertex_fetch_output_ready_slice2__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt2_geometry2_VERTEX_FETCH_OUTPUT_READY_SLICE2_availability,
            },

            {
                .name = "VERTEX FETCH OUTPUT READY SLICE3",
                .symbol_name = "VERTEX_FETCH_OUTPUT_READY_SLICE3",
                .desc = "Percentage of time in which Vertex Fetch output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__geometry2__vertex_fetch_output_ready_slice3__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt2_geometry2_VERTEX_FETCH_OUTPUT_READY_SLICE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 17);
}

static bool acmgt2_geometry3_CLIPPER_PRIMITIVE_CULL_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry3_CLIPPER_PRIMITIVE_CULL_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry3_CLIPPER_PRIMITIVE_CULL_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry3_CLIPPER_PRIMITIVE_CULL_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry3_STRIPSFAN_OUTPUT_READY_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry3_STRIPSFAN_OUTPUT_READY_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry3_STRIPSFAN_OUTPUT_READY_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry3_STRIPSFAN_OUTPUT_READY_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry3_VS_OUTPUT_READY_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry3_VS_OUTPUT_READY_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry3_VS_OUTPUT_READY_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry3_VS_OUTPUT_READY_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_geometry3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Geometry3";
    metric_set->symbol_name = "Geometry3";
    metric_set->hw_config_guid = "f736c728-c16c-4125-97c3-b7e2f7d25ecc";
    metric_set->counters = calloc(13, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_geometry3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "CLIPPER PRIMITIVE CULL SLICE0",
                .symbol_name = "CLIPPER_PRIMITIVE_CULL_SLICE0",
                .desc = "Number of Clipper early cull primitives",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry3__clipper_primitive_cull_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry3_CLIPPER_PRIMITIVE_CULL_SLICE0_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE CULL SLICE1",
                .symbol_name = "CLIPPER_PRIMITIVE_CULL_SLICE1",
                .desc = "Number of Clipper early cull primitives",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry3__clipper_primitive_cull_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry3_CLIPPER_PRIMITIVE_CULL_SLICE1_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE CULL SLICE2",
                .symbol_name = "CLIPPER_PRIMITIVE_CULL_SLICE2",
                .desc = "Number of Clipper early cull primitives",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry3__clipper_primitive_cull_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry3_CLIPPER_PRIMITIVE_CULL_SLICE2_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE CULL SLICE3",
                .symbol_name = "CLIPPER_PRIMITIVE_CULL_SLICE3",
                .desc = "Number of Clipper early cull primitives",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry3__clipper_primitive_cull_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry3_CLIPPER_PRIMITIVE_CULL_SLICE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__geometry3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "STRIPSFAN OUTPUT READY SLICE0",
                .symbol_name = "STRIPSFAN_OUTPUT_READY_SLICE0",
                .desc = "Percentage of time in which in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__geometry3__stripsfan_output_ready_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt2_geometry3_STRIPSFAN_OUTPUT_READY_SLICE0_availability,
            },

            {
                .name = "STRIPSFAN OUTPUT READY SLICE1",
                .symbol_name = "STRIPSFAN_OUTPUT_READY_SLICE1",
                .desc = "Percentage of time in which in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__geometry3__stripsfan_output_ready_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt2_geometry3_STRIPSFAN_OUTPUT_READY_SLICE1_availability,
            },

            {
                .name = "STRIPSFAN OUTPUT READY SLICE2",
                .symbol_name = "STRIPSFAN_OUTPUT_READY_SLICE2",
                .desc = "Percentage of time in which in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__geometry3__stripsfan_output_ready_slice2__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt2_geometry3_STRIPSFAN_OUTPUT_READY_SLICE2_availability,
            },

            {
                .name = "STRIPSFAN OUTPUT READY SLICE3",
                .symbol_name = "STRIPSFAN_OUTPUT_READY_SLICE3",
                .desc = "Percentage of time in which in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__geometry3__stripsfan_output_ready_slice3__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt2_geometry3_STRIPSFAN_OUTPUT_READY_SLICE3_availability,
            },

            {
                .name = "VS OUTPUT READY SLICE0",
                .symbol_name = "VS_OUTPUT_READY_SLICE0",
                .desc = "Percentage of time in which Vertex Shader output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__geometry3__vs_output_ready_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt2_geometry3_VS_OUTPUT_READY_SLICE0_availability,
            },

            {
                .name = "VS OUTPUT READY SLICE1",
                .symbol_name = "VS_OUTPUT_READY_SLICE1",
                .desc = "Percentage of time in which Vertex Shader output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__geometry3__vs_output_ready_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt2_geometry3_VS_OUTPUT_READY_SLICE1_availability,
            },

            {
                .name = "VS OUTPUT READY SLICE2",
                .symbol_name = "VS_OUTPUT_READY_SLICE2",
                .desc = "Percentage of time in which Vertex Shader output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__geometry3__vs_output_ready_slice2__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt2_geometry3_VS_OUTPUT_READY_SLICE2_availability,
            },

            {
                .name = "VS OUTPUT READY SLICE3",
                .symbol_name = "VS_OUTPUT_READY_SLICE3",
                .desc = "Percentage of time in which Vertex Shader output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__geometry3__vs_output_ready_slice3__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt2_geometry3_VS_OUTPUT_READY_SLICE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 13);
}

static bool acmgt2_geometry4_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry4_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry4_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry4_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry4_CLIPPER_PRIMITIVE_OUTPUT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry4_CLIPPER_PRIMITIVE_OUTPUT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry4_CLIPPER_PRIMITIVE_OUTPUT_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry4_CLIPPER_PRIMITIVE_OUTPUT_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_geometry4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Geometry4";
    metric_set->symbol_name = "Geometry4";
    metric_set->hw_config_guid = "81996036-5d85-4ca6-83f8-a5bce6428d80";
    metric_set->counters = calloc(9, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_geometry4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "CLIPPER PRIMITIVE FAR NEAR CLIP SLICE0",
                .symbol_name = "CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE0",
                .desc = "Number of primitives clipped by Clipper due to near/far planes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry4__clipper_primitive_far_near_clip_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry4_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE0_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE FAR NEAR CLIP SLICE1",
                .symbol_name = "CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE1",
                .desc = "Number of primitives clipped by Clipper due to near/far planes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry4__clipper_primitive_far_near_clip_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry4_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE1_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE FAR NEAR CLIP SLICE2",
                .symbol_name = "CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE2",
                .desc = "Number of primitives clipped by Clipper due to near/far planes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry4__clipper_primitive_far_near_clip_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry4_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE2_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE FAR NEAR CLIP SLICE3",
                .symbol_name = "CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE3",
                .desc = "Number of primitives clipped by Clipper due to near/far planes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry4__clipper_primitive_far_near_clip_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry4_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE3_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE OUTPUT SLICE0",
                .symbol_name = "CLIPPER_PRIMITIVE_OUTPUT_SLICE0",
                .desc = "Number of primitives going out of Clipper, must clip plus the trivial accept",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry4__clipper_primitive_output_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry4_CLIPPER_PRIMITIVE_OUTPUT_SLICE0_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE OUTPUT SLICE1",
                .symbol_name = "CLIPPER_PRIMITIVE_OUTPUT_SLICE1",
                .desc = "Number of primitives going out of Clipper, must clip plus the trivial accept",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry4__clipper_primitive_output_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry4_CLIPPER_PRIMITIVE_OUTPUT_SLICE1_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE OUTPUT SLICE2",
                .symbol_name = "CLIPPER_PRIMITIVE_OUTPUT_SLICE2",
                .desc = "Number of primitives going out of Clipper, must clip plus the trivial accept",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry4__clipper_primitive_output_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry4_CLIPPER_PRIMITIVE_OUTPUT_SLICE2_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE OUTPUT SLICE3",
                .symbol_name = "CLIPPER_PRIMITIVE_OUTPUT_SLICE3",
                .desc = "Number of primitives going out of Clipper, must clip plus the trivial accept",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry4__clipper_primitive_output_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry4_CLIPPER_PRIMITIVE_OUTPUT_SLICE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__geometry4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 9);
}

static bool acmgt2_geometry5_CLIPPER_TRANSACTION_OUTPUT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry5_CLIPPER_TRANSACTION_OUTPUT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry5_CLIPPER_TRANSACTION_OUTPUT_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry5_CLIPPER_TRANSACTION_OUTPUT_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry5_STRIPSFAN_OBJECTS_CULL_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry5_STRIPSFAN_OBJECTS_CULL_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry5_STRIPSFAN_OBJECTS_CULL_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry5_STRIPSFAN_OBJECTS_CULL_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry5_STRIPSFAN_OBJECT_COUNT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry5_STRIPSFAN_OBJECT_COUNT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry5_STRIPSFAN_OBJECT_COUNT_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_geometry5_STRIPSFAN_OBJECT_COUNT_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_geometry5_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Geometry5";
    metric_set->symbol_name = "Geometry5";
    metric_set->hw_config_guid = "09075af6-ccdd-49bf-8581-92a84840bbb5";
    metric_set->counters = calloc(13, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_geometry5_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "CLIPPER TRANSACTION OUTPUT SLICE0",
                .symbol_name = "CLIPPER_TRANSACTION_OUTPUT_SLICE0",
                .desc = "Number of elements pushed by Clipper into Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry5__clipper_transaction_output_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry5_CLIPPER_TRANSACTION_OUTPUT_SLICE0_availability,
            },

            {
                .name = "CLIPPER TRANSACTION OUTPUT SLICE1",
                .symbol_name = "CLIPPER_TRANSACTION_OUTPUT_SLICE1",
                .desc = "Number of elements pushed by Clipper into Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry5__clipper_transaction_output_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry5_CLIPPER_TRANSACTION_OUTPUT_SLICE1_availability,
            },

            {
                .name = "CLIPPER TRANSACTION OUTPUT SLICE2",
                .symbol_name = "CLIPPER_TRANSACTION_OUTPUT_SLICE2",
                .desc = "Number of elements pushed by Clipper into Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry5__clipper_transaction_output_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry5_CLIPPER_TRANSACTION_OUTPUT_SLICE2_availability,
            },

            {
                .name = "CLIPPER TRANSACTION OUTPUT SLICE3",
                .symbol_name = "CLIPPER_TRANSACTION_OUTPUT_SLICE3",
                .desc = "Number of elements pushed by Clipper into Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry5__clipper_transaction_output_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry5_CLIPPER_TRANSACTION_OUTPUT_SLICE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__geometry5__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "STRIPSFAN OBJECTS CULL SLICE0",
                .symbol_name = "STRIPSFAN_OBJECTS_CULL_SLICE0",
                .desc = "Number of simple culled objects in Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry5__stripsfan_objects_cull_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry5_STRIPSFAN_OBJECTS_CULL_SLICE0_availability,
            },

            {
                .name = "STRIPSFAN OBJECTS CULL SLICE1",
                .symbol_name = "STRIPSFAN_OBJECTS_CULL_SLICE1",
                .desc = "Number of simple culled objects in Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry5__stripsfan_objects_cull_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry5_STRIPSFAN_OBJECTS_CULL_SLICE1_availability,
            },

            {
                .name = "STRIPSFAN OBJECTS CULL SLICE2",
                .symbol_name = "STRIPSFAN_OBJECTS_CULL_SLICE2",
                .desc = "Number of simple culled objects in Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry5__stripsfan_objects_cull_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry5_STRIPSFAN_OBJECTS_CULL_SLICE2_availability,
            },

            {
                .name = "STRIPSFAN OBJECTS CULL SLICE3",
                .symbol_name = "STRIPSFAN_OBJECTS_CULL_SLICE3",
                .desc = "Number of simple culled objects in Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry5__stripsfan_objects_cull_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry5_STRIPSFAN_OBJECTS_CULL_SLICE3_availability,
            },

            {
                .name = "STRIPSFAN OBJECT COUNT SLICE0",
                .symbol_name = "STRIPSFAN_OBJECT_COUNT_SLICE0",
                .desc = "Number of objects exiting Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry5__stripsfan_object_count_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry5_STRIPSFAN_OBJECT_COUNT_SLICE0_availability,
            },

            {
                .name = "STRIPSFAN OBJECT COUNT SLICE1",
                .symbol_name = "STRIPSFAN_OBJECT_COUNT_SLICE1",
                .desc = "Number of objects exiting Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry5__stripsfan_object_count_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry5_STRIPSFAN_OBJECT_COUNT_SLICE1_availability,
            },

            {
                .name = "STRIPSFAN OBJECT COUNT SLICE2",
                .symbol_name = "STRIPSFAN_OBJECT_COUNT_SLICE2",
                .desc = "Number of objects exiting Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry5__stripsfan_object_count_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry5_STRIPSFAN_OBJECT_COUNT_SLICE2_availability,
            },

            {
                .name = "STRIPSFAN OBJECT COUNT SLICE3",
                .symbol_name = "STRIPSFAN_OBJECT_COUNT_SLICE3",
                .desc = "Number of objects exiting Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__geometry5__stripsfan_object_count_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt2_geometry5_STRIPSFAN_OBJECT_COUNT_SLICE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 13);
}

static bool acmgt2_l1_cache1_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache1_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache1_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache1_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache1";
    metric_set->symbol_name = "L1Cache1";
    metric_set->hw_config_guid = "09aaf18b-f85d-443d-9644-9cc847782212";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache1__load_store_cache_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache1_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache1__load_store_cache_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache1_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache1__load_store_cache_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache1_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache1__load_store_cache_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache1_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache2_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache2_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache2_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache2_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache2";
    metric_set->symbol_name = "L1Cache2";
    metric_set->hw_config_guid = "66096c29-519c-4063-9d03-e04e50d8d478";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache2__load_store_cache_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache2_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache2__load_store_cache_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache2_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache2__load_store_cache_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache2_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache2__load_store_cache_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache2_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache3_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache3_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache3_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache3_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache3";
    metric_set->symbol_name = "L1Cache3";
    metric_set->hw_config_guid = "2237bc33-3e20-446a-8d7d-7ac651314287";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE10",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE10",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache3__load_store_cache_input_available_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache3_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE10_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE11",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE11",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache3__load_store_cache_input_available_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache3_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE11_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE8",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE8",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache3__load_store_cache_input_available_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache3_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE8_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE9",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE9",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache3__load_store_cache_input_available_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache3_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache4_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache4_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache4_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache4_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache4";
    metric_set->symbol_name = "L1Cache4";
    metric_set->hw_config_guid = "c4e31e05-c514-4e2e-9686-f4225de24213";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache4__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE12",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE12",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache4__load_store_cache_input_available_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache4_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE12_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE13",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE13",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache4__load_store_cache_input_available_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache4_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE13_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE14",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE14",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache4__load_store_cache_input_available_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache4_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE14_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE15",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE15",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache4__load_store_cache_input_available_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache4_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache5_LOAD_STORE_CACHE_OUTPUT_READY_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache5_LOAD_STORE_CACHE_OUTPUT_READY_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache5_LOAD_STORE_CACHE_OUTPUT_READY_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache5_LOAD_STORE_CACHE_OUTPUT_READY_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache5_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache5";
    metric_set->symbol_name = "L1Cache5";
    metric_set->hw_config_guid = "1c608270-6be1-4381-bd2a-e7e5e6ec0c84";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache5_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache5__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache5__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache5__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache5__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE0",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache5__load_store_cache_output_ready_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache5_LOAD_STORE_CACHE_OUTPUT_READY_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE1",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache5__load_store_cache_output_ready_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache5_LOAD_STORE_CACHE_OUTPUT_READY_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE2",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache5__load_store_cache_output_ready_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache5_LOAD_STORE_CACHE_OUTPUT_READY_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE3",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache5__load_store_cache_output_ready_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache5_LOAD_STORE_CACHE_OUTPUT_READY_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache6_LOAD_STORE_CACHE_OUTPUT_READY_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache6_LOAD_STORE_CACHE_OUTPUT_READY_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache6_LOAD_STORE_CACHE_OUTPUT_READY_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache6_LOAD_STORE_CACHE_OUTPUT_READY_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache6_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache6";
    metric_set->symbol_name = "L1Cache6";
    metric_set->hw_config_guid = "8ea12c1c-6dfc-4539-b7cc-4c0ed0a0e172";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache6_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache6__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache6__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache6__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache6__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE4",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache6__load_store_cache_output_ready_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache6_LOAD_STORE_CACHE_OUTPUT_READY_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE5",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache6__load_store_cache_output_ready_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache6_LOAD_STORE_CACHE_OUTPUT_READY_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE6",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache6__load_store_cache_output_ready_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache6_LOAD_STORE_CACHE_OUTPUT_READY_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE7",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache6__load_store_cache_output_ready_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache6_LOAD_STORE_CACHE_OUTPUT_READY_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache7_LOAD_STORE_CACHE_OUTPUT_READY_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache7_LOAD_STORE_CACHE_OUTPUT_READY_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache7_LOAD_STORE_CACHE_OUTPUT_READY_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache7_LOAD_STORE_CACHE_OUTPUT_READY_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache7_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache7";
    metric_set->symbol_name = "L1Cache7";
    metric_set->hw_config_guid = "563cb980-9a7e-469f-8fa7-75fbbda1b6a7";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache7_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache7__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache7__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache7__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache7__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE10",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE10",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache7__load_store_cache_output_ready_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache7_LOAD_STORE_CACHE_OUTPUT_READY_XECORE10_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE11",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE11",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache7__load_store_cache_output_ready_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache7_LOAD_STORE_CACHE_OUTPUT_READY_XECORE11_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE8",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE8",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache7__load_store_cache_output_ready_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache7_LOAD_STORE_CACHE_OUTPUT_READY_XECORE8_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE9",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE9",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache7__load_store_cache_output_ready_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache7_LOAD_STORE_CACHE_OUTPUT_READY_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache8_LOAD_STORE_CACHE_OUTPUT_READY_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache8_LOAD_STORE_CACHE_OUTPUT_READY_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache8_LOAD_STORE_CACHE_OUTPUT_READY_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache8_LOAD_STORE_CACHE_OUTPUT_READY_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache8_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache8";
    metric_set->symbol_name = "L1Cache8";
    metric_set->hw_config_guid = "203752ae-e3b3-4895-85cd-9cef09669196";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache8_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache8__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache8__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache8__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache8__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE12",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE12",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache8__load_store_cache_output_ready_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache8_LOAD_STORE_CACHE_OUTPUT_READY_XECORE12_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE13",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE13",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache8__load_store_cache_output_ready_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache8_LOAD_STORE_CACHE_OUTPUT_READY_XECORE13_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE14",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE14",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache8__load_store_cache_output_ready_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache8_LOAD_STORE_CACHE_OUTPUT_READY_XECORE14_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE15",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE15",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l1_cache8__load_store_cache_output_ready_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache8_LOAD_STORE_CACHE_OUTPUT_READY_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache9_LOAD_STORE_CACHE_L3_READ_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache9_LOAD_STORE_CACHE_L3_READ_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache9_LOAD_STORE_CACHE_L3_READ_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache9_LOAD_STORE_CACHE_L3_READ_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache9_LOAD_STORE_CACHE_L3_READ_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache9_LOAD_STORE_CACHE_L3_READ_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache9_LOAD_STORE_CACHE_L3_READ_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache9_LOAD_STORE_CACHE_L3_READ_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache9_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache9";
    metric_set->symbol_name = "L1Cache9";
    metric_set->hw_config_guid = "94ae89ad-096f-42c3-a666-b3bb904605e9";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache9_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache9__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache9__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache9__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache9__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE0",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache9__load_store_cache_l3_read_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache9_LOAD_STORE_CACHE_L3_READ_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE1",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache9__load_store_cache_l3_read_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache9_LOAD_STORE_CACHE_L3_READ_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE2",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache9__load_store_cache_l3_read_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache9_LOAD_STORE_CACHE_L3_READ_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE3",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache9__load_store_cache_l3_read_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache9_LOAD_STORE_CACHE_L3_READ_XECORE3_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE4",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache9__load_store_cache_l3_read_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache9_LOAD_STORE_CACHE_L3_READ_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE5",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache9__load_store_cache_l3_read_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache9_LOAD_STORE_CACHE_L3_READ_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE6",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache9__load_store_cache_l3_read_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache9_LOAD_STORE_CACHE_L3_READ_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE7",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache9__load_store_cache_l3_read_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache9_LOAD_STORE_CACHE_L3_READ_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_l1_cache10_LOAD_STORE_CACHE_L3_READ_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache10_LOAD_STORE_CACHE_L3_READ_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache10_LOAD_STORE_CACHE_L3_READ_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache10_LOAD_STORE_CACHE_L3_READ_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache10_LOAD_STORE_CACHE_L3_READ_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache10_LOAD_STORE_CACHE_L3_READ_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache10_LOAD_STORE_CACHE_L3_READ_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache10_LOAD_STORE_CACHE_L3_READ_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache10_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache10";
    metric_set->symbol_name = "L1Cache10";
    metric_set->hw_config_guid = "97f2d572-60c2-422d-b9eb-f0edb2f9e788";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache10_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache10__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache10__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache10__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache10__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE10",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE10",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache10__load_store_cache_l3_read_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache10_LOAD_STORE_CACHE_L3_READ_XECORE10_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE11",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE11",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache10__load_store_cache_l3_read_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache10_LOAD_STORE_CACHE_L3_READ_XECORE11_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE12",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE12",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache10__load_store_cache_l3_read_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache10_LOAD_STORE_CACHE_L3_READ_XECORE12_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE13",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE13",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache10__load_store_cache_l3_read_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache10_LOAD_STORE_CACHE_L3_READ_XECORE13_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE14",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE14",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache10__load_store_cache_l3_read_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache10_LOAD_STORE_CACHE_L3_READ_XECORE14_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE15",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE15",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache10__load_store_cache_l3_read_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache10_LOAD_STORE_CACHE_L3_READ_XECORE15_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE8",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE8",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache10__load_store_cache_l3_read_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache10_LOAD_STORE_CACHE_L3_READ_XECORE8_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE9",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE9",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache10__load_store_cache_l3_read_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache10_LOAD_STORE_CACHE_L3_READ_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_l1_cache11_LOAD_STORE_CACHE_L3_WRITE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache11_LOAD_STORE_CACHE_L3_WRITE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache11_LOAD_STORE_CACHE_L3_WRITE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache11_LOAD_STORE_CACHE_L3_WRITE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache11_LOAD_STORE_CACHE_L3_WRITE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache11_LOAD_STORE_CACHE_L3_WRITE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache11_LOAD_STORE_CACHE_L3_WRITE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache11_LOAD_STORE_CACHE_L3_WRITE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache11_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache11";
    metric_set->symbol_name = "L1Cache11";
    metric_set->hw_config_guid = "df474009-ed7f-4a1b-84a5-473b35804e42";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache11_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache11__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache11__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache11__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache11__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE0",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache11__load_store_cache_l3_write_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache11_LOAD_STORE_CACHE_L3_WRITE_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE1",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache11__load_store_cache_l3_write_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache11_LOAD_STORE_CACHE_L3_WRITE_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE2",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache11__load_store_cache_l3_write_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache11_LOAD_STORE_CACHE_L3_WRITE_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE3",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache11__load_store_cache_l3_write_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache11_LOAD_STORE_CACHE_L3_WRITE_XECORE3_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE4",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache11__load_store_cache_l3_write_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache11_LOAD_STORE_CACHE_L3_WRITE_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE5",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache11__load_store_cache_l3_write_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache11_LOAD_STORE_CACHE_L3_WRITE_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE6",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache11__load_store_cache_l3_write_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache11_LOAD_STORE_CACHE_L3_WRITE_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE7",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache11__load_store_cache_l3_write_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache11_LOAD_STORE_CACHE_L3_WRITE_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_l1_cache12_LOAD_STORE_CACHE_L3_WRITE_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache12_LOAD_STORE_CACHE_L3_WRITE_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache12_LOAD_STORE_CACHE_L3_WRITE_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache12_LOAD_STORE_CACHE_L3_WRITE_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache12_LOAD_STORE_CACHE_L3_WRITE_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache12_LOAD_STORE_CACHE_L3_WRITE_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache12_LOAD_STORE_CACHE_L3_WRITE_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache12_LOAD_STORE_CACHE_L3_WRITE_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache12_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache12";
    metric_set->symbol_name = "L1Cache12";
    metric_set->hw_config_guid = "7c3b945e-3b30-4ef2-8544-34b535ca90b8";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache12_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache12__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache12__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache12__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache12__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE10",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE10",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache12__load_store_cache_l3_write_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache12_LOAD_STORE_CACHE_L3_WRITE_XECORE10_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE11",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE11",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache12__load_store_cache_l3_write_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache12_LOAD_STORE_CACHE_L3_WRITE_XECORE11_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE12",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE12",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache12__load_store_cache_l3_write_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache12_LOAD_STORE_CACHE_L3_WRITE_XECORE12_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE13",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE13",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache12__load_store_cache_l3_write_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache12_LOAD_STORE_CACHE_L3_WRITE_XECORE13_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE14",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE14",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache12__load_store_cache_l3_write_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache12_LOAD_STORE_CACHE_L3_WRITE_XECORE14_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE15",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE15",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache12__load_store_cache_l3_write_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache12_LOAD_STORE_CACHE_L3_WRITE_XECORE15_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE8",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE8",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache12__load_store_cache_l3_write_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache12_LOAD_STORE_CACHE_L3_WRITE_XECORE8_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE9",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE9",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache12__load_store_cache_l3_write_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache12_LOAD_STORE_CACHE_L3_WRITE_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_l1_cache13_LOAD_STORE_CACHE_ACCESS_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache13_LOAD_STORE_CACHE_ACCESS_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache13_LOAD_STORE_CACHE_ACCESS_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache13_LOAD_STORE_CACHE_ACCESS_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache13_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache13";
    metric_set->symbol_name = "L1Cache13";
    metric_set->hw_config_guid = "a55bc2da-2c6f-4774-a20e-bd79371902db";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache13_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache13__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache13__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache13__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache13__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE0",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache13__load_store_cache_access_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache13_LOAD_STORE_CACHE_ACCESS_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE1",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache13__load_store_cache_access_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache13_LOAD_STORE_CACHE_ACCESS_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE2",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache13__load_store_cache_access_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache13_LOAD_STORE_CACHE_ACCESS_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE3",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache13__load_store_cache_access_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache13_LOAD_STORE_CACHE_ACCESS_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache14_LOAD_STORE_CACHE_ACCESS_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache14_LOAD_STORE_CACHE_ACCESS_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache14_LOAD_STORE_CACHE_ACCESS_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache14_LOAD_STORE_CACHE_ACCESS_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache14_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache14";
    metric_set->symbol_name = "L1Cache14";
    metric_set->hw_config_guid = "0e4e660e-96bf-4b86-90cb-64ec0532fd03";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache14_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache14__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache14__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache14__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache14__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE4",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache14__load_store_cache_access_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache14_LOAD_STORE_CACHE_ACCESS_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE5",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache14__load_store_cache_access_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache14_LOAD_STORE_CACHE_ACCESS_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE6",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache14__load_store_cache_access_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache14_LOAD_STORE_CACHE_ACCESS_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE7",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache14__load_store_cache_access_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache14_LOAD_STORE_CACHE_ACCESS_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache15_LOAD_STORE_CACHE_ACCESS_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache15_LOAD_STORE_CACHE_ACCESS_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache15_LOAD_STORE_CACHE_ACCESS_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache15_LOAD_STORE_CACHE_ACCESS_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache15_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache15";
    metric_set->symbol_name = "L1Cache15";
    metric_set->hw_config_guid = "8bb39f7a-53b5-403d-94fb-f1f7350d2ce0";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache15_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache15__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache15__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache15__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache15__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE10",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE10",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache15__load_store_cache_access_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache15_LOAD_STORE_CACHE_ACCESS_XECORE10_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE11",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE11",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache15__load_store_cache_access_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache15_LOAD_STORE_CACHE_ACCESS_XECORE11_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE8",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE8",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache15__load_store_cache_access_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache15_LOAD_STORE_CACHE_ACCESS_XECORE8_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE9",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE9",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache15__load_store_cache_access_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache15_LOAD_STORE_CACHE_ACCESS_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache16_LOAD_STORE_CACHE_ACCESS_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache16_LOAD_STORE_CACHE_ACCESS_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache16_LOAD_STORE_CACHE_ACCESS_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache16_LOAD_STORE_CACHE_ACCESS_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache16_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache16";
    metric_set->symbol_name = "L1Cache16";
    metric_set->hw_config_guid = "f4b433d4-2af0-45c2-b61c-7e9a4db553cc";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache16_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache16__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache16__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache16__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache16__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE12",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE12",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache16__load_store_cache_access_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache16_LOAD_STORE_CACHE_ACCESS_XECORE12_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE13",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE13",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache16__load_store_cache_access_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache16_LOAD_STORE_CACHE_ACCESS_XECORE13_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE14",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE14",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache16__load_store_cache_access_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache16_LOAD_STORE_CACHE_ACCESS_XECORE14_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE15",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE15",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache16__load_store_cache_access_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache16_LOAD_STORE_CACHE_ACCESS_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache17_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache17_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache17_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache17_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache17_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache17";
    metric_set->symbol_name = "L1Cache17";
    metric_set->hw_config_guid = "bde419e8-3eb1-4525-9317-f74900301c1d";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache17_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache17__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache17__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache17__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache17__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE0",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache17__load_store_cache_partial_write_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache17_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE1",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache17__load_store_cache_partial_write_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache17_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE2",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache17__load_store_cache_partial_write_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache17_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE3",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache17__load_store_cache_partial_write_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache17_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache18_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache18_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache18_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache18_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache18_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache18";
    metric_set->symbol_name = "L1Cache18";
    metric_set->hw_config_guid = "7a8bccbc-6900-470c-8204-2dc21423e247";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache18_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache18__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache18__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache18__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache18__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE4",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache18__load_store_cache_partial_write_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache18_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE5",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache18__load_store_cache_partial_write_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache18_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE6",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache18__load_store_cache_partial_write_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache18_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE7",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache18__load_store_cache_partial_write_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache18_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache19_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache19_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache19_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache19_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache19_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache19";
    metric_set->symbol_name = "L1Cache19";
    metric_set->hw_config_guid = "2d1b823a-ee3a-43b4-b46f-379ab7920aef";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache19_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache19__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache19__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache19__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache19__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE10",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE10",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache19__load_store_cache_partial_write_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache19_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE10_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE11",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE11",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache19__load_store_cache_partial_write_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache19_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE11_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE8",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE8",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache19__load_store_cache_partial_write_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache19_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE8_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE9",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE9",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache19__load_store_cache_partial_write_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache19_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache20_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache20_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache20_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache20_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache20_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache20";
    metric_set->symbol_name = "L1Cache20";
    metric_set->hw_config_guid = "3b20c2df-ccd7-4c6c-a211-5724fa8bda6d";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache20_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache20__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache20__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache20__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache20__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE12",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE12",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache20__load_store_cache_partial_write_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache20_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE12_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE13",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE13",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache20__load_store_cache_partial_write_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache20_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE13_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE14",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE14",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache20__load_store_cache_partial_write_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache20_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE14_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE15",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE15",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache20__load_store_cache_partial_write_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache20_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache21_LOAD_STORE_CACHE_HIT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache21_LOAD_STORE_CACHE_HIT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache21_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache21";
    metric_set->symbol_name = "L1Cache21";
    metric_set->hw_config_guid = "186189aa-0aaf-4c63-9977-d5dfd5eb5084";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache21_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache21__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache21__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache21__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache21__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE0",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache21__load_store_cache_hit_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache21_LOAD_STORE_CACHE_HIT_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE1",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache21__load_store_cache_hit_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache21_LOAD_STORE_CACHE_HIT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache22_LOAD_STORE_CACHE_HIT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache22_LOAD_STORE_CACHE_HIT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache22_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache22";
    metric_set->symbol_name = "L1Cache22";
    metric_set->hw_config_guid = "13dee569-144e-4bb0-b2da-e902336c2f08";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache22_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache22__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache22__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache22__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache22__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE2",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache22__load_store_cache_hit_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache22_LOAD_STORE_CACHE_HIT_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE3",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache22__load_store_cache_hit_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache22_LOAD_STORE_CACHE_HIT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache23_LOAD_STORE_CACHE_HIT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache23_LOAD_STORE_CACHE_HIT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache23_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache23";
    metric_set->symbol_name = "L1Cache23";
    metric_set->hw_config_guid = "4b450172-544b-4249-87a4-96acdde97d6c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache23_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache23__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache23__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache23__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache23__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE4",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache23__load_store_cache_hit_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache23_LOAD_STORE_CACHE_HIT_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE5",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache23__load_store_cache_hit_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache23_LOAD_STORE_CACHE_HIT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache24_LOAD_STORE_CACHE_HIT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache24_LOAD_STORE_CACHE_HIT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache24_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache24";
    metric_set->symbol_name = "L1Cache24";
    metric_set->hw_config_guid = "2bf27543-d6b4-4cb7-b53a-3b83fe6c102e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache24_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache24__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache24__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache24__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache24__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE6",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache24__load_store_cache_hit_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache24_LOAD_STORE_CACHE_HIT_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE7",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache24__load_store_cache_hit_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache24_LOAD_STORE_CACHE_HIT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache25_LOAD_STORE_CACHE_HIT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache25_LOAD_STORE_CACHE_HIT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache25_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache25";
    metric_set->symbol_name = "L1Cache25";
    metric_set->hw_config_guid = "e1066219-5e33-4b74-b056-94b3a62a7900";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache25_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache25__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache25__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache25__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache25__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE8",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE8",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache25__load_store_cache_hit_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache25_LOAD_STORE_CACHE_HIT_XECORE8_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE9",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE9",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache25__load_store_cache_hit_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache25_LOAD_STORE_CACHE_HIT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache26_LOAD_STORE_CACHE_HIT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache26_LOAD_STORE_CACHE_HIT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache26_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache26";
    metric_set->symbol_name = "L1Cache26";
    metric_set->hw_config_guid = "30ee8347-968a-4ec0-985a-234c0d5ee72e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache26_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache26__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache26__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache26__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache26__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE10",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE10",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache26__load_store_cache_hit_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache26_LOAD_STORE_CACHE_HIT_XECORE10_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE11",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE11",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache26__load_store_cache_hit_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache26_LOAD_STORE_CACHE_HIT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache27_LOAD_STORE_CACHE_HIT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache27_LOAD_STORE_CACHE_HIT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache27_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache27";
    metric_set->symbol_name = "L1Cache27";
    metric_set->hw_config_guid = "d38715b6-5d8d-44ad-82b4-83d6a143d61c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache27_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache27__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache27__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache27__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache27__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE12",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE12",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache27__load_store_cache_hit_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache27_LOAD_STORE_CACHE_HIT_XECORE12_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE13",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE13",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache27__load_store_cache_hit_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache27_LOAD_STORE_CACHE_HIT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache28_LOAD_STORE_CACHE_HIT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache28_LOAD_STORE_CACHE_HIT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache28_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache28";
    metric_set->symbol_name = "L1Cache28";
    metric_set->hw_config_guid = "1f851454-2f9c-44da-b403-82493b4e41ee";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache28_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache28__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache28__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache28__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache28__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE14",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE14",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache28__load_store_cache_hit_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache28_LOAD_STORE_CACHE_HIT_XECORE14_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE15",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE15",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache28__load_store_cache_hit_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache28_LOAD_STORE_CACHE_HIT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache29_SLM_BANK_CONFLICT_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache29_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache29";
    metric_set->symbol_name = "L1Cache29";
    metric_set->hw_config_guid = "32f03e2e-890a-4db8-9d12-cd2a9b46456c";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache29_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache29__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache29__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache29__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache29__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE0",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE0",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache29__slm_bank_conflict_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache29_SLM_BANK_CONFLICT_COUNT_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_l1_cache30_SLM_BANK_CONFLICT_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache30_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache30";
    metric_set->symbol_name = "L1Cache30";
    metric_set->hw_config_guid = "f124e69c-983e-4d57-bd6a-26af2dd386ba";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache30_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache30__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache30__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache30__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache30__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE1",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE1",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache30__slm_bank_conflict_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache30_SLM_BANK_CONFLICT_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_l1_cache31_SLM_BANK_CONFLICT_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache31_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache31";
    metric_set->symbol_name = "L1Cache31";
    metric_set->hw_config_guid = "77bfa913-7775-4d45-8c3f-4510520c7b15";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache31_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache31__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache31__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache31__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache31__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE2",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE2",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache31__slm_bank_conflict_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache31_SLM_BANK_CONFLICT_COUNT_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_l1_cache32_SLM_BANK_CONFLICT_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache32_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache32";
    metric_set->symbol_name = "L1Cache32";
    metric_set->hw_config_guid = "9ed928dc-d0e2-455c-a2ef-b5cac335bab9";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache32_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache32__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache32__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache32__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache32__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE3",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE3",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache32__slm_bank_conflict_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache32_SLM_BANK_CONFLICT_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_l1_cache33_SLM_BANK_CONFLICT_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache33_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache33";
    metric_set->symbol_name = "L1Cache33";
    metric_set->hw_config_guid = "6ac07bf2-e77c-4a85-97d8-08d9f86b3f77";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache33_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache33__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache33__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache33__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache33__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE4",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE4",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache33__slm_bank_conflict_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache33_SLM_BANK_CONFLICT_COUNT_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_l1_cache34_SLM_BANK_CONFLICT_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache34_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache34";
    metric_set->symbol_name = "L1Cache34";
    metric_set->hw_config_guid = "d8fde355-eb9a-4490-b61f-31fb98ba4f70";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache34_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache34__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache34__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache34__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache34__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE5",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE5",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache34__slm_bank_conflict_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache34_SLM_BANK_CONFLICT_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_l1_cache35_SLM_BANK_CONFLICT_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache35_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache35";
    metric_set->symbol_name = "L1Cache35";
    metric_set->hw_config_guid = "c045a7e6-dd83-419c-abff-643ccb4ff70f";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache35_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache35__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache35__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache35__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache35__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE6",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE6",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache35__slm_bank_conflict_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache35_SLM_BANK_CONFLICT_COUNT_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_l1_cache36_SLM_BANK_CONFLICT_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache36_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache36";
    metric_set->symbol_name = "L1Cache36";
    metric_set->hw_config_guid = "5c6b81b0-056f-451e-b3be-dea10b2c1ecb";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache36_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache36__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache36__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache36__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache36__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE7",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE7",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache36__slm_bank_conflict_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache36_SLM_BANK_CONFLICT_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_l1_cache37_SLM_BANK_CONFLICT_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache37_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache37";
    metric_set->symbol_name = "L1Cache37";
    metric_set->hw_config_guid = "2558f9cd-1565-498c-a539-430377a55a93";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache37_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache37__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache37__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache37__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache37__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE8",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE8",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache37__slm_bank_conflict_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache37_SLM_BANK_CONFLICT_COUNT_XECORE8_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_l1_cache38_SLM_BANK_CONFLICT_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache38_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache38";
    metric_set->symbol_name = "L1Cache38";
    metric_set->hw_config_guid = "a4a5c1e1-beeb-42ec-ba01-6af0c5eeee90";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache38_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache38__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache38__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache38__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache38__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE9",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE9",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache38__slm_bank_conflict_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache38_SLM_BANK_CONFLICT_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_l1_cache39_SLM_BANK_CONFLICT_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache39_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache39";
    metric_set->symbol_name = "L1Cache39";
    metric_set->hw_config_guid = "7d80234b-4dae-4def-aa0b-2b1fe3ff0a13";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache39_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache39__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache39__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache39__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache39__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE10",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE10",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache39__slm_bank_conflict_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache39_SLM_BANK_CONFLICT_COUNT_XECORE10_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_l1_cache40_SLM_BANK_CONFLICT_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache40_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache40";
    metric_set->symbol_name = "L1Cache40";
    metric_set->hw_config_guid = "ba5d47a0-a35b-4ee2-9cdd-8272cfc149d9";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache40_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache40__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache40__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache40__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache40__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE11",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE11",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache40__slm_bank_conflict_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache40_SLM_BANK_CONFLICT_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_l1_cache41_SLM_BANK_CONFLICT_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache41_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache41";
    metric_set->symbol_name = "L1Cache41";
    metric_set->hw_config_guid = "692e3adb-d471-44a3-a3ad-0b0fedf05630";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache41_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache41__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache41__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache41__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache41__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE12",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE12",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache41__slm_bank_conflict_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache41_SLM_BANK_CONFLICT_COUNT_XECORE12_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_l1_cache42_SLM_BANK_CONFLICT_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache42_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache42";
    metric_set->symbol_name = "L1Cache42";
    metric_set->hw_config_guid = "c1c40fc7-8db1-401b-8dc9-42c3b51361a4";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache42_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache42__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache42__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache42__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache42__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE13",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE13",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache42__slm_bank_conflict_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache42_SLM_BANK_CONFLICT_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_l1_cache43_SLM_BANK_CONFLICT_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache43_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache43";
    metric_set->symbol_name = "L1Cache43";
    metric_set->hw_config_guid = "e75bf1f9-071f-4c21-8f55-e9ee154638ba";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache43_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache43__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache43__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache43__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache43__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE14",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE14",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache43__slm_bank_conflict_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache43_SLM_BANK_CONFLICT_COUNT_XECORE14_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_l1_cache44_SLM_BANK_CONFLICT_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache44_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache44";
    metric_set->symbol_name = "L1Cache44";
    metric_set->hw_config_guid = "975595a3-2d15-44aa-b32f-0204e42485f4";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache44_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache44__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache44__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache44__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache44__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE15",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE15",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache44__slm_bank_conflict_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache44_SLM_BANK_CONFLICT_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_l1_cache45_SLM_ACCESS_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache45_SLM_ACCESS_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache45_SLM_ACCESS_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache45_SLM_ACCESS_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache45_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache45";
    metric_set->symbol_name = "L1Cache45";
    metric_set->hw_config_guid = "9c1f54c9-3b59-479a-97e9-179a40b4b949";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache45_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache45__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache45__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache45__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache45__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM ACCESS COUNT XECORE0",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE0",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache45__slm_access_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache45_SLM_ACCESS_COUNT_XECORE0_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE1",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE1",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache45__slm_access_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache45_SLM_ACCESS_COUNT_XECORE1_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE2",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE2",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache45__slm_access_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache45_SLM_ACCESS_COUNT_XECORE2_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE3",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE3",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache45__slm_access_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache45_SLM_ACCESS_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache46_SLM_ACCESS_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache46_SLM_ACCESS_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache46_SLM_ACCESS_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache46_SLM_ACCESS_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache46_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache46";
    metric_set->symbol_name = "L1Cache46";
    metric_set->hw_config_guid = "eebc8739-0987-4f55-b70f-6cdee1a4ec02";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache46_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache46__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache46__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache46__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache46__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM ACCESS COUNT XECORE4",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE4",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache46__slm_access_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache46_SLM_ACCESS_COUNT_XECORE4_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE5",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE5",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache46__slm_access_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache46_SLM_ACCESS_COUNT_XECORE5_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE6",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE6",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache46__slm_access_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache46_SLM_ACCESS_COUNT_XECORE6_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE7",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE7",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache46__slm_access_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache46_SLM_ACCESS_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache47_SLM_ACCESS_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache47_SLM_ACCESS_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache47_SLM_ACCESS_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache47_SLM_ACCESS_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache47_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache47";
    metric_set->symbol_name = "L1Cache47";
    metric_set->hw_config_guid = "e01f5549-332a-4e23-b915-828860d438cc";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache47_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache47__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache47__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache47__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache47__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM ACCESS COUNT XECORE10",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE10",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache47__slm_access_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache47_SLM_ACCESS_COUNT_XECORE10_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE11",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE11",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache47__slm_access_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache47_SLM_ACCESS_COUNT_XECORE11_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE8",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE8",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache47__slm_access_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache47_SLM_ACCESS_COUNT_XECORE8_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE9",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE9",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache47__slm_access_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache47_SLM_ACCESS_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache48_SLM_ACCESS_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache48_SLM_ACCESS_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache48_SLM_ACCESS_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache48_SLM_ACCESS_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache48_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache48";
    metric_set->symbol_name = "L1Cache48";
    metric_set->hw_config_guid = "389c0253-dbfb-47b3-878e-3eb1b9b6e74f";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache48_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache48__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache48__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache48__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache48__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM ACCESS COUNT XECORE12",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE12",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache48__slm_access_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache48_SLM_ACCESS_COUNT_XECORE12_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE13",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE13",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache48__slm_access_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache48_SLM_ACCESS_COUNT_XECORE13_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE14",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE14",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache48__slm_access_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache48_SLM_ACCESS_COUNT_XECORE14_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE15",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE15",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache48__slm_access_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache48_SLM_ACCESS_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache49_XVE_SLM_READ_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache49_XVE_SLM_READ_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache49_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache49";
    metric_set->symbol_name = "L1Cache49";
    metric_set->hw_config_guid = "23488fdc-0420-4cee-b15a-000f3fe0c61c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache49_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache49__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache49__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache49__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache49__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE0",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache49__xve_slm_read_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache49_XVE_SLM_READ_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE1",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache49__xve_slm_read_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache49_XVE_SLM_READ_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache50_XVE_SLM_READ_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache50_XVE_SLM_READ_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache50_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache50";
    metric_set->symbol_name = "L1Cache50";
    metric_set->hw_config_guid = "229bdc13-d602-4e78-a325-c082919dc47a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache50_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache50__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache50__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache50__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache50__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE2",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache50__xve_slm_read_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache50_XVE_SLM_READ_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE3",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache50__xve_slm_read_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache50_XVE_SLM_READ_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache51_XVE_SLM_READ_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache51_XVE_SLM_READ_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache51_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache51";
    metric_set->symbol_name = "L1Cache51";
    metric_set->hw_config_guid = "35c25f46-14d7-46fa-927f-35507e61a2fc";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache51_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache51__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache51__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache51__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache51__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE4",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache51__xve_slm_read_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache51_XVE_SLM_READ_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE5",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache51__xve_slm_read_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache51_XVE_SLM_READ_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache52_XVE_SLM_READ_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache52_XVE_SLM_READ_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache52_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache52";
    metric_set->symbol_name = "L1Cache52";
    metric_set->hw_config_guid = "94284c36-9664-4d60-b4d9-15179f266d23";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache52_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache52__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache52__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache52__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache52__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE6",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache52__xve_slm_read_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache52_XVE_SLM_READ_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE7",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache52__xve_slm_read_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache52_XVE_SLM_READ_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache53_XVE_SLM_READ_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache53_XVE_SLM_READ_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache53_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache53";
    metric_set->symbol_name = "L1Cache53";
    metric_set->hw_config_guid = "a2b93539-7c7e-4ea4-85df-2fa675381a1b";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache53_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache53__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache53__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache53__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache53__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE8",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE8",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache53__xve_slm_read_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache53_XVE_SLM_READ_MESSAGE_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE9",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE9",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache53__xve_slm_read_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache53_XVE_SLM_READ_MESSAGE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache54_XVE_SLM_READ_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache54_XVE_SLM_READ_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache54_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache54";
    metric_set->symbol_name = "L1Cache54";
    metric_set->hw_config_guid = "8efc5126-1bb6-47cd-bd3c-b1bfa6a99dc1";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache54_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache54__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache54__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache54__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache54__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE10",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE10",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache54__xve_slm_read_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache54_XVE_SLM_READ_MESSAGE_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE11",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE11",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache54__xve_slm_read_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache54_XVE_SLM_READ_MESSAGE_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache55_XVE_SLM_READ_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache55_XVE_SLM_READ_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache55_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache55";
    metric_set->symbol_name = "L1Cache55";
    metric_set->hw_config_guid = "4a628907-5db2-437c-b04e-8c14dede3794";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache55_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache55__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache55__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache55__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache55__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE12",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE12",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache55__xve_slm_read_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache55_XVE_SLM_READ_MESSAGE_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE13",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE13",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache55__xve_slm_read_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache55_XVE_SLM_READ_MESSAGE_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache56_XVE_SLM_READ_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache56_XVE_SLM_READ_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache56_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache56";
    metric_set->symbol_name = "L1Cache56";
    metric_set->hw_config_guid = "e017d352-78fe-4f3e-bda9-814fb14f495e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache56_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache56__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache56__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache56__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache56__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE14",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE14",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache56__xve_slm_read_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache56_XVE_SLM_READ_MESSAGE_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE15",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE15",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache56__xve_slm_read_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache56_XVE_SLM_READ_MESSAGE_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache57_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache57_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache57_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache57";
    metric_set->symbol_name = "L1Cache57";
    metric_set->hw_config_guid = "c89b207d-e5c1-480a-8b15-5403d0e45fb9";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache57_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache57__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache57__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache57__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache57__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE0",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache57__xve_slm_write_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache57_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE1",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache57__xve_slm_write_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache57_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache58_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache58_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache58_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache58";
    metric_set->symbol_name = "L1Cache58";
    metric_set->hw_config_guid = "dd46fc9a-6a2c-44c7-94f3-069b58c95aca";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache58_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache58__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache58__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache58__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache58__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE2",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache58__xve_slm_write_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache58_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE3",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache58__xve_slm_write_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache58_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache59_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache59_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache59_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache59";
    metric_set->symbol_name = "L1Cache59";
    metric_set->hw_config_guid = "4669435c-6f14-4557-b983-3f5186807fd6";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache59_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache59__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache59__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache59__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache59__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE4",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache59__xve_slm_write_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache59_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE5",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache59__xve_slm_write_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache59_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache60_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache60_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache60_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache60";
    metric_set->symbol_name = "L1Cache60";
    metric_set->hw_config_guid = "6f37e5b7-c8fd-4f28-a95d-919848fe4a95";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache60_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache60__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache60__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache60__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache60__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE6",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache60__xve_slm_write_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache60_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE7",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache60__xve_slm_write_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache60_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache61_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache61_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache61_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache61";
    metric_set->symbol_name = "L1Cache61";
    metric_set->hw_config_guid = "0cd1c331-f998-467e-ae36-ea334c3ba2a5";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache61_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache61__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache61__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache61__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache61__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE8",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE8",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache61__xve_slm_write_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache61_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE9",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE9",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache61__xve_slm_write_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache61_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache62_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache62_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache62_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache62";
    metric_set->symbol_name = "L1Cache62";
    metric_set->hw_config_guid = "09153d17-1912-4ce4-b41a-709df4aba848";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache62_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache62__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache62__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache62__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache62__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE10",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE10",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache62__xve_slm_write_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache62_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE11",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE11",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache62__xve_slm_write_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache62_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache63_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache63_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache63_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache63";
    metric_set->symbol_name = "L1Cache63";
    metric_set->hw_config_guid = "ea0e19bb-8a13-4e51-92ca-1cb3db78fb10";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache63_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache63__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache63__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache63__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache63__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE12",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE12",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache63__xve_slm_write_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache63_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE13",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE13",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache63__xve_slm_write_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache63_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache64_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache64_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache64_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache64";
    metric_set->symbol_name = "L1Cache64";
    metric_set->hw_config_guid = "d7eb30f5-28aa-455b-b8a5-221db2ccfe62";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache64_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache64__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache64__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache64__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache64__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE14",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE14",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache64__xve_slm_write_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache64_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE15",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE15",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache64__xve_slm_write_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache64_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache65_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache65_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache65_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache65";
    metric_set->symbol_name = "L1Cache65";
    metric_set->hw_config_guid = "ae51ef65-a808-4248-8c26-8fcda92bb018";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache65_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache65__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache65__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache65__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache65__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE0",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache65__xve_slm_atomic_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache65_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE0",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache65__xve_slm_fence_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache65_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache66_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache66_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache66_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache66";
    metric_set->symbol_name = "L1Cache66";
    metric_set->hw_config_guid = "e6e2b49c-615f-4af1-a7b1-349f6b906c90";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache66_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache66__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache66__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache66__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache66__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE1",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache66__xve_slm_atomic_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache66_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE1",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache66__xve_slm_fence_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache66_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache67_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache67_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache67_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache67";
    metric_set->symbol_name = "L1Cache67";
    metric_set->hw_config_guid = "691098de-d8d8-40f3-906f-b20df78f5b52";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache67_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache67__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache67__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache67__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache67__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE2",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache67__xve_slm_atomic_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache67_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE2",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache67__xve_slm_fence_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache67_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache68_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache68_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache68_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache68";
    metric_set->symbol_name = "L1Cache68";
    metric_set->hw_config_guid = "bdcc17c1-0c82-4277-8c4a-6c878af1f374";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache68_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache68__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache68__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache68__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache68__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE3",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache68__xve_slm_atomic_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache68_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE3_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE3",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache68__xve_slm_fence_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache68_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache69_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache69_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache69_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache69";
    metric_set->symbol_name = "L1Cache69";
    metric_set->hw_config_guid = "e2417f86-ea22-4512-b4b6-1918c6721e47";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache69_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache69__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache69__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache69__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache69__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE4",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache69__xve_slm_atomic_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache69_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE4",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache69__xve_slm_fence_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache69_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache70_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache70_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache70_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache70";
    metric_set->symbol_name = "L1Cache70";
    metric_set->hw_config_guid = "0b7a01c5-5622-43cd-90c1-963d8ebc4d30";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache70_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache70__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache70__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache70__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache70__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE5",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache70__xve_slm_atomic_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache70_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE5",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache70__xve_slm_fence_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache70_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache71_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache71_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache71_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache71";
    metric_set->symbol_name = "L1Cache71";
    metric_set->hw_config_guid = "e0da306c-65eb-4032-b327-f95f4eba3020";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache71_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache71__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache71__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache71__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache71__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE6",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache71__xve_slm_atomic_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache71_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE6",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache71__xve_slm_fence_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache71_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache72_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache72_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache72_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache72";
    metric_set->symbol_name = "L1Cache72";
    metric_set->hw_config_guid = "10f602b1-6401-49df-b617-8fb07c188fa2";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache72_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache72__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache72__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache72__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache72__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE7",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache72__xve_slm_atomic_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache72_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE7_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE7",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache72__xve_slm_fence_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache72_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache73_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache73_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache73_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache73";
    metric_set->symbol_name = "L1Cache73";
    metric_set->hw_config_guid = "8bcaab96-b9ff-4445-9b12-77c6645d4889";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache73_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache73__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache73__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache73__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache73__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE8",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE8",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache73__xve_slm_atomic_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache73_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE8",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE8",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache73__xve_slm_fence_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache73_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE8_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache74_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache74_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache74_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache74";
    metric_set->symbol_name = "L1Cache74";
    metric_set->hw_config_guid = "fb2f0a27-1305-4d18-9940-d644f2fd2607";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache74_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache74__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache74__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache74__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache74__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE9",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE9",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache74__xve_slm_atomic_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache74_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE9_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE9",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE9",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache74__xve_slm_fence_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache74_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache75_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache75_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache75_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache75";
    metric_set->symbol_name = "L1Cache75";
    metric_set->hw_config_guid = "e79fe17b-cecf-4808-98f8-dbf002286e99";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache75_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache75__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache75__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache75__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache75__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE10",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE10",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache75__xve_slm_atomic_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache75_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE10",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE10",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache75__xve_slm_fence_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache75_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE10_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache76_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache76_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache76_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache76";
    metric_set->symbol_name = "L1Cache76";
    metric_set->hw_config_guid = "b25a8d2b-6410-4f91-af8d-364c2f31263a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache76_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache76__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache76__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache76__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache76__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE11",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE11",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache76__xve_slm_atomic_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache76_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE11_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE11",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE11",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache76__xve_slm_fence_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache76_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache77_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache77_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache77_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache77";
    metric_set->symbol_name = "L1Cache77";
    metric_set->hw_config_guid = "45ec41ff-4a28-4282-973b-8fcbe65cf00d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache77_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache77__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache77__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache77__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache77__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE12",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE12",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache77__xve_slm_atomic_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache77_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE12",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE12",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache77__xve_slm_fence_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache77_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE12_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache78_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache78_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache78_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache78";
    metric_set->symbol_name = "L1Cache78";
    metric_set->hw_config_guid = "f2ea74eb-3520-4e62-a9e9-6907afd1a5e6";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache78_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache78__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache78__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache78__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache78__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE13",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE13",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache78__xve_slm_atomic_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache78_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE13_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE13",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE13",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache78__xve_slm_fence_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache78_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache79_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache79_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache79_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache79";
    metric_set->symbol_name = "L1Cache79";
    metric_set->hw_config_guid = "90e0b182-84d1-4bc7-aa0b-448bb0a7a850";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache79_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache79__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache79__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache79__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache79__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE14",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE14",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache79__xve_slm_atomic_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache79_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE14",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE14",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache79__xve_slm_fence_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache79_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE14_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache80_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache80_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache80_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache80";
    metric_set->symbol_name = "L1Cache80";
    metric_set->hw_config_guid = "8f0b735d-f269-4545-8a11-a31b3ebed779";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache80_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache80__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache80__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache80__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache80__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE15",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE15",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache80__xve_slm_atomic_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache80_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE15_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE15",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE15",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache80__xve_slm_fence_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache80_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache81_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache81_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache81_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache81_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache81_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache81";
    metric_set->symbol_name = "L1Cache81";
    metric_set->hw_config_guid = "6e136a5b-e7fa-4349-be46-e83455caec62";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache81_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache81__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache81__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache81__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache81__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE0",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE0",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache81__xve_load_store_cache_register_request_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache81_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE1",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE1",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache81__xve_load_store_cache_register_request_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache81_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE2",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE2",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache81__xve_load_store_cache_register_request_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache81_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE3",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE3",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache81__xve_load_store_cache_register_request_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache81_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache82_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache82_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache82_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache82_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache82_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache82";
    metric_set->symbol_name = "L1Cache82";
    metric_set->hw_config_guid = "c59e0c0d-d038-4b0a-b643-bccfd3963f4b";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache82_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache82__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache82__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache82__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache82__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE4",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE4",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache82__xve_load_store_cache_register_request_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache82_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE5",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE5",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache82__xve_load_store_cache_register_request_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache82_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE6",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE6",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache82__xve_load_store_cache_register_request_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache82_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE7",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE7",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache82__xve_load_store_cache_register_request_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache82_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache83_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache83_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache83_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache83_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache83_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache83";
    metric_set->symbol_name = "L1Cache83";
    metric_set->hw_config_guid = "5180e659-772f-4531-a2cb-f38a86841e22";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache83_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache83__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache83__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache83__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache83__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE10",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE10",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache83__xve_load_store_cache_register_request_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache83_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE11",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE11",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache83__xve_load_store_cache_register_request_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache83_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE11_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE8",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE8",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache83__xve_load_store_cache_register_request_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache83_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE9",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE9",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache83__xve_load_store_cache_register_request_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache83_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache84_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache84_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache84_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache84_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache84_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache84";
    metric_set->symbol_name = "L1Cache84";
    metric_set->hw_config_guid = "53e81609-e3d2-4679-b348-6f6473dd0fe2";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache84_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache84__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache84__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache84__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache84__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE12",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE12",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache84__xve_load_store_cache_register_request_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache84_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE13",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE13",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache84__xve_load_store_cache_register_request_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache84_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE13_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE14",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE14",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache84__xve_load_store_cache_register_request_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache84_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE15",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE15",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache84__xve_load_store_cache_register_request_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache84_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache85_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache85_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache85_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache85_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache85_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache85";
    metric_set->symbol_name = "L1Cache85";
    metric_set->hw_config_guid = "16e8cd96-5a5d-4528-999b-90629facef72";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache85_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache85__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache85__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache85__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache85__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE0",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE0",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache85__xve_load_store_cache_register_response_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache85_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE1",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE1",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache85__xve_load_store_cache_register_response_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache85_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE2",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE2",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache85__xve_load_store_cache_register_response_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache85_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE3",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE3",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache85__xve_load_store_cache_register_response_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache85_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache86_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache86_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache86_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache86_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache86_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache86";
    metric_set->symbol_name = "L1Cache86";
    metric_set->hw_config_guid = "d4e55aa0-754b-4fab-9134-ba7168529642";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache86_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache86__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache86__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache86__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache86__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE4",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE4",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache86__xve_load_store_cache_register_response_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache86_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE5",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE5",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache86__xve_load_store_cache_register_response_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache86_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE6",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE6",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache86__xve_load_store_cache_register_response_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache86_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE7",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE7",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache86__xve_load_store_cache_register_response_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache86_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache87_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache87_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache87_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache87_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache87_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache87";
    metric_set->symbol_name = "L1Cache87";
    metric_set->hw_config_guid = "e80e1404-d74b-4e84-b8b2-317fe06a2900";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache87_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache87__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache87__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache87__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache87__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE10",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE10",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache87__xve_load_store_cache_register_response_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache87_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE11",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE11",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache87__xve_load_store_cache_register_response_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache87_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE11_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE8",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE8",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache87__xve_load_store_cache_register_response_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache87_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE9",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE9",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache87__xve_load_store_cache_register_response_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache87_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache88_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache88_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache88_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache88_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache88_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache88";
    metric_set->symbol_name = "L1Cache88";
    metric_set->hw_config_guid = "b096a99f-7544-4891-9336-6a1a8f341b31";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache88_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache88__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache88__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache88__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache88__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE12",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE12",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache88__xve_load_store_cache_register_response_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache88_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE13",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE13",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache88__xve_load_store_cache_register_response_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache88_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE13_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE14",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE14",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache88__xve_load_store_cache_register_response_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache88_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE15",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE15",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache88__xve_load_store_cache_register_response_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache88_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache89_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache89_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache89_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache89";
    metric_set->symbol_name = "L1Cache89";
    metric_set->hw_config_guid = "8164944d-16b7-4415-9c9d-c9155b54d313";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache89_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache89__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache89__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache89__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache89__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache89__xve_load_store_cache_read_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache89_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache89__xve_load_store_cache_read_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache89_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache90_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache90_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache90_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache90";
    metric_set->symbol_name = "L1Cache90";
    metric_set->hw_config_guid = "f04cb35e-ad18-487c-a3a7-4c3df903df4e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache90_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache90__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache90__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache90__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache90__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache90__xve_load_store_cache_read_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache90_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE3",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache90__xve_load_store_cache_read_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache90_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache91_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache91_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache91_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache91";
    metric_set->symbol_name = "L1Cache91";
    metric_set->hw_config_guid = "7476a997-fd23-4e09-9e41-be5ad6998370";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache91_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache91__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache91__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache91__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache91__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache91__xve_load_store_cache_read_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache91_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE5",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache91__xve_load_store_cache_read_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache91_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache92_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache92_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache92_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache92";
    metric_set->symbol_name = "L1Cache92";
    metric_set->hw_config_guid = "c39f76fb-108f-4470-adb7-92f0830b4b85";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache92_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache92__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache92__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache92__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache92__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache92__xve_load_store_cache_read_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache92_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache92__xve_load_store_cache_read_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache92_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache93_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache93_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache93_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache93";
    metric_set->symbol_name = "L1Cache93";
    metric_set->hw_config_guid = "3a32053e-1919-4630-a163-dcacf9c6d003";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache93_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache93__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache93__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache93__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache93__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE8",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE8",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache93__xve_load_store_cache_read_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache93_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE9",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE9",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache93__xve_load_store_cache_read_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache93_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache94_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache94_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache94_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache94";
    metric_set->symbol_name = "L1Cache94";
    metric_set->hw_config_guid = "340e5f66-a0d2-4365-9a67-76f5fea0b623";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache94_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache94__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache94__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache94__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache94__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE10",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE10",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache94__xve_load_store_cache_read_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache94_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE11",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE11",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache94__xve_load_store_cache_read_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache94_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache95_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache95_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache95_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache95";
    metric_set->symbol_name = "L1Cache95";
    metric_set->hw_config_guid = "14d53071-a58c-4e71-b4e4-160815efdc7c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache95_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache95__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache95__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache95__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache95__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE12",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE12",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache95__xve_load_store_cache_read_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache95_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE13",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE13",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache95__xve_load_store_cache_read_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache95_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache96_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache96_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache96_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache96";
    metric_set->symbol_name = "L1Cache96";
    metric_set->hw_config_guid = "b390699e-0883-423a-a7c3-064e0520ebed";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache96_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache96__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache96__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache96__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache96__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE14",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE14",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache96__xve_load_store_cache_read_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache96_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE15",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE15",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache96__xve_load_store_cache_read_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache96_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache97_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache97_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache97_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache97";
    metric_set->symbol_name = "L1Cache97";
    metric_set->hw_config_guid = "74f12f6d-05be-4a80-9870-2a2c487f7bd9";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache97_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache97__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache97__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache97__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache97__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE0",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache97__xve_load_store_cache_write_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache97_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE1",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache97__xve_load_store_cache_write_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache97_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache98_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache98_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache98_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache98";
    metric_set->symbol_name = "L1Cache98";
    metric_set->hw_config_guid = "f587f7f5-b5fd-4183-a59c-3ca769fe8148";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache98_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache98__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache98__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache98__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache98__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE2",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache98__xve_load_store_cache_write_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache98_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE3",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache98__xve_load_store_cache_write_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache98_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache99_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache99_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache99_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache99";
    metric_set->symbol_name = "L1Cache99";
    metric_set->hw_config_guid = "08848093-c9f7-4554-a447-278c4da9f9ea";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache99_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache99__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache99__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache99__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache99__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE4",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache99__xve_load_store_cache_write_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache99_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE5",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache99__xve_load_store_cache_write_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache99_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache100_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache100_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache100_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache100";
    metric_set->symbol_name = "L1Cache100";
    metric_set->hw_config_guid = "8fd337d7-938c-4a64-b5b9-37df6074e4c0";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache100_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache100__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache100__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache100__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache100__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE6",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache100__xve_load_store_cache_write_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache100_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE7",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache100__xve_load_store_cache_write_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache100_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache101_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache101_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache101_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache101";
    metric_set->symbol_name = "L1Cache101";
    metric_set->hw_config_guid = "e47ea265-e42a-4a04-81b2-30814815b3aa";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache101_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache101__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache101__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache101__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache101__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE8",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE8",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache101__xve_load_store_cache_write_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache101_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE9",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE9",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache101__xve_load_store_cache_write_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache101_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache102_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache102_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache102_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache102";
    metric_set->symbol_name = "L1Cache102";
    metric_set->hw_config_guid = "ff5717d6-fae7-4288-885c-3850588e4b2e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache102_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache102__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache102__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache102__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache102__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE10",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE10",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache102__xve_load_store_cache_write_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache102_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE11",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE11",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache102__xve_load_store_cache_write_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache102_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache103_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache103_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache103_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache103";
    metric_set->symbol_name = "L1Cache103";
    metric_set->hw_config_guid = "9fad96f4-5977-4cf8-a2e4-bd72b277075f";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache103_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache103__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache103__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache103__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache103__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE12",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE12",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache103__xve_load_store_cache_write_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache103_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE13",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE13",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache103__xve_load_store_cache_write_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache103_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache104_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache104_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache104_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache104";
    metric_set->symbol_name = "L1Cache104";
    metric_set->hw_config_guid = "997c44e5-85b3-47f7-9845-6c42c554caae";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache104_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache104__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache104__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache104__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache104__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE14",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE14",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache104__xve_load_store_cache_write_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache104_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE15",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE15",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache104__xve_load_store_cache_write_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache104_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache105_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache105_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache105_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache105";
    metric_set->symbol_name = "L1Cache105";
    metric_set->hw_config_guid = "7c51d383-b682-4f1d-831d-b689c8be3fdd";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache105_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache105__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache105__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache105__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache105__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE0",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache105__xve_load_store_cache_atomic_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache105_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE0",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache105__xve_load_store_cache_fence_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache105_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache106_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache106_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache106_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache106";
    metric_set->symbol_name = "L1Cache106";
    metric_set->hw_config_guid = "04638c41-779d-4d79-a3bc-69b642342b99";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache106_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache106__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache106__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache106__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache106__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE1",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache106__xve_load_store_cache_atomic_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache106_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE1",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache106__xve_load_store_cache_fence_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache106_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache107_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache107_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache107_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache107";
    metric_set->symbol_name = "L1Cache107";
    metric_set->hw_config_guid = "86bb1e10-f542-4f9c-b0f3-8a1fc1caf5aa";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache107_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache107__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache107__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache107__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache107__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE2",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache107__xve_load_store_cache_atomic_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache107_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE2",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache107__xve_load_store_cache_fence_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache107_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache108_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache108_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache108_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache108";
    metric_set->symbol_name = "L1Cache108";
    metric_set->hw_config_guid = "dab065f1-c8a2-4e03-823e-ad9591fdcf29";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache108_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache108__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache108__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache108__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache108__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE3",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache108__xve_load_store_cache_atomic_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache108_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE3_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE3",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache108__xve_load_store_cache_fence_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache108_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache109_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache109_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache109_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache109";
    metric_set->symbol_name = "L1Cache109";
    metric_set->hw_config_guid = "cefea11c-d38d-4ddb-8ce1-f24d75799a7e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache109_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache109__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache109__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache109__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache109__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE4",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache109__xve_load_store_cache_atomic_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache109_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE4",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache109__xve_load_store_cache_fence_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache109_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache110_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache110_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache110_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache110";
    metric_set->symbol_name = "L1Cache110";
    metric_set->hw_config_guid = "1178f323-ea3e-41c3-905c-2a8442f3b4f6";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache110_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache110__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache110__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache110__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache110__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE5",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache110__xve_load_store_cache_atomic_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache110_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE5",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache110__xve_load_store_cache_fence_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache110_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache111_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache111_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache111_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache111";
    metric_set->symbol_name = "L1Cache111";
    metric_set->hw_config_guid = "26bca320-d4e2-460a-9896-a5fb2a279ccf";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache111_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache111__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache111__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache111__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache111__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE6",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache111__xve_load_store_cache_atomic_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache111_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE6",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache111__xve_load_store_cache_fence_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache111_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache112_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache112_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache112_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache112";
    metric_set->symbol_name = "L1Cache112";
    metric_set->hw_config_guid = "3f8fbb78-69b9-4e93-afcb-2a0f380c2013";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache112_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache112__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache112__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache112__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache112__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE7",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache112__xve_load_store_cache_atomic_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache112_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE7_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE7",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache112__xve_load_store_cache_fence_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache112_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache113_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache113_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache113_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache113";
    metric_set->symbol_name = "L1Cache113";
    metric_set->hw_config_guid = "da9b2768-977e-4de8-bbd1-036260d79f93";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache113_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache113__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache113__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache113__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache113__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE8",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE8",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache113__xve_load_store_cache_atomic_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache113_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE8",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE8",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache113__xve_load_store_cache_fence_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache113_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE8_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache114_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache114_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache114_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache114";
    metric_set->symbol_name = "L1Cache114";
    metric_set->hw_config_guid = "0eb1375c-25b4-47ff-b124-ba4eba95871a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache114_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache114__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache114__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache114__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache114__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE9",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE9",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache114__xve_load_store_cache_atomic_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache114_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE9_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE9",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE9",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache114__xve_load_store_cache_fence_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache114_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache115_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache115_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache115_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache115";
    metric_set->symbol_name = "L1Cache115";
    metric_set->hw_config_guid = "58be8181-92a3-4cec-ad46-30ea575830ad";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache115_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache115__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache115__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache115__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache115__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE10",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE10",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache115__xve_load_store_cache_atomic_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache115_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE10",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE10",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache115__xve_load_store_cache_fence_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache115_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE10_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache116_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache116_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache116_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache116";
    metric_set->symbol_name = "L1Cache116";
    metric_set->hw_config_guid = "1a3918a7-1fc2-430f-82f2-9114e69586fb";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache116_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache116__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache116__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache116__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache116__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE11",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE11",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache116__xve_load_store_cache_atomic_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache116_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE11_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE11",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE11",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache116__xve_load_store_cache_fence_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache116_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache117_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache117_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache117_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache117";
    metric_set->symbol_name = "L1Cache117";
    metric_set->hw_config_guid = "5206a8c9-3c75-485b-8e78-e3057cda1bb2";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache117_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache117__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache117__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache117__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache117__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE12",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE12",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache117__xve_load_store_cache_atomic_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache117_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE12",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE12",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache117__xve_load_store_cache_fence_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache117_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE12_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache118_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache118_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache118_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache118";
    metric_set->symbol_name = "L1Cache118";
    metric_set->hw_config_guid = "fe39d1bc-b405-4a4d-99a5-3079c0cb6a71";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache118_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache118__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache118__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache118__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache118__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE13",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE13",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache118__xve_load_store_cache_atomic_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache118_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE13_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE13",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE13",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache118__xve_load_store_cache_fence_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache118_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache119_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache119_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache119_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache119";
    metric_set->symbol_name = "L1Cache119";
    metric_set->hw_config_guid = "7580647f-8c47-4796-a7f6-8f6011aaabe8";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache119_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache119__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache119__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache119__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache119__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE14",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE14",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache119__xve_load_store_cache_atomic_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache119_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE14",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE14",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache119__xve_load_store_cache_fence_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache119_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE14_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache120_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache120_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache120_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache120";
    metric_set->symbol_name = "L1Cache120";
    metric_set->hw_config_guid = "b7ae9004-efa6-4851-951c-e901b3228664";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache120_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache120__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache120__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache120__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache120__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE15",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE15",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache120__xve_load_store_cache_atomic_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache120_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE15_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE15",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE15",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache120__xve_load_store_cache_fence_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache120_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache121_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache121_SLM_BYTE_READ_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache121_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache121";
    metric_set->symbol_name = "L1Cache121";
    metric_set->hw_config_guid = "77902327-49d2-4174-ba8c-94a796e54c72";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache121_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache121__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache121__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache121__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache121__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK0 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE0",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache121__load_store_cache_byte_read_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache121_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE0_availability,
            },

            {
                .name = "SLM BYTE READ BANK0 XECORE0",
                .symbol_name = "SLM_BYTE_READ_BANK0_XECORE0",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache121__slm_byte_read_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache121_SLM_BYTE_READ_BANK0_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache122_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache122_SLM_BYTE_READ_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache122_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache122";
    metric_set->symbol_name = "L1Cache122";
    metric_set->hw_config_guid = "f4c597eb-8ac7-4138-8775-759d14e2cd40";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache122_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache122__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache122__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache122__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache122__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK0 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE1",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache122__load_store_cache_byte_read_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache122_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE1_availability,
            },

            {
                .name = "SLM BYTE READ BANK0 XECORE1",
                .symbol_name = "SLM_BYTE_READ_BANK0_XECORE1",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache122__slm_byte_read_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache122_SLM_BYTE_READ_BANK0_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache123_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache123_SLM_BYTE_READ_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache123_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache123";
    metric_set->symbol_name = "L1Cache123";
    metric_set->hw_config_guid = "e9ee5eb7-90aa-4798-a586-79764c58a6ac";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache123_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache123__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache123__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache123__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache123__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK0 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE2",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache123__load_store_cache_byte_read_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache123_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE2_availability,
            },

            {
                .name = "SLM BYTE READ BANK0 XECORE2",
                .symbol_name = "SLM_BYTE_READ_BANK0_XECORE2",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache123__slm_byte_read_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache123_SLM_BYTE_READ_BANK0_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache124_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache124_SLM_BYTE_READ_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache124_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache124";
    metric_set->symbol_name = "L1Cache124";
    metric_set->hw_config_guid = "a5438972-875a-4301-9b15-f4d16d9d106e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache124_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache124__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache124__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache124__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache124__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK0 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE3",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache124__load_store_cache_byte_read_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache124_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE3_availability,
            },

            {
                .name = "SLM BYTE READ BANK0 XECORE3",
                .symbol_name = "SLM_BYTE_READ_BANK0_XECORE3",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache124__slm_byte_read_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache124_SLM_BYTE_READ_BANK0_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache125_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache125_SLM_BYTE_READ_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache125_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache125";
    metric_set->symbol_name = "L1Cache125";
    metric_set->hw_config_guid = "9d7b58e1-a5fa-47fb-a446-1e03556fa59a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache125_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache125__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache125__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache125__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache125__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK1 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE0",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache125__load_store_cache_byte_read_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache125_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE0_availability,
            },

            {
                .name = "SLM BYTE READ BANK1 XECORE0",
                .symbol_name = "SLM_BYTE_READ_BANK1_XECORE0",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache125__slm_byte_read_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache125_SLM_BYTE_READ_BANK1_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache126_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache126_SLM_BYTE_READ_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache126_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache126";
    metric_set->symbol_name = "L1Cache126";
    metric_set->hw_config_guid = "7ce674af-6177-4d79-8bd4-dff2ef2fab24";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache126_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache126__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache126__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache126__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache126__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK1 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE1",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache126__load_store_cache_byte_read_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache126_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE1_availability,
            },

            {
                .name = "SLM BYTE READ BANK1 XECORE1",
                .symbol_name = "SLM_BYTE_READ_BANK1_XECORE1",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache126__slm_byte_read_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache126_SLM_BYTE_READ_BANK1_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache127_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache127_SLM_BYTE_READ_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache127_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache127";
    metric_set->symbol_name = "L1Cache127";
    metric_set->hw_config_guid = "6dedd9cf-b928-4862-80b5-32a0a17cc238";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache127_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache127__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache127__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache127__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache127__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK1 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE2",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache127__load_store_cache_byte_read_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache127_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE2_availability,
            },

            {
                .name = "SLM BYTE READ BANK1 XECORE2",
                .symbol_name = "SLM_BYTE_READ_BANK1_XECORE2",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache127__slm_byte_read_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache127_SLM_BYTE_READ_BANK1_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache128_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache128_SLM_BYTE_READ_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache128_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache128";
    metric_set->symbol_name = "L1Cache128";
    metric_set->hw_config_guid = "f9352d6f-8b0f-4df0-9e79-1bd75ed6c2b3";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache128_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache128__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache128__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache128__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache128__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK1 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE3",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache128__load_store_cache_byte_read_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache128_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE3_availability,
            },

            {
                .name = "SLM BYTE READ BANK1 XECORE3",
                .symbol_name = "SLM_BYTE_READ_BANK1_XECORE3",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache128__slm_byte_read_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache128_SLM_BYTE_READ_BANK1_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache129_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache129_SLM_BYTE_READ_BANK2_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache129_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache129";
    metric_set->symbol_name = "L1Cache129";
    metric_set->hw_config_guid = "6c5a3c61-b4cb-48d7-970f-13740c6fd02e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache129_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache129__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache129__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache129__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache129__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK2 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE0",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache129__load_store_cache_byte_read_bank2_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache129_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE0_availability,
            },

            {
                .name = "SLM BYTE READ BANK2 XECORE0",
                .symbol_name = "SLM_BYTE_READ_BANK2_XECORE0",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache129__slm_byte_read_bank2_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache129_SLM_BYTE_READ_BANK2_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache130_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache130_SLM_BYTE_READ_BANK2_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache130_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache130";
    metric_set->symbol_name = "L1Cache130";
    metric_set->hw_config_guid = "a0ee28df-2030-4045-b858-d7153e151801";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache130_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache130__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache130__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache130__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache130__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK2 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE1",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache130__load_store_cache_byte_read_bank2_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache130_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE1_availability,
            },

            {
                .name = "SLM BYTE READ BANK2 XECORE1",
                .symbol_name = "SLM_BYTE_READ_BANK2_XECORE1",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache130__slm_byte_read_bank2_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache130_SLM_BYTE_READ_BANK2_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache131_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache131_SLM_BYTE_READ_BANK2_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache131_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache131";
    metric_set->symbol_name = "L1Cache131";
    metric_set->hw_config_guid = "6a5e1ad7-35fe-4877-a057-c029fdcbd1eb";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache131_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache131__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache131__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache131__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache131__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK2 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE2",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache131__load_store_cache_byte_read_bank2_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache131_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE2_availability,
            },

            {
                .name = "SLM BYTE READ BANK2 XECORE2",
                .symbol_name = "SLM_BYTE_READ_BANK2_XECORE2",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache131__slm_byte_read_bank2_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache131_SLM_BYTE_READ_BANK2_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache132_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache132_SLM_BYTE_READ_BANK2_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache132_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache132";
    metric_set->symbol_name = "L1Cache132";
    metric_set->hw_config_guid = "8c4700c6-ea20-4b8e-a74a-f42f46f9bac4";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache132_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache132__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache132__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache132__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache132__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK2 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE3",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache132__load_store_cache_byte_read_bank2_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache132_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE3_availability,
            },

            {
                .name = "SLM BYTE READ BANK2 XECORE3",
                .symbol_name = "SLM_BYTE_READ_BANK2_XECORE3",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache132__slm_byte_read_bank2_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache132_SLM_BYTE_READ_BANK2_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache133_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache133_SLM_BYTE_READ_BANK3_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache133_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache133";
    metric_set->symbol_name = "L1Cache133";
    metric_set->hw_config_guid = "e1fd9e53-181f-4a61-95a1-3612f36fdeef";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache133_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache133__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache133__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache133__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache133__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK3 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE0",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache133__load_store_cache_byte_read_bank3_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache133_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE0_availability,
            },

            {
                .name = "SLM BYTE READ BANK3 XECORE0",
                .symbol_name = "SLM_BYTE_READ_BANK3_XECORE0",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache133__slm_byte_read_bank3_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache133_SLM_BYTE_READ_BANK3_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache134_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache134_SLM_BYTE_READ_BANK3_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache134_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache134";
    metric_set->symbol_name = "L1Cache134";
    metric_set->hw_config_guid = "0f1d1caf-29f5-4ae3-8b3b-8a645752df97";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache134_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache134__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache134__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache134__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache134__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK3 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE1",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache134__load_store_cache_byte_read_bank3_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache134_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE1_availability,
            },

            {
                .name = "SLM BYTE READ BANK3 XECORE1",
                .symbol_name = "SLM_BYTE_READ_BANK3_XECORE1",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache134__slm_byte_read_bank3_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache134_SLM_BYTE_READ_BANK3_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache135_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache135_SLM_BYTE_READ_BANK3_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache135_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache135";
    metric_set->symbol_name = "L1Cache135";
    metric_set->hw_config_guid = "6eed11fb-4013-479b-94d3-9c4e084e82f1";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache135_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache135__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache135__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache135__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache135__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK3 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE2",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache135__load_store_cache_byte_read_bank3_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache135_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE2_availability,
            },

            {
                .name = "SLM BYTE READ BANK3 XECORE2",
                .symbol_name = "SLM_BYTE_READ_BANK3_XECORE2",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache135__slm_byte_read_bank3_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache135_SLM_BYTE_READ_BANK3_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache136_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache136_SLM_BYTE_READ_BANK3_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache136_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache136";
    metric_set->symbol_name = "L1Cache136";
    metric_set->hw_config_guid = "d08bf17e-d459-43d6-83fe-ba8ee4829cdc";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache136_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache136__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache136__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache136__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache136__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK3 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE3",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache136__load_store_cache_byte_read_bank3_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache136_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE3_availability,
            },

            {
                .name = "SLM BYTE READ BANK3 XECORE3",
                .symbol_name = "SLM_BYTE_READ_BANK3_XECORE3",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache136__slm_byte_read_bank3_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache136_SLM_BYTE_READ_BANK3_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache137_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache137_SLM_BYTE_WRITE_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache137_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache137";
    metric_set->symbol_name = "L1Cache137";
    metric_set->hw_config_guid = "b3d01145-903d-49f7-9ed7-45ed893af630";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache137_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache137__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache137__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache137__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache137__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK0 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE0",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache137__load_store_cache_byte_write_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache137_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE0_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK0 XECORE0",
                .symbol_name = "SLM_BYTE_WRITE_BANK0_XECORE0",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache137__slm_byte_write_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache137_SLM_BYTE_WRITE_BANK0_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache138_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache138_SLM_BYTE_WRITE_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache138_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache138";
    metric_set->symbol_name = "L1Cache138";
    metric_set->hw_config_guid = "5abc1aeb-9795-4d41-8872-7d9c6bb83f46";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache138_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache138__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache138__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache138__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache138__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK0 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE1",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache138__load_store_cache_byte_write_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache138_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE1_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK0 XECORE1",
                .symbol_name = "SLM_BYTE_WRITE_BANK0_XECORE1",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache138__slm_byte_write_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache138_SLM_BYTE_WRITE_BANK0_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache139_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache139_SLM_BYTE_WRITE_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache139_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache139";
    metric_set->symbol_name = "L1Cache139";
    metric_set->hw_config_guid = "231f49f8-1312-4cf8-86a5-ecdeb9070b44";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache139_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache139__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache139__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache139__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache139__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK0 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE2",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache139__load_store_cache_byte_write_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache139_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE2_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK0 XECORE2",
                .symbol_name = "SLM_BYTE_WRITE_BANK0_XECORE2",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache139__slm_byte_write_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache139_SLM_BYTE_WRITE_BANK0_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache140_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache140_SLM_BYTE_WRITE_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache140_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache140";
    metric_set->symbol_name = "L1Cache140";
    metric_set->hw_config_guid = "231e99e6-e1ad-47b3-ba45-2ac2846202b6";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache140_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache140__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache140__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache140__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache140__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK0 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE3",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache140__load_store_cache_byte_write_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache140_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE3_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK0 XECORE3",
                .symbol_name = "SLM_BYTE_WRITE_BANK0_XECORE3",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache140__slm_byte_write_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache140_SLM_BYTE_WRITE_BANK0_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache141_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache141_SLM_BYTE_WRITE_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache141_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache141";
    metric_set->symbol_name = "L1Cache141";
    metric_set->hw_config_guid = "34ccdeff-29d0-4a12-8d2a-45d6ac39a2bf";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache141_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache141__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache141__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache141__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache141__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK1 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE0",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache141__load_store_cache_byte_write_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache141_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE0_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK1 XECORE0",
                .symbol_name = "SLM_BYTE_WRITE_BANK1_XECORE0",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache141__slm_byte_write_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache141_SLM_BYTE_WRITE_BANK1_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache142_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache142_SLM_BYTE_WRITE_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache142_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache142";
    metric_set->symbol_name = "L1Cache142";
    metric_set->hw_config_guid = "2e9e5b1f-3974-405c-a8a1-aeed17baca42";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache142_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache142__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache142__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache142__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache142__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK1 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE1",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache142__load_store_cache_byte_write_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache142_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE1_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK1 XECORE1",
                .symbol_name = "SLM_BYTE_WRITE_BANK1_XECORE1",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache142__slm_byte_write_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache142_SLM_BYTE_WRITE_BANK1_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache143_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache143_SLM_BYTE_WRITE_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache143_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache143";
    metric_set->symbol_name = "L1Cache143";
    metric_set->hw_config_guid = "7d8da90c-fd7c-482c-afed-007f8323285c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache143_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache143__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache143__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache143__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache143__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK1 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE2",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache143__load_store_cache_byte_write_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache143_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE2_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK1 XECORE2",
                .symbol_name = "SLM_BYTE_WRITE_BANK1_XECORE2",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache143__slm_byte_write_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache143_SLM_BYTE_WRITE_BANK1_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache144_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache144_SLM_BYTE_WRITE_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache144_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache144";
    metric_set->symbol_name = "L1Cache144";
    metric_set->hw_config_guid = "ab19e5f0-333d-4787-a32d-83f2396b1dd9";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache144_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache144__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache144__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache144__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache144__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK1 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE3",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache144__load_store_cache_byte_write_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache144_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE3_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK1 XECORE3",
                .symbol_name = "SLM_BYTE_WRITE_BANK1_XECORE3",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache144__slm_byte_write_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache144_SLM_BYTE_WRITE_BANK1_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache145_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache145_SLM_BYTE_WRITE_BANK2_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache145_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache145";
    metric_set->symbol_name = "L1Cache145";
    metric_set->hw_config_guid = "49fb217b-1f94-480f-9f7f-80350a8b3f05";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache145_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache145__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache145__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache145__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache145__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK2 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE0",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache145__load_store_cache_byte_write_bank2_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache145_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE0_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK2 XECORE0",
                .symbol_name = "SLM_BYTE_WRITE_BANK2_XECORE0",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache145__slm_byte_write_bank2_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache145_SLM_BYTE_WRITE_BANK2_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache146_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache146_SLM_BYTE_WRITE_BANK2_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache146_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache146";
    metric_set->symbol_name = "L1Cache146";
    metric_set->hw_config_guid = "448d0663-b147-4471-8bd3-41a75af71caa";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache146_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache146__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache146__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache146__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache146__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK2 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE1",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache146__load_store_cache_byte_write_bank2_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache146_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE1_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK2 XECORE1",
                .symbol_name = "SLM_BYTE_WRITE_BANK2_XECORE1",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache146__slm_byte_write_bank2_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache146_SLM_BYTE_WRITE_BANK2_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache147_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache147_SLM_BYTE_WRITE_BANK2_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache147_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache147";
    metric_set->symbol_name = "L1Cache147";
    metric_set->hw_config_guid = "b1dda4b7-b8aa-4db5-8e88-d09b47f092c0";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache147_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache147__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache147__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache147__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache147__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK2 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE2",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache147__load_store_cache_byte_write_bank2_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache147_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE2_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK2 XECORE2",
                .symbol_name = "SLM_BYTE_WRITE_BANK2_XECORE2",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache147__slm_byte_write_bank2_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache147_SLM_BYTE_WRITE_BANK2_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache148_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache148_SLM_BYTE_WRITE_BANK2_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache148_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache148";
    metric_set->symbol_name = "L1Cache148";
    metric_set->hw_config_guid = "c2eb3ac8-1dd9-4a95-9723-f4bb3e1f9040";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache148_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache148__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache148__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache148__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache148__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK2 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE3",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache148__load_store_cache_byte_write_bank2_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache148_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE3_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK2 XECORE3",
                .symbol_name = "SLM_BYTE_WRITE_BANK2_XECORE3",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache148__slm_byte_write_bank2_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache148_SLM_BYTE_WRITE_BANK2_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache149_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache149_SLM_BYTE_WRITE_BANK3_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache149_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache149";
    metric_set->symbol_name = "L1Cache149";
    metric_set->hw_config_guid = "1fc4fe4d-473a-42c1-a9d4-c68a23c1bc02";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache149_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache149__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache149__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache149__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache149__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK3 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE0",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache149__load_store_cache_byte_write_bank3_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache149_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE0_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK3 XECORE0",
                .symbol_name = "SLM_BYTE_WRITE_BANK3_XECORE0",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache149__slm_byte_write_bank3_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache149_SLM_BYTE_WRITE_BANK3_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache150_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache150_SLM_BYTE_WRITE_BANK3_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache150_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache150";
    metric_set->symbol_name = "L1Cache150";
    metric_set->hw_config_guid = "cb3742b7-e01b-4759-a5cf-a473ffdc1bae";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache150_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache150__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache150__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache150__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache150__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK3 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE1",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache150__load_store_cache_byte_write_bank3_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache150_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE1_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK3 XECORE1",
                .symbol_name = "SLM_BYTE_WRITE_BANK3_XECORE1",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache150__slm_byte_write_bank3_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache150_SLM_BYTE_WRITE_BANK3_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache151_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache151_SLM_BYTE_WRITE_BANK3_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache151_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache151";
    metric_set->symbol_name = "L1Cache151";
    metric_set->hw_config_guid = "e116bb6e-4a74-4d70-91ef-30162e83fa72";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache151_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache151__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache151__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache151__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache151__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK3 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE2",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache151__load_store_cache_byte_write_bank3_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache151_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE2_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK3 XECORE2",
                .symbol_name = "SLM_BYTE_WRITE_BANK3_XECORE2",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache151__slm_byte_write_bank3_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache151_SLM_BYTE_WRITE_BANK3_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache152_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache152_SLM_BYTE_WRITE_BANK3_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache152_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache152";
    metric_set->symbol_name = "L1Cache152";
    metric_set->hw_config_guid = "d2731321-319c-4e1e-8cc2-70832ed45e85";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache152_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache152__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache152__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache152__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache152__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK3 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE3",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache152__load_store_cache_byte_write_bank3_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache152_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE3_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK3 XECORE3",
                .symbol_name = "SLM_BYTE_WRITE_BANK3_XECORE3",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__l1_cache152__slm_byte_write_bank3_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache152_SLM_BYTE_WRITE_BANK3_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_l1_cache153_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache153_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache153_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache153_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache153_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache153";
    metric_set->symbol_name = "L1Cache153";
    metric_set->hw_config_guid = "9b3e9938-36a7-45fa-a855-a1664cca7e7b";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache153_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache153__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache153__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache153__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache153__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE0",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache153__load_store_cache_number_of_bank_access_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache153_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE1",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache153__load_store_cache_number_of_bank_access_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache153_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE2",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache153__load_store_cache_number_of_bank_access_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache153_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE3",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache153__load_store_cache_number_of_bank_access_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache153_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache154_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache154_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache154_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache154_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache154_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache154";
    metric_set->symbol_name = "L1Cache154";
    metric_set->hw_config_guid = "6588bbbc-22b5-4387-8263-2de455505fe5";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache154_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache154__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache154__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache154__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache154__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE4",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache154__load_store_cache_number_of_bank_access_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache154_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE5",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache154__load_store_cache_number_of_bank_access_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache154_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE6",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache154__load_store_cache_number_of_bank_access_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache154_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE7",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache154__load_store_cache_number_of_bank_access_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache154_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache155_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache155_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache155_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache155_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache155_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache155";
    metric_set->symbol_name = "L1Cache155";
    metric_set->hw_config_guid = "916d2db4-8950-4577-b17a-91bae4439648";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache155_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache155__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache155__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache155__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache155__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE10",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE10",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache155__load_store_cache_number_of_bank_access_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache155_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE10_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE11",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE11",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache155__load_store_cache_number_of_bank_access_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache155_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE11_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE8",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE8",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache155__load_store_cache_number_of_bank_access_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache155_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE8_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE9",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE9",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache155__load_store_cache_number_of_bank_access_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache155_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l1_cache156_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache156_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache156_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_l1_cache156_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l1_cache156_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1Cache156";
    metric_set->symbol_name = "L1Cache156";
    metric_set->hw_config_guid = "60481905-7439-44f1-81b6-ef356e002f74";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l1_cache156_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l1_cache156__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l1_cache156__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l1_cache156__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l1_cache156__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE12",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE12",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache156__load_store_cache_number_of_bank_access_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache156_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE12_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE13",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE13",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache156__load_store_cache_number_of_bank_access_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache156_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE13_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE14",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE14",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache156__load_store_cache_number_of_bank_access_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache156_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE14_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE15",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE15",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l1_cache156__load_store_cache_number_of_bank_access_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt2_l1_cache156_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_l3_cache1_L3_INPUT_AVAILABLE_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache1_L3_INPUT_AVAILABLE_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache1_L3_INPUT_AVAILABLE_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache1_L3_INPUT_AVAILABLE_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache1_L3_INPUT_AVAILABLE_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache1_L3_INPUT_AVAILABLE_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache1_L3_INPUT_AVAILABLE_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache1_L3_INPUT_AVAILABLE_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache1_L3_OUTPUT_READY_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache1_L3_OUTPUT_READY_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache1_L3_OUTPUT_READY_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache1_L3_OUTPUT_READY_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache1_L3_OUTPUT_READY_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache1_L3_OUTPUT_READY_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache1_L3_OUTPUT_READY_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache1_L3_OUTPUT_READY_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l3_cache1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3Cache1";
    metric_set->symbol_name = "L3Cache1";
    metric_set->hw_config_guid = "e735a53a-442a-43e6-b5be-d1c89c017bf2";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l3_cache1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l3_cache1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l3_cache1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l3_cache1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l3_cache1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK0",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK0",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache1__l3_input_available_l3_bank0__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache1_L3_INPUT_AVAILABLE_L3BANK0_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK1",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK1",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache1__l3_input_available_l3_bank1__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache1_L3_INPUT_AVAILABLE_L3BANK1_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK2",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK2",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache1__l3_input_available_l3_bank2__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache1_L3_INPUT_AVAILABLE_L3BANK2_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK3",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK3",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache1__l3_input_available_l3_bank3__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache1_L3_INPUT_AVAILABLE_L3BANK3_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK4",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK4",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache1__l3_input_available_l3_bank4__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache1_L3_INPUT_AVAILABLE_L3BANK4_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK5",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK5",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache1__l3_input_available_l3_bank5__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache1_L3_INPUT_AVAILABLE_L3BANK5_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK6",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK6",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache1__l3_input_available_l3_bank6__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache1_L3_INPUT_AVAILABLE_L3BANK6_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK7",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK7",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache1__l3_input_available_l3_bank7__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache1_L3_INPUT_AVAILABLE_L3BANK7_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK0",
                .symbol_name = "L3_OUTPUT_READY_L3BANK0",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache1__l3_output_ready_l3_bank0__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache1_L3_OUTPUT_READY_L3BANK0_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK1",
                .symbol_name = "L3_OUTPUT_READY_L3BANK1",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache1__l3_output_ready_l3_bank1__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache1_L3_OUTPUT_READY_L3BANK1_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK2",
                .symbol_name = "L3_OUTPUT_READY_L3BANK2",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache1__l3_output_ready_l3_bank2__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache1_L3_OUTPUT_READY_L3BANK2_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK3",
                .symbol_name = "L3_OUTPUT_READY_L3BANK3",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache1__l3_output_ready_l3_bank3__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache1_L3_OUTPUT_READY_L3BANK3_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK4",
                .symbol_name = "L3_OUTPUT_READY_L3BANK4",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache1__l3_output_ready_l3_bank4__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache1_L3_OUTPUT_READY_L3BANK4_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK5",
                .symbol_name = "L3_OUTPUT_READY_L3BANK5",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache1__l3_output_ready_l3_bank5__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache1_L3_OUTPUT_READY_L3BANK5_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK6",
                .symbol_name = "L3_OUTPUT_READY_L3BANK6",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache1__l3_output_ready_l3_bank6__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache1_L3_OUTPUT_READY_L3BANK6_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK7",
                .symbol_name = "L3_OUTPUT_READY_L3BANK7",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache1__l3_output_ready_l3_bank7__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache1_L3_OUTPUT_READY_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_l3_cache2_L3_INPUT_AVAILABLE_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache2_L3_INPUT_AVAILABLE_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache2_L3_INPUT_AVAILABLE_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache2_L3_INPUT_AVAILABLE_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache2_L3_INPUT_AVAILABLE_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache2_L3_INPUT_AVAILABLE_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache2_L3_INPUT_AVAILABLE_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache2_L3_INPUT_AVAILABLE_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache2_L3_OUTPUT_READY_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache2_L3_OUTPUT_READY_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache2_L3_OUTPUT_READY_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache2_L3_OUTPUT_READY_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache2_L3_OUTPUT_READY_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache2_L3_OUTPUT_READY_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache2_L3_OUTPUT_READY_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache2_L3_OUTPUT_READY_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l3_cache2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3Cache2";
    metric_set->symbol_name = "L3Cache2";
    metric_set->hw_config_guid = "fd307172-3c1e-432f-8347-014d0a93e2be";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l3_cache2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l3_cache2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l3_cache2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l3_cache2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l3_cache2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK10",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK10",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache2__l3_input_available_l3_bank10__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache2_L3_INPUT_AVAILABLE_L3BANK10_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK11",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK11",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache2__l3_input_available_l3_bank11__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache2_L3_INPUT_AVAILABLE_L3BANK11_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK12",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK12",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache2__l3_input_available_l3_bank12__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache2_L3_INPUT_AVAILABLE_L3BANK12_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK13",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK13",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache2__l3_input_available_l3_bank13__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache2_L3_INPUT_AVAILABLE_L3BANK13_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK14",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK14",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache2__l3_input_available_l3_bank14__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache2_L3_INPUT_AVAILABLE_L3BANK14_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK15",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK15",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache2__l3_input_available_l3_bank15__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache2_L3_INPUT_AVAILABLE_L3BANK15_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK8",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK8",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache2__l3_input_available_l3_bank8__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache2_L3_INPUT_AVAILABLE_L3BANK8_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK9",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK9",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache2__l3_input_available_l3_bank9__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache2_L3_INPUT_AVAILABLE_L3BANK9_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK10",
                .symbol_name = "L3_OUTPUT_READY_L3BANK10",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache2__l3_output_ready_l3_bank10__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache2_L3_OUTPUT_READY_L3BANK10_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK11",
                .symbol_name = "L3_OUTPUT_READY_L3BANK11",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache2__l3_output_ready_l3_bank11__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache2_L3_OUTPUT_READY_L3BANK11_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK12",
                .symbol_name = "L3_OUTPUT_READY_L3BANK12",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache2__l3_output_ready_l3_bank12__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache2_L3_OUTPUT_READY_L3BANK12_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK13",
                .symbol_name = "L3_OUTPUT_READY_L3BANK13",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache2__l3_output_ready_l3_bank13__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache2_L3_OUTPUT_READY_L3BANK13_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK14",
                .symbol_name = "L3_OUTPUT_READY_L3BANK14",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache2__l3_output_ready_l3_bank14__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache2_L3_OUTPUT_READY_L3BANK14_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK15",
                .symbol_name = "L3_OUTPUT_READY_L3BANK15",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache2__l3_output_ready_l3_bank15__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache2_L3_OUTPUT_READY_L3BANK15_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK8",
                .symbol_name = "L3_OUTPUT_READY_L3BANK8",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache2__l3_output_ready_l3_bank8__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache2_L3_OUTPUT_READY_L3BANK8_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK9",
                .symbol_name = "L3_OUTPUT_READY_L3BANK9",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache2__l3_output_ready_l3_bank9__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache2_L3_OUTPUT_READY_L3BANK9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_l3_cache3_L3_READ_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache3_L3_READ_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache3_L3_READ_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache3_L3_READ_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache3_L3_READ_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache3_L3_READ_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache3_L3_READ_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache3_L3_READ_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache3_L3_WRITE_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache3_L3_WRITE_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache3_L3_WRITE_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache3_L3_WRITE_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache3_L3_WRITE_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache3_L3_WRITE_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache3_L3_WRITE_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache3_L3_WRITE_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l3_cache3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3Cache3";
    metric_set->symbol_name = "L3Cache3";
    metric_set->hw_config_guid = "44447e1a-90df-452e-b701-e38c034a4eca";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l3_cache3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l3_cache3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l3_cache3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l3_cache3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l3_cache3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 READ L3BANK0",
                .symbol_name = "L3_READ_L3BANK0",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache3__l3_read_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache3_L3_READ_L3BANK0_availability,
            },

            {
                .name = "L3 READ L3BANK1",
                .symbol_name = "L3_READ_L3BANK1",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache3__l3_read_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache3_L3_READ_L3BANK1_availability,
            },

            {
                .name = "L3 READ L3BANK2",
                .symbol_name = "L3_READ_L3BANK2",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache3__l3_read_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache3_L3_READ_L3BANK2_availability,
            },

            {
                .name = "L3 READ L3BANK3",
                .symbol_name = "L3_READ_L3BANK3",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache3__l3_read_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache3_L3_READ_L3BANK3_availability,
            },

            {
                .name = "L3 READ L3BANK4",
                .symbol_name = "L3_READ_L3BANK4",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache3__l3_read_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache3_L3_READ_L3BANK4_availability,
            },

            {
                .name = "L3 READ L3BANK5",
                .symbol_name = "L3_READ_L3BANK5",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache3__l3_read_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache3_L3_READ_L3BANK5_availability,
            },

            {
                .name = "L3 READ L3BANK6",
                .symbol_name = "L3_READ_L3BANK6",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache3__l3_read_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache3_L3_READ_L3BANK6_availability,
            },

            {
                .name = "L3 READ L3BANK7",
                .symbol_name = "L3_READ_L3BANK7",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache3__l3_read_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache3_L3_READ_L3BANK7_availability,
            },

            {
                .name = "L3 WRITE L3BANK0",
                .symbol_name = "L3_WRITE_L3BANK0",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache3__l3_write_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache3_L3_WRITE_L3BANK0_availability,
            },

            {
                .name = "L3 WRITE L3BANK1",
                .symbol_name = "L3_WRITE_L3BANK1",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache3__l3_write_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache3_L3_WRITE_L3BANK1_availability,
            },

            {
                .name = "L3 WRITE L3BANK2",
                .symbol_name = "L3_WRITE_L3BANK2",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache3__l3_write_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache3_L3_WRITE_L3BANK2_availability,
            },

            {
                .name = "L3 WRITE L3BANK3",
                .symbol_name = "L3_WRITE_L3BANK3",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache3__l3_write_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache3_L3_WRITE_L3BANK3_availability,
            },

            {
                .name = "L3 WRITE L3BANK4",
                .symbol_name = "L3_WRITE_L3BANK4",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache3__l3_write_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache3_L3_WRITE_L3BANK4_availability,
            },

            {
                .name = "L3 WRITE L3BANK5",
                .symbol_name = "L3_WRITE_L3BANK5",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache3__l3_write_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache3_L3_WRITE_L3BANK5_availability,
            },

            {
                .name = "L3 WRITE L3BANK6",
                .symbol_name = "L3_WRITE_L3BANK6",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache3__l3_write_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache3_L3_WRITE_L3BANK6_availability,
            },

            {
                .name = "L3 WRITE L3BANK7",
                .symbol_name = "L3_WRITE_L3BANK7",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache3__l3_write_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache3_L3_WRITE_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_l3_cache4_L3_READ_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache4_L3_READ_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache4_L3_READ_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache4_L3_READ_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache4_L3_READ_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache4_L3_READ_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache4_L3_READ_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache4_L3_READ_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache4_L3_WRITE_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache4_L3_WRITE_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache4_L3_WRITE_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache4_L3_WRITE_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache4_L3_WRITE_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache4_L3_WRITE_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache4_L3_WRITE_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache4_L3_WRITE_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l3_cache4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3Cache4";
    metric_set->symbol_name = "L3Cache4";
    metric_set->hw_config_guid = "e37c49ce-822e-43c5-9875-6945c962305e";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l3_cache4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l3_cache4__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l3_cache4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l3_cache4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l3_cache4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 READ L3BANK10",
                .symbol_name = "L3_READ_L3BANK10",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache4__l3_read_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache4_L3_READ_L3BANK10_availability,
            },

            {
                .name = "L3 READ L3BANK11",
                .symbol_name = "L3_READ_L3BANK11",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache4__l3_read_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache4_L3_READ_L3BANK11_availability,
            },

            {
                .name = "L3 READ L3BANK12",
                .symbol_name = "L3_READ_L3BANK12",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache4__l3_read_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache4_L3_READ_L3BANK12_availability,
            },

            {
                .name = "L3 READ L3BANK13",
                .symbol_name = "L3_READ_L3BANK13",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache4__l3_read_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache4_L3_READ_L3BANK13_availability,
            },

            {
                .name = "L3 READ L3BANK14",
                .symbol_name = "L3_READ_L3BANK14",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache4__l3_read_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache4_L3_READ_L3BANK14_availability,
            },

            {
                .name = "L3 READ L3BANK15",
                .symbol_name = "L3_READ_L3BANK15",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache4__l3_read_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache4_L3_READ_L3BANK15_availability,
            },

            {
                .name = "L3 READ L3BANK8",
                .symbol_name = "L3_READ_L3BANK8",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache4__l3_read_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache4_L3_READ_L3BANK8_availability,
            },

            {
                .name = "L3 READ L3BANK9",
                .symbol_name = "L3_READ_L3BANK9",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache4__l3_read_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache4_L3_READ_L3BANK9_availability,
            },

            {
                .name = "L3 WRITE L3BANK10",
                .symbol_name = "L3_WRITE_L3BANK10",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache4__l3_write_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache4_L3_WRITE_L3BANK10_availability,
            },

            {
                .name = "L3 WRITE L3BANK11",
                .symbol_name = "L3_WRITE_L3BANK11",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache4__l3_write_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache4_L3_WRITE_L3BANK11_availability,
            },

            {
                .name = "L3 WRITE L3BANK12",
                .symbol_name = "L3_WRITE_L3BANK12",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache4__l3_write_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache4_L3_WRITE_L3BANK12_availability,
            },

            {
                .name = "L3 WRITE L3BANK13",
                .symbol_name = "L3_WRITE_L3BANK13",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache4__l3_write_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache4_L3_WRITE_L3BANK13_availability,
            },

            {
                .name = "L3 WRITE L3BANK14",
                .symbol_name = "L3_WRITE_L3BANK14",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache4__l3_write_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache4_L3_WRITE_L3BANK14_availability,
            },

            {
                .name = "L3 WRITE L3BANK15",
                .symbol_name = "L3_WRITE_L3BANK15",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache4__l3_write_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache4_L3_WRITE_L3BANK15_availability,
            },

            {
                .name = "L3 WRITE L3BANK8",
                .symbol_name = "L3_WRITE_L3BANK8",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache4__l3_write_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache4_L3_WRITE_L3BANK8_availability,
            },

            {
                .name = "L3 WRITE L3BANK9",
                .symbol_name = "L3_WRITE_L3BANK9",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache4__l3_write_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache4_L3_WRITE_L3BANK9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_l3_cache5_L3_MISS_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache5_L3_MISS_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache5_L3_MISS_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache5_L3_MISS_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache5_L3_MISS_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache5_L3_MISS_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache5_L3_MISS_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache5_L3_MISS_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l3_cache5_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3Cache5";
    metric_set->symbol_name = "L3Cache5";
    metric_set->hw_config_guid = "45bb2f55-4b48-4d0d-882a-abfbac133ca4";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l3_cache5_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l3_cache5__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l3_cache5__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l3_cache5__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l3_cache5__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 HIT L3BANK0",
                .symbol_name = "L3_HIT_L3BANK0",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache5__l3_hit_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK1",
                .symbol_name = "L3_HIT_L3BANK1",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache5__l3_hit_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK2",
                .symbol_name = "L3_HIT_L3BANK2",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache5__l3_hit_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK3",
                .symbol_name = "L3_HIT_L3BANK3",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache5__l3_hit_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK4",
                .symbol_name = "L3_HIT_L3BANK4",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache5__l3_hit_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK5",
                .symbol_name = "L3_HIT_L3BANK5",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache5__l3_hit_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK6",
                .symbol_name = "L3_HIT_L3BANK6",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache5__l3_hit_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK7",
                .symbol_name = "L3_HIT_L3BANK7",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache5__l3_hit_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 MISS L3BANK0",
                .symbol_name = "L3_MISS_L3BANK0",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache5__l3_miss_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache5_L3_MISS_L3BANK0_availability,
            },

            {
                .name = "L3 MISS L3BANK1",
                .symbol_name = "L3_MISS_L3BANK1",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache5__l3_miss_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache5_L3_MISS_L3BANK1_availability,
            },

            {
                .name = "L3 MISS L3BANK2",
                .symbol_name = "L3_MISS_L3BANK2",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache5__l3_miss_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache5_L3_MISS_L3BANK2_availability,
            },

            {
                .name = "L3 MISS L3BANK3",
                .symbol_name = "L3_MISS_L3BANK3",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache5__l3_miss_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache5_L3_MISS_L3BANK3_availability,
            },

            {
                .name = "L3 MISS L3BANK4",
                .symbol_name = "L3_MISS_L3BANK4",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache5__l3_miss_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache5_L3_MISS_L3BANK4_availability,
            },

            {
                .name = "L3 MISS L3BANK5",
                .symbol_name = "L3_MISS_L3BANK5",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache5__l3_miss_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache5_L3_MISS_L3BANK5_availability,
            },

            {
                .name = "L3 MISS L3BANK6",
                .symbol_name = "L3_MISS_L3BANK6",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache5__l3_miss_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache5_L3_MISS_L3BANK6_availability,
            },

            {
                .name = "L3 MISS L3BANK7",
                .symbol_name = "L3_MISS_L3BANK7",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache5__l3_miss_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache5_L3_MISS_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_l3_cache6_L3_MISS_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache6_L3_MISS_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache6_L3_MISS_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache6_L3_MISS_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache6_L3_MISS_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache6_L3_MISS_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache6_L3_MISS_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache6_L3_MISS_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l3_cache6_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3Cache6";
    metric_set->symbol_name = "L3Cache6";
    metric_set->hw_config_guid = "215b0c4c-5977-4f01-a4de-3c8f654e3573";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l3_cache6_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l3_cache6__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l3_cache6__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l3_cache6__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l3_cache6__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 HIT L3BANK10",
                .symbol_name = "L3_HIT_L3BANK10",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache6__l3_hit_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK11",
                .symbol_name = "L3_HIT_L3BANK11",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache6__l3_hit_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK12",
                .symbol_name = "L3_HIT_L3BANK12",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache6__l3_hit_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK13",
                .symbol_name = "L3_HIT_L3BANK13",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache6__l3_hit_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK14",
                .symbol_name = "L3_HIT_L3BANK14",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache6__l3_hit_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK15",
                .symbol_name = "L3_HIT_L3BANK15",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache6__l3_hit_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK8",
                .symbol_name = "L3_HIT_L3BANK8",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache6__l3_hit_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK9",
                .symbol_name = "L3_HIT_L3BANK9",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache6__l3_hit_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 MISS L3BANK10",
                .symbol_name = "L3_MISS_L3BANK10",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache6__l3_miss_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache6_L3_MISS_L3BANK10_availability,
            },

            {
                .name = "L3 MISS L3BANK11",
                .symbol_name = "L3_MISS_L3BANK11",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache6__l3_miss_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache6_L3_MISS_L3BANK11_availability,
            },

            {
                .name = "L3 MISS L3BANK12",
                .symbol_name = "L3_MISS_L3BANK12",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache6__l3_miss_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache6_L3_MISS_L3BANK12_availability,
            },

            {
                .name = "L3 MISS L3BANK13",
                .symbol_name = "L3_MISS_L3BANK13",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache6__l3_miss_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache6_L3_MISS_L3BANK13_availability,
            },

            {
                .name = "L3 MISS L3BANK14",
                .symbol_name = "L3_MISS_L3BANK14",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache6__l3_miss_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache6_L3_MISS_L3BANK14_availability,
            },

            {
                .name = "L3 MISS L3BANK15",
                .symbol_name = "L3_MISS_L3BANK15",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache6__l3_miss_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache6_L3_MISS_L3BANK15_availability,
            },

            {
                .name = "L3 MISS L3BANK8",
                .symbol_name = "L3_MISS_L3BANK8",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache6__l3_miss_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache6_L3_MISS_L3BANK8_availability,
            },

            {
                .name = "L3 MISS L3BANK9",
                .symbol_name = "L3_MISS_L3BANK9",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache6__l3_miss_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache6_L3_MISS_L3BANK9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_l3_cache7_DATAPORT_L3_READ_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache7_DATAPORT_L3_READ_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache7_DATAPORT_L3_READ_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache7_DATAPORT_L3_READ_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache7_DATAPORT_L3_READ_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache7_DATAPORT_L3_READ_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache7_DATAPORT_L3_READ_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache7_DATAPORT_L3_READ_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache7_DATAPORT_L3_WRITE_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache7_DATAPORT_L3_WRITE_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache7_DATAPORT_L3_WRITE_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache7_DATAPORT_L3_WRITE_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache7_DATAPORT_L3_WRITE_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache7_DATAPORT_L3_WRITE_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache7_DATAPORT_L3_WRITE_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache7_DATAPORT_L3_WRITE_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l3_cache7_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3Cache7";
    metric_set->symbol_name = "L3Cache7";
    metric_set->hw_config_guid = "47f3839a-9fcb-4bc5-85ed-7096d712cda6";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l3_cache7_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l3_cache7__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l3_cache7__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT L3 READ L3BANK0",
                .symbol_name = "DATAPORT_L3_READ_L3BANK0",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache7__dataport_l3_read_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache7_DATAPORT_L3_READ_L3BANK0_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK1",
                .symbol_name = "DATAPORT_L3_READ_L3BANK1",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache7__dataport_l3_read_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache7_DATAPORT_L3_READ_L3BANK1_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK2",
                .symbol_name = "DATAPORT_L3_READ_L3BANK2",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache7__dataport_l3_read_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache7_DATAPORT_L3_READ_L3BANK2_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK3",
                .symbol_name = "DATAPORT_L3_READ_L3BANK3",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache7__dataport_l3_read_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache7_DATAPORT_L3_READ_L3BANK3_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK4",
                .symbol_name = "DATAPORT_L3_READ_L3BANK4",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache7__dataport_l3_read_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache7_DATAPORT_L3_READ_L3BANK4_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK5",
                .symbol_name = "DATAPORT_L3_READ_L3BANK5",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache7__dataport_l3_read_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache7_DATAPORT_L3_READ_L3BANK5_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK6",
                .symbol_name = "DATAPORT_L3_READ_L3BANK6",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache7__dataport_l3_read_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache7_DATAPORT_L3_READ_L3BANK6_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK7",
                .symbol_name = "DATAPORT_L3_READ_L3BANK7",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache7__dataport_l3_read_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache7_DATAPORT_L3_READ_L3BANK7_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK0",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK0",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache7__dataport_l3_write_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache7_DATAPORT_L3_WRITE_L3BANK0_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK1",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK1",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache7__dataport_l3_write_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache7_DATAPORT_L3_WRITE_L3BANK1_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK2",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK2",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache7__dataport_l3_write_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache7_DATAPORT_L3_WRITE_L3BANK2_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK3",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK3",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache7__dataport_l3_write_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache7_DATAPORT_L3_WRITE_L3BANK3_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK4",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK4",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache7__dataport_l3_write_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache7_DATAPORT_L3_WRITE_L3BANK4_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK5",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK5",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache7__dataport_l3_write_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache7_DATAPORT_L3_WRITE_L3BANK5_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK6",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK6",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache7__dataport_l3_write_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache7_DATAPORT_L3_WRITE_L3BANK6_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK7",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK7",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache7__dataport_l3_write_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache7_DATAPORT_L3_WRITE_L3BANK7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l3_cache7__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l3_cache7__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_l3_cache8_DATAPORT_L3_READ_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache8_DATAPORT_L3_READ_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache8_DATAPORT_L3_READ_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache8_DATAPORT_L3_READ_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache8_DATAPORT_L3_READ_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache8_DATAPORT_L3_READ_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache8_DATAPORT_L3_READ_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache8_DATAPORT_L3_READ_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache8_DATAPORT_L3_WRITE_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache8_DATAPORT_L3_WRITE_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache8_DATAPORT_L3_WRITE_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache8_DATAPORT_L3_WRITE_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache8_DATAPORT_L3_WRITE_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache8_DATAPORT_L3_WRITE_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache8_DATAPORT_L3_WRITE_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache8_DATAPORT_L3_WRITE_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l3_cache8_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3Cache8";
    metric_set->symbol_name = "L3Cache8";
    metric_set->hw_config_guid = "84f32171-9963-413e-8f14-163a3e258342";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l3_cache8_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l3_cache8__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l3_cache8__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT L3 READ L3BANK10",
                .symbol_name = "DATAPORT_L3_READ_L3BANK10",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache8__dataport_l3_read_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache8_DATAPORT_L3_READ_L3BANK10_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK11",
                .symbol_name = "DATAPORT_L3_READ_L3BANK11",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache8__dataport_l3_read_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache8_DATAPORT_L3_READ_L3BANK11_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK12",
                .symbol_name = "DATAPORT_L3_READ_L3BANK12",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache8__dataport_l3_read_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache8_DATAPORT_L3_READ_L3BANK12_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK13",
                .symbol_name = "DATAPORT_L3_READ_L3BANK13",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache8__dataport_l3_read_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache8_DATAPORT_L3_READ_L3BANK13_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK14",
                .symbol_name = "DATAPORT_L3_READ_L3BANK14",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache8__dataport_l3_read_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache8_DATAPORT_L3_READ_L3BANK14_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK15",
                .symbol_name = "DATAPORT_L3_READ_L3BANK15",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache8__dataport_l3_read_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache8_DATAPORT_L3_READ_L3BANK15_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK8",
                .symbol_name = "DATAPORT_L3_READ_L3BANK8",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache8__dataport_l3_read_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache8_DATAPORT_L3_READ_L3BANK8_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK9",
                .symbol_name = "DATAPORT_L3_READ_L3BANK9",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache8__dataport_l3_read_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache8_DATAPORT_L3_READ_L3BANK9_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK10",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK10",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache8__dataport_l3_write_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache8_DATAPORT_L3_WRITE_L3BANK10_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK11",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK11",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache8__dataport_l3_write_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache8_DATAPORT_L3_WRITE_L3BANK11_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK12",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK12",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache8__dataport_l3_write_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache8_DATAPORT_L3_WRITE_L3BANK12_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK13",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK13",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache8__dataport_l3_write_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache8_DATAPORT_L3_WRITE_L3BANK13_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK14",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK14",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache8__dataport_l3_write_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache8_DATAPORT_L3_WRITE_L3BANK14_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK15",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK15",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache8__dataport_l3_write_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache8_DATAPORT_L3_WRITE_L3BANK15_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK8",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK8",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache8__dataport_l3_write_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache8_DATAPORT_L3_WRITE_L3BANK8_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK9",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK9",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache8__dataport_l3_write_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache8_DATAPORT_L3_WRITE_L3BANK9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l3_cache8__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l3_cache8__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_l3_cache9_ICACHE_L3_HIT_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache9_ICACHE_L3_HIT_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache9_ICACHE_L3_HIT_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache9_ICACHE_L3_HIT_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache9_ICACHE_L3_HIT_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache9_ICACHE_L3_HIT_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache9_ICACHE_L3_HIT_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache9_ICACHE_L3_HIT_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache9_ICACHE_L3_READ_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache9_ICACHE_L3_READ_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache9_ICACHE_L3_READ_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache9_ICACHE_L3_READ_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache9_ICACHE_L3_READ_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache9_ICACHE_L3_READ_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache9_ICACHE_L3_READ_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache9_ICACHE_L3_READ_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l3_cache9_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3Cache9";
    metric_set->symbol_name = "L3Cache9";
    metric_set->hw_config_guid = "9e9237e0-0d36-4e0d-8413-1109670a1f0f";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l3_cache9_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l3_cache9__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l3_cache9__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l3_cache9__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l3_cache9__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE L3 HIT L3BANK0",
                .symbol_name = "ICACHE_L3_HIT_L3BANK0",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache9__icache_l3_hit_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache9_ICACHE_L3_HIT_L3BANK0_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK1",
                .symbol_name = "ICACHE_L3_HIT_L3BANK1",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache9__icache_l3_hit_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache9_ICACHE_L3_HIT_L3BANK1_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK2",
                .symbol_name = "ICACHE_L3_HIT_L3BANK2",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache9__icache_l3_hit_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache9_ICACHE_L3_HIT_L3BANK2_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK3",
                .symbol_name = "ICACHE_L3_HIT_L3BANK3",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache9__icache_l3_hit_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache9_ICACHE_L3_HIT_L3BANK3_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK4",
                .symbol_name = "ICACHE_L3_HIT_L3BANK4",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache9__icache_l3_hit_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache9_ICACHE_L3_HIT_L3BANK4_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK5",
                .symbol_name = "ICACHE_L3_HIT_L3BANK5",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache9__icache_l3_hit_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache9_ICACHE_L3_HIT_L3BANK5_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK6",
                .symbol_name = "ICACHE_L3_HIT_L3BANK6",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache9__icache_l3_hit_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache9_ICACHE_L3_HIT_L3BANK6_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK7",
                .symbol_name = "ICACHE_L3_HIT_L3BANK7",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache9__icache_l3_hit_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache9_ICACHE_L3_HIT_L3BANK7_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK0",
                .symbol_name = "ICACHE_L3_READ_L3BANK0",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache9__icache_l3_read_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache9_ICACHE_L3_READ_L3BANK0_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK1",
                .symbol_name = "ICACHE_L3_READ_L3BANK1",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache9__icache_l3_read_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache9_ICACHE_L3_READ_L3BANK1_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK2",
                .symbol_name = "ICACHE_L3_READ_L3BANK2",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache9__icache_l3_read_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache9_ICACHE_L3_READ_L3BANK2_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK3",
                .symbol_name = "ICACHE_L3_READ_L3BANK3",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache9__icache_l3_read_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache9_ICACHE_L3_READ_L3BANK3_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK4",
                .symbol_name = "ICACHE_L3_READ_L3BANK4",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache9__icache_l3_read_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache9_ICACHE_L3_READ_L3BANK4_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK5",
                .symbol_name = "ICACHE_L3_READ_L3BANK5",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache9__icache_l3_read_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache9_ICACHE_L3_READ_L3BANK5_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK6",
                .symbol_name = "ICACHE_L3_READ_L3BANK6",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache9__icache_l3_read_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache9_ICACHE_L3_READ_L3BANK6_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK7",
                .symbol_name = "ICACHE_L3_READ_L3BANK7",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache9__icache_l3_read_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache9_ICACHE_L3_READ_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_l3_cache10_ICACHE_L3_HIT_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache10_ICACHE_L3_HIT_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache10_ICACHE_L3_HIT_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache10_ICACHE_L3_HIT_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache10_ICACHE_L3_HIT_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache10_ICACHE_L3_HIT_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache10_ICACHE_L3_HIT_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache10_ICACHE_L3_HIT_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache10_ICACHE_L3_READ_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache10_ICACHE_L3_READ_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache10_ICACHE_L3_READ_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache10_ICACHE_L3_READ_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache10_ICACHE_L3_READ_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache10_ICACHE_L3_READ_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache10_ICACHE_L3_READ_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache10_ICACHE_L3_READ_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l3_cache10_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3Cache10";
    metric_set->symbol_name = "L3Cache10";
    metric_set->hw_config_guid = "156b77b5-f696-42be-ad63-13a8372d5d51";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l3_cache10_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l3_cache10__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l3_cache10__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l3_cache10__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l3_cache10__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE L3 HIT L3BANK10",
                .symbol_name = "ICACHE_L3_HIT_L3BANK10",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache10__icache_l3_hit_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache10_ICACHE_L3_HIT_L3BANK10_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK11",
                .symbol_name = "ICACHE_L3_HIT_L3BANK11",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache10__icache_l3_hit_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache10_ICACHE_L3_HIT_L3BANK11_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK12",
                .symbol_name = "ICACHE_L3_HIT_L3BANK12",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache10__icache_l3_hit_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache10_ICACHE_L3_HIT_L3BANK12_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK13",
                .symbol_name = "ICACHE_L3_HIT_L3BANK13",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache10__icache_l3_hit_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache10_ICACHE_L3_HIT_L3BANK13_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK14",
                .symbol_name = "ICACHE_L3_HIT_L3BANK14",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache10__icache_l3_hit_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache10_ICACHE_L3_HIT_L3BANK14_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK15",
                .symbol_name = "ICACHE_L3_HIT_L3BANK15",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache10__icache_l3_hit_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache10_ICACHE_L3_HIT_L3BANK15_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK8",
                .symbol_name = "ICACHE_L3_HIT_L3BANK8",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache10__icache_l3_hit_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache10_ICACHE_L3_HIT_L3BANK8_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK9",
                .symbol_name = "ICACHE_L3_HIT_L3BANK9",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache10__icache_l3_hit_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache10_ICACHE_L3_HIT_L3BANK9_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK10",
                .symbol_name = "ICACHE_L3_READ_L3BANK10",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache10__icache_l3_read_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache10_ICACHE_L3_READ_L3BANK10_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK11",
                .symbol_name = "ICACHE_L3_READ_L3BANK11",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache10__icache_l3_read_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache10_ICACHE_L3_READ_L3BANK11_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK12",
                .symbol_name = "ICACHE_L3_READ_L3BANK12",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache10__icache_l3_read_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache10_ICACHE_L3_READ_L3BANK12_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK13",
                .symbol_name = "ICACHE_L3_READ_L3BANK13",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache10__icache_l3_read_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache10_ICACHE_L3_READ_L3BANK13_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK14",
                .symbol_name = "ICACHE_L3_READ_L3BANK14",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache10__icache_l3_read_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache10_ICACHE_L3_READ_L3BANK14_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK15",
                .symbol_name = "ICACHE_L3_READ_L3BANK15",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache10__icache_l3_read_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache10_ICACHE_L3_READ_L3BANK15_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK8",
                .symbol_name = "ICACHE_L3_READ_L3BANK8",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache10__icache_l3_read_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache10_ICACHE_L3_READ_L3BANK8_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK9",
                .symbol_name = "ICACHE_L3_READ_L3BANK9",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache10__icache_l3_read_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache10_ICACHE_L3_READ_L3BANK9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_l3_cache11_L3_BUSY_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache11_L3_BUSY_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache11_L3_BUSY_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache11_L3_BUSY_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache11_L3_STALL_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache11_L3_STALL_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache11_L3_STALL_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache11_L3_STALL_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l3_cache11_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3Cache11";
    metric_set->symbol_name = "L3Cache11";
    metric_set->hw_config_guid = "fd98f311-2512-48f3-b0fe-464f34238811";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l3_cache11_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l3_cache11__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l3_cache11__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l3_cache11__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l3_cache11__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BANK ACTIVE L3BANK0",
                .symbol_name = "L3_BUSY_L3BANK0",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache11__l3_busy_l3_bank0__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache11_L3_BUSY_L3BANK0_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK1",
                .symbol_name = "L3_BUSY_L3BANK1",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache11__l3_busy_l3_bank1__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache11_L3_BUSY_L3BANK1_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK2",
                .symbol_name = "L3_BUSY_L3BANK2",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache11__l3_busy_l3_bank2__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache11_L3_BUSY_L3BANK2_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK3",
                .symbol_name = "L3_BUSY_L3BANK3",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache11__l3_busy_l3_bank3__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache11_L3_BUSY_L3BANK3_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK0",
                .symbol_name = "L3_STALL_L3BANK0",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache11__l3_stall_l3_bank0__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache11_L3_STALL_L3BANK0_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK1",
                .symbol_name = "L3_STALL_L3BANK1",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache11__l3_stall_l3_bank1__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache11_L3_STALL_L3BANK1_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK2",
                .symbol_name = "L3_STALL_L3BANK2",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache11__l3_stall_l3_bank2__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache11_L3_STALL_L3BANK2_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK3",
                .symbol_name = "L3_STALL_L3BANK3",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache11__l3_stall_l3_bank3__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache11_L3_STALL_L3BANK3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_l3_cache12_L3_BUSY_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache12_L3_BUSY_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache12_L3_BUSY_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache12_L3_BUSY_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache12_L3_STALL_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache12_L3_STALL_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache12_L3_STALL_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache12_L3_STALL_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l3_cache12_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3Cache12";
    metric_set->symbol_name = "L3Cache12";
    metric_set->hw_config_guid = "efee1ff5-333a-49f5-8093-7b7a6196cfce";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l3_cache12_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l3_cache12__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l3_cache12__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l3_cache12__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l3_cache12__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BANK ACTIVE L3BANK4",
                .symbol_name = "L3_BUSY_L3BANK4",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache12__l3_busy_l3_bank4__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache12_L3_BUSY_L3BANK4_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK5",
                .symbol_name = "L3_BUSY_L3BANK5",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache12__l3_busy_l3_bank5__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache12_L3_BUSY_L3BANK5_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK6",
                .symbol_name = "L3_BUSY_L3BANK6",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache12__l3_busy_l3_bank6__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache12_L3_BUSY_L3BANK6_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK7",
                .symbol_name = "L3_BUSY_L3BANK7",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache12__l3_busy_l3_bank7__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache12_L3_BUSY_L3BANK7_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK4",
                .symbol_name = "L3_STALL_L3BANK4",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache12__l3_stall_l3_bank4__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache12_L3_STALL_L3BANK4_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK5",
                .symbol_name = "L3_STALL_L3BANK5",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache12__l3_stall_l3_bank5__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache12_L3_STALL_L3BANK5_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK6",
                .symbol_name = "L3_STALL_L3BANK6",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache12__l3_stall_l3_bank6__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache12_L3_STALL_L3BANK6_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK7",
                .symbol_name = "L3_STALL_L3BANK7",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache12__l3_stall_l3_bank7__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache12_L3_STALL_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_l3_cache13_L3_BUSY_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache13_L3_BUSY_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache13_L3_BUSY_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache13_L3_BUSY_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache13_L3_STALL_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache13_L3_STALL_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache13_L3_STALL_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache13_L3_STALL_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l3_cache13_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3Cache13";
    metric_set->symbol_name = "L3Cache13";
    metric_set->hw_config_guid = "a979c83d-ccd1-4aea-8a3f-966aa9e5a4aa";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l3_cache13_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l3_cache13__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l3_cache13__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l3_cache13__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l3_cache13__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BANK ACTIVE L3BANK10",
                .symbol_name = "L3_BUSY_L3BANK10",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache13__l3_busy_l3_bank10__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache13_L3_BUSY_L3BANK10_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK11",
                .symbol_name = "L3_BUSY_L3BANK11",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache13__l3_busy_l3_bank11__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache13_L3_BUSY_L3BANK11_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK8",
                .symbol_name = "L3_BUSY_L3BANK8",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache13__l3_busy_l3_bank8__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache13_L3_BUSY_L3BANK8_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK9",
                .symbol_name = "L3_BUSY_L3BANK9",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache13__l3_busy_l3_bank9__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache13_L3_BUSY_L3BANK9_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK10",
                .symbol_name = "L3_STALL_L3BANK10",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache13__l3_stall_l3_bank10__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache13_L3_STALL_L3BANK10_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK11",
                .symbol_name = "L3_STALL_L3BANK11",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache13__l3_stall_l3_bank11__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache13_L3_STALL_L3BANK11_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK8",
                .symbol_name = "L3_STALL_L3BANK8",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache13__l3_stall_l3_bank8__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache13_L3_STALL_L3BANK8_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK9",
                .symbol_name = "L3_STALL_L3BANK9",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache13__l3_stall_l3_bank9__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache13_L3_STALL_L3BANK9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_l3_cache14_L3_BUSY_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache14_L3_BUSY_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache14_L3_BUSY_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache14_L3_BUSY_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache14_L3_STALL_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache14_L3_STALL_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache14_L3_STALL_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache14_L3_STALL_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l3_cache14_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3Cache14";
    metric_set->symbol_name = "L3Cache14";
    metric_set->hw_config_guid = "6c0c13ac-31ac-4875-a5bd-a2a0ee46dd29";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l3_cache14_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l3_cache14__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l3_cache14__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l3_cache14__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l3_cache14__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BANK ACTIVE L3BANK12",
                .symbol_name = "L3_BUSY_L3BANK12",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache14__l3_busy_l3_bank12__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache14_L3_BUSY_L3BANK12_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK13",
                .symbol_name = "L3_BUSY_L3BANK13",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache14__l3_busy_l3_bank13__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache14_L3_BUSY_L3BANK13_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK14",
                .symbol_name = "L3_BUSY_L3BANK14",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache14__l3_busy_l3_bank14__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache14_L3_BUSY_L3BANK14_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK15",
                .symbol_name = "L3_BUSY_L3BANK15",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache14__l3_busy_l3_bank15__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache14_L3_BUSY_L3BANK15_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK12",
                .symbol_name = "L3_STALL_L3BANK12",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache14__l3_stall_l3_bank12__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache14_L3_STALL_L3BANK12_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK13",
                .symbol_name = "L3_STALL_L3BANK13",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache14__l3_stall_l3_bank13__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache14_L3_STALL_L3BANK13_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK14",
                .symbol_name = "L3_STALL_L3BANK14",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache14__l3_stall_l3_bank14__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache14_L3_STALL_L3BANK14_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK15",
                .symbol_name = "L3_STALL_L3BANK15",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache14__l3_stall_l3_bank15__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache14_L3_STALL_L3BANK15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_l3_cache15_SAMPLER_L3_HIT_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache15_SAMPLER_L3_HIT_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache15_SAMPLER_L3_HIT_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache15_SAMPLER_L3_HIT_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache15_SAMPLER_L3_HIT_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache15_SAMPLER_L3_HIT_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache15_SAMPLER_L3_HIT_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache15_SAMPLER_L3_HIT_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache15_SAMPLER_L3_READ_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache15_SAMPLER_L3_READ_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache15_SAMPLER_L3_READ_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache15_SAMPLER_L3_READ_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache15_SAMPLER_L3_READ_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache15_SAMPLER_L3_READ_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache15_SAMPLER_L3_READ_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache15_SAMPLER_L3_READ_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l3_cache15_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3Cache15";
    metric_set->symbol_name = "L3Cache15";
    metric_set->hw_config_guid = "7c562d8e-e5ab-44c4-8d2d-76026e6d9ac1";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l3_cache15_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l3_cache15__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l3_cache15__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l3_cache15__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l3_cache15__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER L3 HIT L3BANK0",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK0",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache15__sampler_l3_hit_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache15_SAMPLER_L3_HIT_L3BANK0_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK1",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK1",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache15__sampler_l3_hit_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache15_SAMPLER_L3_HIT_L3BANK1_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK2",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK2",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache15__sampler_l3_hit_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache15_SAMPLER_L3_HIT_L3BANK2_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK3",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK3",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache15__sampler_l3_hit_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache15_SAMPLER_L3_HIT_L3BANK3_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK4",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK4",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache15__sampler_l3_hit_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache15_SAMPLER_L3_HIT_L3BANK4_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK5",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK5",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache15__sampler_l3_hit_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache15_SAMPLER_L3_HIT_L3BANK5_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK6",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK6",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache15__sampler_l3_hit_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache15_SAMPLER_L3_HIT_L3BANK6_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK7",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK7",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache15__sampler_l3_hit_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache15_SAMPLER_L3_HIT_L3BANK7_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK0",
                .symbol_name = "SAMPLER_L3_READ_L3BANK0",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache15__sampler_l3_read_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache15_SAMPLER_L3_READ_L3BANK0_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK1",
                .symbol_name = "SAMPLER_L3_READ_L3BANK1",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache15__sampler_l3_read_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache15_SAMPLER_L3_READ_L3BANK1_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK2",
                .symbol_name = "SAMPLER_L3_READ_L3BANK2",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache15__sampler_l3_read_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache15_SAMPLER_L3_READ_L3BANK2_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK3",
                .symbol_name = "SAMPLER_L3_READ_L3BANK3",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache15__sampler_l3_read_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache15_SAMPLER_L3_READ_L3BANK3_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK4",
                .symbol_name = "SAMPLER_L3_READ_L3BANK4",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache15__sampler_l3_read_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache15_SAMPLER_L3_READ_L3BANK4_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK5",
                .symbol_name = "SAMPLER_L3_READ_L3BANK5",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache15__sampler_l3_read_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache15_SAMPLER_L3_READ_L3BANK5_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK6",
                .symbol_name = "SAMPLER_L3_READ_L3BANK6",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache15__sampler_l3_read_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache15_SAMPLER_L3_READ_L3BANK6_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK7",
                .symbol_name = "SAMPLER_L3_READ_L3BANK7",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache15__sampler_l3_read_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache15_SAMPLER_L3_READ_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_l3_cache16_SAMPLER_L3_HIT_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache16_SAMPLER_L3_HIT_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache16_SAMPLER_L3_HIT_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache16_SAMPLER_L3_HIT_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache16_SAMPLER_L3_HIT_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache16_SAMPLER_L3_HIT_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache16_SAMPLER_L3_HIT_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache16_SAMPLER_L3_HIT_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache16_SAMPLER_L3_READ_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache16_SAMPLER_L3_READ_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache16_SAMPLER_L3_READ_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache16_SAMPLER_L3_READ_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache16_SAMPLER_L3_READ_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache16_SAMPLER_L3_READ_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache16_SAMPLER_L3_READ_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache16_SAMPLER_L3_READ_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l3_cache16_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3Cache16";
    metric_set->symbol_name = "L3Cache16";
    metric_set->hw_config_guid = "7eb61dda-7e60-40ed-aaae-603533cf941f";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l3_cache16_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l3_cache16__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l3_cache16__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l3_cache16__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l3_cache16__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER L3 HIT L3BANK10",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK10",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache16__sampler_l3_hit_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache16_SAMPLER_L3_HIT_L3BANK10_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK11",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK11",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache16__sampler_l3_hit_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache16_SAMPLER_L3_HIT_L3BANK11_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK12",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK12",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache16__sampler_l3_hit_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache16_SAMPLER_L3_HIT_L3BANK12_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK13",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK13",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache16__sampler_l3_hit_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache16_SAMPLER_L3_HIT_L3BANK13_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK14",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK14",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache16__sampler_l3_hit_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache16_SAMPLER_L3_HIT_L3BANK14_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK15",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK15",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache16__sampler_l3_hit_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache16_SAMPLER_L3_HIT_L3BANK15_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK8",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK8",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache16__sampler_l3_hit_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache16_SAMPLER_L3_HIT_L3BANK8_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK9",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK9",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache16__sampler_l3_hit_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache16_SAMPLER_L3_HIT_L3BANK9_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK10",
                .symbol_name = "SAMPLER_L3_READ_L3BANK10",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache16__sampler_l3_read_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache16_SAMPLER_L3_READ_L3BANK10_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK11",
                .symbol_name = "SAMPLER_L3_READ_L3BANK11",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache16__sampler_l3_read_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache16_SAMPLER_L3_READ_L3BANK11_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK12",
                .symbol_name = "SAMPLER_L3_READ_L3BANK12",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache16__sampler_l3_read_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache16_SAMPLER_L3_READ_L3BANK12_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK13",
                .symbol_name = "SAMPLER_L3_READ_L3BANK13",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache16__sampler_l3_read_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache16_SAMPLER_L3_READ_L3BANK13_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK14",
                .symbol_name = "SAMPLER_L3_READ_L3BANK14",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache16__sampler_l3_read_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache16_SAMPLER_L3_READ_L3BANK14_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK15",
                .symbol_name = "SAMPLER_L3_READ_L3BANK15",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache16__sampler_l3_read_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache16_SAMPLER_L3_READ_L3BANK15_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK8",
                .symbol_name = "SAMPLER_L3_READ_L3BANK8",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache16__sampler_l3_read_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache16_SAMPLER_L3_READ_L3BANK8_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK9",
                .symbol_name = "SAMPLER_L3_READ_L3BANK9",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache16__sampler_l3_read_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache16_SAMPLER_L3_READ_L3BANK9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_l3_cache17_L3_SUPERQ_FULL_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache17_L3_SUPERQ_FULL_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache17_L3_SUPERQ_FULL_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache17_L3_SUPERQ_FULL_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache17_L3_SUPERQ_FULL_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache17_L3_SUPERQ_FULL_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache17_L3_SUPERQ_FULL_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache17_L3_SUPERQ_FULL_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l3_cache17_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3Cache17";
    metric_set->symbol_name = "L3Cache17";
    metric_set->hw_config_guid = "07329ee0-625a-45bf-851c-a8d7b8694afb";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l3_cache17_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l3_cache17__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l3_cache17__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l3_cache17__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l3_cache17__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 SUPERQ FULL L3BANK0",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK0",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache17__l3_superq_full_l3_bank0__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache17_L3_SUPERQ_FULL_L3BANK0_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK1",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK1",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache17__l3_superq_full_l3_bank1__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache17_L3_SUPERQ_FULL_L3BANK1_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK2",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK2",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache17__l3_superq_full_l3_bank2__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache17_L3_SUPERQ_FULL_L3BANK2_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK3",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK3",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache17__l3_superq_full_l3_bank3__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache17_L3_SUPERQ_FULL_L3BANK3_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK4",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK4",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache17__l3_superq_full_l3_bank4__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache17_L3_SUPERQ_FULL_L3BANK4_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK5",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK5",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache17__l3_superq_full_l3_bank5__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache17_L3_SUPERQ_FULL_L3BANK5_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK6",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK6",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache17__l3_superq_full_l3_bank6__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache17_L3_SUPERQ_FULL_L3BANK6_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK7",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK7",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache17__l3_superq_full_l3_bank7__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache17_L3_SUPERQ_FULL_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_l3_cache18_L3_SUPERQ_FULL_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache18_L3_SUPERQ_FULL_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache18_L3_SUPERQ_FULL_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache18_L3_SUPERQ_FULL_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache18_L3_SUPERQ_FULL_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache18_L3_SUPERQ_FULL_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache18_L3_SUPERQ_FULL_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache18_L3_SUPERQ_FULL_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l3_cache18_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3Cache18";
    metric_set->symbol_name = "L3Cache18";
    metric_set->hw_config_guid = "ee38be83-7e26-4c3d-83ce-4882411fba2a";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l3_cache18_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l3_cache18__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l3_cache18__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l3_cache18__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l3_cache18__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 SUPERQ FULL L3BANK10",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK10",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache18__l3_superq_full_l3_bank10__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache18_L3_SUPERQ_FULL_L3BANK10_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK11",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK11",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache18__l3_superq_full_l3_bank11__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache18_L3_SUPERQ_FULL_L3BANK11_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK12",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK12",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache18__l3_superq_full_l3_bank12__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache18_L3_SUPERQ_FULL_L3BANK12_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK13",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK13",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache18__l3_superq_full_l3_bank13__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache18_L3_SUPERQ_FULL_L3BANK13_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK14",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK14",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache18__l3_superq_full_l3_bank14__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache18_L3_SUPERQ_FULL_L3BANK14_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK15",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK15",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache18__l3_superq_full_l3_bank15__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache18_L3_SUPERQ_FULL_L3BANK15_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK8",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK8",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache18__l3_superq_full_l3_bank8__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache18_L3_SUPERQ_FULL_L3BANK8_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK9",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK9",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__l3_cache18__l3_superq_full_l3_bank9__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache18_L3_SUPERQ_FULL_L3BANK9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l3_cache19_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3Cache19";
    metric_set->symbol_name = "L3Cache19";
    metric_set->hw_config_guid = "9c3213fc-98df-4619-b6ed-3dbfe01b76e7";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l3_cache19_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l3_cache19__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l3_cache19__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "COLOR L3 HIT L3BANK0",
                .symbol_name = "COLOR_L3_HIT_L3BANK0",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache19__color_l3_hit_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK0_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK1",
                .symbol_name = "COLOR_L3_HIT_L3BANK1",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache19__color_l3_hit_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK1_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK10",
                .symbol_name = "COLOR_L3_HIT_L3BANK10",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache19__color_l3_hit_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK10_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK11",
                .symbol_name = "COLOR_L3_HIT_L3BANK11",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache19__color_l3_hit_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK11_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK12",
                .symbol_name = "COLOR_L3_HIT_L3BANK12",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache19__color_l3_hit_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK12_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK13",
                .symbol_name = "COLOR_L3_HIT_L3BANK13",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache19__color_l3_hit_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK13_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK14",
                .symbol_name = "COLOR_L3_HIT_L3BANK14",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache19__color_l3_hit_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK14_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK15",
                .symbol_name = "COLOR_L3_HIT_L3BANK15",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache19__color_l3_hit_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK15_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK2",
                .symbol_name = "COLOR_L3_HIT_L3BANK2",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache19__color_l3_hit_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK2_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK3",
                .symbol_name = "COLOR_L3_HIT_L3BANK3",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache19__color_l3_hit_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK3_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK4",
                .symbol_name = "COLOR_L3_HIT_L3BANK4",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache19__color_l3_hit_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK4_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK5",
                .symbol_name = "COLOR_L3_HIT_L3BANK5",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache19__color_l3_hit_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK5_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK6",
                .symbol_name = "COLOR_L3_HIT_L3BANK6",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache19__color_l3_hit_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK6_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK7",
                .symbol_name = "COLOR_L3_HIT_L3BANK7",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache19__color_l3_hit_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK7_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK8",
                .symbol_name = "COLOR_L3_HIT_L3BANK8",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache19__color_l3_hit_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK8_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK9",
                .symbol_name = "COLOR_L3_HIT_L3BANK9",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache19__color_l3_hit_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache19_COLOR_L3_HIT_L3BANK9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l3_cache19__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l3_cache19__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_l3_cache20_Z_L3_HIT_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache20_Z_L3_HIT_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache20_Z_L3_HIT_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache20_Z_L3_HIT_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache20_Z_L3_HIT_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache20_Z_L3_HIT_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache20_Z_L3_HIT_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache20_Z_L3_HIT_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache20_Z_L3_HIT_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache20_Z_L3_HIT_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache20_Z_L3_HIT_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache20_Z_L3_HIT_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache20_Z_L3_HIT_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache20_Z_L3_HIT_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache20_Z_L3_HIT_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache20_Z_L3_HIT_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l3_cache20_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3Cache20";
    metric_set->symbol_name = "L3Cache20";
    metric_set->hw_config_guid = "eeee50d3-45ec-4978-a359-c577c3c7ccdb";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l3_cache20_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l3_cache20__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l3_cache20__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l3_cache20__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l3_cache20__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Z L3 HIT L3BANK0",
                .symbol_name = "Z_L3_HIT_L3BANK0",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache20__z_l3_hit_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache20_Z_L3_HIT_L3BANK0_availability,
            },

            {
                .name = "Z L3 HIT L3BANK1",
                .symbol_name = "Z_L3_HIT_L3BANK1",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache20__z_l3_hit_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache20_Z_L3_HIT_L3BANK1_availability,
            },

            {
                .name = "Z L3 HIT L3BANK10",
                .symbol_name = "Z_L3_HIT_L3BANK10",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache20__z_l3_hit_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache20_Z_L3_HIT_L3BANK10_availability,
            },

            {
                .name = "Z L3 HIT L3BANK11",
                .symbol_name = "Z_L3_HIT_L3BANK11",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache20__z_l3_hit_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache20_Z_L3_HIT_L3BANK11_availability,
            },

            {
                .name = "Z L3 HIT L3BANK12",
                .symbol_name = "Z_L3_HIT_L3BANK12",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache20__z_l3_hit_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache20_Z_L3_HIT_L3BANK12_availability,
            },

            {
                .name = "Z L3 HIT L3BANK13",
                .symbol_name = "Z_L3_HIT_L3BANK13",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache20__z_l3_hit_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache20_Z_L3_HIT_L3BANK13_availability,
            },

            {
                .name = "Z L3 HIT L3BANK14",
                .symbol_name = "Z_L3_HIT_L3BANK14",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache20__z_l3_hit_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache20_Z_L3_HIT_L3BANK14_availability,
            },

            {
                .name = "Z L3 HIT L3BANK15",
                .symbol_name = "Z_L3_HIT_L3BANK15",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache20__z_l3_hit_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache20_Z_L3_HIT_L3BANK15_availability,
            },

            {
                .name = "Z L3 HIT L3BANK2",
                .symbol_name = "Z_L3_HIT_L3BANK2",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache20__z_l3_hit_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache20_Z_L3_HIT_L3BANK2_availability,
            },

            {
                .name = "Z L3 HIT L3BANK3",
                .symbol_name = "Z_L3_HIT_L3BANK3",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache20__z_l3_hit_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache20_Z_L3_HIT_L3BANK3_availability,
            },

            {
                .name = "Z L3 HIT L3BANK4",
                .symbol_name = "Z_L3_HIT_L3BANK4",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache20__z_l3_hit_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache20_Z_L3_HIT_L3BANK4_availability,
            },

            {
                .name = "Z L3 HIT L3BANK5",
                .symbol_name = "Z_L3_HIT_L3BANK5",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache20__z_l3_hit_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache20_Z_L3_HIT_L3BANK5_availability,
            },

            {
                .name = "Z L3 HIT L3BANK6",
                .symbol_name = "Z_L3_HIT_L3BANK6",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache20__z_l3_hit_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache20_Z_L3_HIT_L3BANK6_availability,
            },

            {
                .name = "Z L3 HIT L3BANK7",
                .symbol_name = "Z_L3_HIT_L3BANK7",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache20__z_l3_hit_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache20_Z_L3_HIT_L3BANK7_availability,
            },

            {
                .name = "Z L3 HIT L3BANK8",
                .symbol_name = "Z_L3_HIT_L3BANK8",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache20__z_l3_hit_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache20_Z_L3_HIT_L3BANK8_availability,
            },

            {
                .name = "Z L3 HIT L3BANK9",
                .symbol_name = "Z_L3_HIT_L3BANK9",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache20__z_l3_hit_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache20_Z_L3_HIT_L3BANK9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l3_cache21_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3Cache21";
    metric_set->symbol_name = "L3Cache21";
    metric_set->hw_config_guid = "955bae70-17de-4328-ac24-3f8f2c8e1f78";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l3_cache21_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l3_cache21__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l3_cache21__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT L3 HIT L3BANK0",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK0",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache21__dataport_l3_hit_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK0_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK1",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK1",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache21__dataport_l3_hit_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK1_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK10",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK10",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache21__dataport_l3_hit_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK10_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK11",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK11",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache21__dataport_l3_hit_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK11_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK12",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK12",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache21__dataport_l3_hit_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK12_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK13",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK13",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache21__dataport_l3_hit_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK13_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK14",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK14",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache21__dataport_l3_hit_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK14_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK15",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK15",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache21__dataport_l3_hit_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK15_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK2",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK2",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache21__dataport_l3_hit_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK2_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK3",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK3",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache21__dataport_l3_hit_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK3_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK4",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK4",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache21__dataport_l3_hit_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK4_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK5",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK5",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache21__dataport_l3_hit_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK5_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK6",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK6",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache21__dataport_l3_hit_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK6_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK7",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK7",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache21__dataport_l3_hit_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK7_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK8",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK8",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache21__dataport_l3_hit_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK8_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK9",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK9",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache21__dataport_l3_hit_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache21_DATAPORT_L3_HIT_L3BANK9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l3_cache21__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l3_cache21__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt2_add_l3_cache22_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3Cache22";
    metric_set->symbol_name = "L3Cache22";
    metric_set->hw_config_guid = "a3076e23-85b3-4aae-bfa3-de0b0806fa54";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_l3_cache22_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__l3_cache22__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__l3_cache22__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__l3_cache22__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__l3_cache22__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK0",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK0",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache22__l3_atomic_access_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK0_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK1",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK1",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache22__l3_atomic_access_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK1_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK10",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK10",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache22__l3_atomic_access_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK10_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK11",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK11",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache22__l3_atomic_access_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK11_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK12",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK12",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache22__l3_atomic_access_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK12_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK13",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK13",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache22__l3_atomic_access_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK13_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK14",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK14",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache22__l3_atomic_access_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK14_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK15",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK15",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache22__l3_atomic_access_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK15_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK2",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK2",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache22__l3_atomic_access_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK2_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK3",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK3",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache22__l3_atomic_access_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK3_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK4",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK4",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache22__l3_atomic_access_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK4_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK5",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK5",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache22__l3_atomic_access_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK5_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK6",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK6",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache22__l3_atomic_access_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK6_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK7",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK7",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache22__l3_atomic_access_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK7_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK8",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK8",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache22__l3_atomic_access_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK8_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK9",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK9",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__l3_cache22__l3_atomic_access_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt2_l3_cache22_L3_ATOMIC_ACCESS_L3BANK9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}


static void
acmgt2_add_memory1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Memory1";
    metric_set->symbol_name = "Memory1";
    metric_set->hw_config_guid = "6b77c667-0ea4-4d77-9a2a-ae996fc127bc";
    metric_set->counters = calloc(23, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_memory1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__memory1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__memory1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY BYTE READ",
                .symbol_name = "GPU_MEMORY_BYTE_READ",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__memory1__gpu_memory_byte_read__read,
                .max_uint64 = acmgt2__memory1__gpu_memory_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ BW",
                .symbol_name = "GPU_MEMORY_BYTE_READ_BW",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) read bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt2__memory1__gpu_memory_byte_read_bw__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ BW SQIDI0",
                .symbol_name = "GPU_MEMORY_BYTE_READ_BW_SQIDI0",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) read bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt2__memory1__gpu_memory_byte_read_bw_sqidi0__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ BW SQIDI1",
                .symbol_name = "GPU_MEMORY_BYTE_READ_BW_SQIDI1",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) read bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt2__memory1__gpu_memory_byte_read_bw_sqidi1__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ BW SQIDI2",
                .symbol_name = "GPU_MEMORY_BYTE_READ_BW_SQIDI2",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) read bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt2__memory1__gpu_memory_byte_read_bw_sqidi2__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ BW SQIDI3",
                .symbol_name = "GPU_MEMORY_BYTE_READ_BW_SQIDI3",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) read bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt2__memory1__gpu_memory_byte_read_bw_sqidi3__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ SQIDI0",
                .symbol_name = "GPU_MEMORY_BYTE_READ_SQIDI0",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__memory1__gpu_memory_byte_read_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ SQIDI1",
                .symbol_name = "GPU_MEMORY_BYTE_READ_SQIDI1",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__memory1__gpu_memory_byte_read_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ SQIDI2",
                .symbol_name = "GPU_MEMORY_BYTE_READ_SQIDI2",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__memory1__gpu_memory_byte_read_sqidi2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ SQIDI3",
                .symbol_name = "GPU_MEMORY_BYTE_READ_SQIDI3",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__memory1__gpu_memory_byte_read_sqidi3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__memory1__gpu_memory_byte_write__read,
                .max_uint64 = acmgt2__memory1__gpu_memory_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE BW",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_BW",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) write bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt2__memory1__gpu_memory_byte_write_bw__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE BW SQIDI0",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_BW_SQIDI0",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) write bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt2__memory1__gpu_memory_byte_write_bw_sqidi0__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE BW SQIDI1",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_BW_SQIDI1",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) write bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt2__memory1__gpu_memory_byte_write_bw_sqidi1__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE BW SQIDI2",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_BW_SQIDI2",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) write bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt2__memory1__gpu_memory_byte_write_bw_sqidi2__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE BW SQIDI3",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_BW_SQIDI3",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) write bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt2__memory1__gpu_memory_byte_write_bw_sqidi3__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE SQIDI0",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_SQIDI0",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__memory1__gpu_memory_byte_write_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE SQIDI1",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_SQIDI1",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__memory1__gpu_memory_byte_write_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE SQIDI2",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_SQIDI2",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__memory1__gpu_memory_byte_write_sqidi2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE SQIDI3",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_SQIDI3",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt2__memory1__gpu_memory_byte_write_sqidi3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__memory1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__memory1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 23);
}


static void
acmgt2_add_memory2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Memory2";
    metric_set->symbol_name = "Memory2";
    metric_set->hw_config_guid = "d96f021b-8a19-44df-8f52-68ed64096056";
    metric_set->counters = calloc(8, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_memory2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__memory2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__memory2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY READ",
                .symbol_name = "GPU_MEMORY_READ",
                .desc = "Number of GTI memory reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory2__gpu_memory_read__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY READ SQIDI0",
                .symbol_name = "GPU_MEMORY_READ_SQIDI0",
                .desc = "Number of GTI memory reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory2__gpu_memory_read_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY READ SQIDI1",
                .symbol_name = "GPU_MEMORY_READ_SQIDI1",
                .desc = "Number of GTI memory reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory2__gpu_memory_read_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY READ SQIDI2",
                .symbol_name = "GPU_MEMORY_READ_SQIDI2",
                .desc = "Number of GTI memory reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory2__gpu_memory_read_sqidi2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY READ SQIDI3",
                .symbol_name = "GPU_MEMORY_READ_SQIDI3",
                .desc = "Number of GTI memory reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory2__gpu_memory_read_sqidi3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__memory2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__memory2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 8);
}


static void
acmgt2_add_memory3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Memory3";
    metric_set->symbol_name = "Memory3";
    metric_set->hw_config_guid = "1aefcfd0-08ce-4632-b634-2009d3303341";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_memory3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__memory3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__memory3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY WRITE",
                .symbol_name = "GPU_MEMORY_WRITE",
                .desc = "Number of GTI memory writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory3__gpu_memory_write__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY WRITE SQIDI0",
                .symbol_name = "GPU_MEMORY_WRITE_SQIDI0",
                .desc = "Number of GTI memory writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory3__gpu_memory_write_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY WRITE SQIDI1",
                .symbol_name = "GPU_MEMORY_WRITE_SQIDI1",
                .desc = "Number of GTI memory writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory3__gpu_memory_write_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY WRITE SQIDI2",
                .symbol_name = "GPU_MEMORY_WRITE_SQIDI2",
                .desc = "Number of GTI memory writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory3__gpu_memory_write_sqidi2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY WRITE SQIDI3",
                .symbol_name = "GPU_MEMORY_WRITE_SQIDI3",
                .desc = "Number of GTI memory writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory3__gpu_memory_write_sqidi3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__memory3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__memory3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HOST TO GPUMEM TRANSACTION READ",
                .symbol_name = "HOST_TO_GPUMEM_TRANSACTION_READ",
                .desc = "Number of host reads to GPU local (HBM) memory (downstream)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory3__host_to_gpumem_transaction_read__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "HOST TO GPUMEM TRANSACTION WRITE",
                .symbol_name = "HOST_TO_GPUMEM_TRANSACTION_WRITE",
                .desc = "Number of host writes to GPU local (HBM) memory (downstream)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory3__host_to_gpumem_transaction_write__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}


static void
acmgt2_add_memory4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Memory4";
    metric_set->symbol_name = "Memory4";
    metric_set->hw_config_guid = "d49bf819-990d-4638-a1f2-57943ad58d8d";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_memory4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__memory4__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__memory4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION READ SQIDI0",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_READ_SQIDI0",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory4__gpu_memory_32_b_transaction_read_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION READ SQIDI1",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_READ_SQIDI1",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory4__gpu_memory_32_b_transaction_read_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION READ SQIDI2",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_READ_SQIDI2",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory4__gpu_memory_32_b_transaction_read_sqidi2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION READ SQIDI3",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_READ_SQIDI3",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory4__gpu_memory_32_b_transaction_read_sqidi3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION READ SQIDI0",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_READ_SQIDI0",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory4__gpu_memory_64_b_transaction_read_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION READ SQIDI1",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_READ_SQIDI1",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory4__gpu_memory_64_b_transaction_read_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION READ SQIDI2",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_READ_SQIDI2",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory4__gpu_memory_64_b_transaction_read_sqidi2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION READ SQIDI3",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_READ_SQIDI3",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory4__gpu_memory_64_b_transaction_read_sqidi3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__memory4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__memory4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}


static void
acmgt2_add_memory5_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Memory5";
    metric_set->symbol_name = "Memory5";
    metric_set->hw_config_guid = "bd8af739-2f08-4384-823b-ea5fe198fee9";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_memory5_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__memory5__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__memory5__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION WRITE SQIDI0",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_WRITE_SQIDI0",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory5__gpu_memory_32_b_transaction_write_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION WRITE SQIDI1",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_WRITE_SQIDI1",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory5__gpu_memory_32_b_transaction_write_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION WRITE SQIDI2",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_WRITE_SQIDI2",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory5__gpu_memory_32_b_transaction_write_sqidi2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION WRITE SQIDI3",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_WRITE_SQIDI3",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory5__gpu_memory_32_b_transaction_write_sqidi3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION WRITE SQIDI0",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_WRITE_SQIDI0",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory5__gpu_memory_64_b_transaction_write_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION WRITE SQIDI1",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_WRITE_SQIDI1",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory5__gpu_memory_64_b_transaction_write_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION WRITE SQIDI2",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_WRITE_SQIDI2",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory5__gpu_memory_64_b_transaction_write_sqidi2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION WRITE SQIDI3",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_WRITE_SQIDI3",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory5__gpu_memory_64_b_transaction_write_sqidi3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__memory5__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__memory5__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}


static void
acmgt2_add_memory6_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Memory6";
    metric_set->symbol_name = "Memory6";
    metric_set->hw_config_guid = "b43a5fd8-3d74-46c4-9261-62c25070e559";
    metric_set->counters = calloc(13, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_memory6_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__memory6__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__memory6__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY ACTIVE",
                .symbol_name = "GPU_MEMORY_ACTIVE",
                .desc = "Percentage of time in which device local memory (HBM, GDDR, LPDDR, etc.) is active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__memory6__gpu_memory_active__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY ACTIVE SQIDI0",
                .symbol_name = "GPU_MEMORY_ACTIVE_SQIDI0",
                .desc = "Percentage of time in which device local memory (HBM, GDDR, LPDDR, etc.) is active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__memory6__gpu_memory_active_sqidi0__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY ACTIVE SQIDI1",
                .symbol_name = "GPU_MEMORY_ACTIVE_SQIDI1",
                .desc = "Percentage of time in which device local memory (HBM, GDDR, LPDDR, etc.) is active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__memory6__gpu_memory_active_sqidi1__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY ACTIVE SQIDI2",
                .symbol_name = "GPU_MEMORY_ACTIVE_SQIDI2",
                .desc = "Percentage of time in which device local memory (HBM, GDDR, LPDDR, etc.) is active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__memory6__gpu_memory_active_sqidi2__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY ACTIVE SQIDI3",
                .symbol_name = "GPU_MEMORY_ACTIVE_SQIDI3",
                .desc = "Percentage of time in which device local memory (HBM, GDDR, LPDDR, etc.) is active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__memory6__gpu_memory_active_sqidi3__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY REQUEST QUEUE FULL",
                .symbol_name = "GPU_MEMORY_REQUEST_QUEUE_FULL",
                .desc = "Percentage of time in which SQ is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__memory6__gpu_memory_request_queue_full__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY REQUEST QUEUE FULL SQIDI0",
                .symbol_name = "GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI0",
                .desc = "Percentage of time in which SQ is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__memory6__gpu_memory_request_queue_full_sqidi0__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY REQUEST QUEUE FULL SQIDI1",
                .symbol_name = "GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI1",
                .desc = "Percentage of time in which SQ is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__memory6__gpu_memory_request_queue_full_sqidi1__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY REQUEST QUEUE FULL SQIDI2",
                .symbol_name = "GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI2",
                .desc = "Percentage of time in which SQ is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__memory6__gpu_memory_request_queue_full_sqidi2__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY REQUEST QUEUE FULL SQIDI3",
                .symbol_name = "GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI3",
                .desc = "Percentage of time in which SQ is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__memory6__gpu_memory_request_queue_full_sqidi3__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__memory6__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__memory6__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 13);
}


static void
acmgt2_add_memory7_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Memory7";
    metric_set->symbol_name = "Memory7";
    metric_set->hw_config_guid = "51e468d7-f95f-4b2a-bfeb-01986463e901";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_memory7_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__memory7__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__memory7__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 WRITE SQIDI0",
                .symbol_name = "GPU_MEMORY_L3_WRITE_SQIDI0",
                .desc = "Number of GTI memory writes from L3 caused by L3 invalidations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory7__gpu_memory_l3_write_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__memory7__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__memory7__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SYSMEM TRANSACTION READ",
                .symbol_name = "SYSMEM_TRANSACTION_READ",
                .desc = "Number of system memory reads (upstream)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory7__sysmem_transaction_read__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "SYSMEM TRANSACTION WRITE",
                .symbol_name = "SYSMEM_TRANSACTION_WRITE",
                .desc = "Number of system memory writes (upstream)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory7__sysmem_transaction_write__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}


static void
acmgt2_add_memory8_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Memory8";
    metric_set->symbol_name = "Memory8";
    metric_set->hw_config_guid = "08667e1d-ae1b-4370-bc59-2347bb0d7f8d";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_memory8_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__memory8__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__memory8__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 WRITE SQIDI1",
                .symbol_name = "GPU_MEMORY_L3_WRITE_SQIDI1",
                .desc = "Number of GTI memory writes from L3 caused by L3 invalidations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory8__gpu_memory_l3_write_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__memory8__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__memory8__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt2_add_memory9_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Memory9";
    metric_set->symbol_name = "Memory9";
    metric_set->hw_config_guid = "b2462b2f-f73f-42d6-9b5e-46cae062d1c1";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_memory9_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__memory9__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__memory9__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 WRITE SQIDI2",
                .symbol_name = "GPU_MEMORY_L3_WRITE_SQIDI2",
                .desc = "Number of GTI memory writes from L3 caused by L3 invalidations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory9__gpu_memory_l3_write_sqidi2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__memory9__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__memory9__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt2_add_memory10_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Memory10";
    metric_set->symbol_name = "Memory10";
    metric_set->hw_config_guid = "15694e7b-c38d-4a65-a355-df93411ed0df";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_memory10_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__memory10__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__memory10__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 WRITE SQIDI3",
                .symbol_name = "GPU_MEMORY_L3_WRITE_SQIDI3",
                .desc = "Number of GTI memory writes from L3 caused by L3 invalidations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory10__gpu_memory_l3_write_sqidi3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__memory10__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__memory10__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt2_add_memory11_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Memory11";
    metric_set->symbol_name = "Memory11";
    metric_set->hw_config_guid = "84667f81-6441-46d7-844d-e13078a16811";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_memory11_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__memory11__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__memory11__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 READ SQIDI0",
                .symbol_name = "GPU_MEMORY_L3_READ_SQIDI0",
                .desc = "Number of GTI memory reads from L3 caused by L3 Cache misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory11__gpu_memory_l3_read_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__memory11__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__memory11__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt2_add_memory12_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Memory12";
    metric_set->symbol_name = "Memory12";
    metric_set->hw_config_guid = "3ec5f9fe-1567-456a-bb0c-f3b026813bd7";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_memory12_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__memory12__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__memory12__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 READ SQIDI1",
                .symbol_name = "GPU_MEMORY_L3_READ_SQIDI1",
                .desc = "Number of GTI memory reads from L3 caused by L3 Cache misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory12__gpu_memory_l3_read_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__memory12__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__memory12__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt2_add_memory13_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Memory13";
    metric_set->symbol_name = "Memory13";
    metric_set->hw_config_guid = "3ab47029-8b0b-4049-ac68-1ff07d0e7a6e";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_memory13_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__memory13__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__memory13__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 READ SQIDI2",
                .symbol_name = "GPU_MEMORY_L3_READ_SQIDI2",
                .desc = "Number of GTI memory reads from L3 caused by L3 Cache misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory13__gpu_memory_l3_read_sqidi2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__memory13__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__memory13__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt2_add_memory14_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Memory14";
    metric_set->symbol_name = "Memory14";
    metric_set->hw_config_guid = "8748eaa5-422c-4597-b4a1-519ccb6f4e95";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_memory14_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__memory14__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__memory14__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 READ SQIDI3",
                .symbol_name = "GPU_MEMORY_L3_READ_SQIDI3",
                .desc = "Number of GTI memory reads from L3 caused by L3 Cache misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__memory14__gpu_memory_l3_read_sqidi3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__memory14__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__memory14__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_rasterizer1_RASTERIZER_INPUT_AVAILABLE_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_rasterizer1_RASTERIZER_INPUT_AVAILABLE_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_rasterizer1_RASTERIZER_INPUT_AVAILABLE_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_rasterizer1_RASTERIZER_INPUT_AVAILABLE_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_rasterizer1_RASTERIZER_OUTPUT_READY_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_rasterizer1_RASTERIZER_OUTPUT_READY_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_rasterizer1_RASTERIZER_OUTPUT_READY_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_rasterizer1_RASTERIZER_OUTPUT_READY_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_rasterizer1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Rasterizer1";
    metric_set->symbol_name = "Rasterizer1";
    metric_set->hw_config_guid = "5050cadd-fc05-4183-b3dc-99f9ff5a0075";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_rasterizer1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__rasterizer1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__rasterizer1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__rasterizer1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__rasterizer1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RASTERIZER INPUT AVAILABLE SLICE0",
                .symbol_name = "RASTERIZER_INPUT_AVAILABLE_SLICE0",
                .desc = "Percentage of time in which Rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer1__rasterizer_input_available_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt2_rasterizer1_RASTERIZER_INPUT_AVAILABLE_SLICE0_availability,
            },

            {
                .name = "RASTERIZER INPUT AVAILABLE SLICE1",
                .symbol_name = "RASTERIZER_INPUT_AVAILABLE_SLICE1",
                .desc = "Percentage of time in which Rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer1__rasterizer_input_available_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt2_rasterizer1_RASTERIZER_INPUT_AVAILABLE_SLICE1_availability,
            },

            {
                .name = "RASTERIZER INPUT AVAILABLE SLICE2",
                .symbol_name = "RASTERIZER_INPUT_AVAILABLE_SLICE2",
                .desc = "Percentage of time in which Rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer1__rasterizer_input_available_slice2__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt2_rasterizer1_RASTERIZER_INPUT_AVAILABLE_SLICE2_availability,
            },

            {
                .name = "RASTERIZER INPUT AVAILABLE SLICE3",
                .symbol_name = "RASTERIZER_INPUT_AVAILABLE_SLICE3",
                .desc = "Percentage of time in which Rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer1__rasterizer_input_available_slice3__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt2_rasterizer1_RASTERIZER_INPUT_AVAILABLE_SLICE3_availability,
            },

            {
                .name = "RASTERIZER OUTPUT READY SLICE0",
                .symbol_name = "RASTERIZER_OUTPUT_READY_SLICE0",
                .desc = "Percentage of time in which Rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer1__rasterizer_output_ready_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt2_rasterizer1_RASTERIZER_OUTPUT_READY_SLICE0_availability,
            },

            {
                .name = "RASTERIZER OUTPUT READY SLICE1",
                .symbol_name = "RASTERIZER_OUTPUT_READY_SLICE1",
                .desc = "Percentage of time in which Rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer1__rasterizer_output_ready_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt2_rasterizer1_RASTERIZER_OUTPUT_READY_SLICE1_availability,
            },

            {
                .name = "RASTERIZER OUTPUT READY SLICE2",
                .symbol_name = "RASTERIZER_OUTPUT_READY_SLICE2",
                .desc = "Percentage of time in which Rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer1__rasterizer_output_ready_slice2__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt2_rasterizer1_RASTERIZER_OUTPUT_READY_SLICE2_availability,
            },

            {
                .name = "RASTERIZER OUTPUT READY SLICE3",
                .symbol_name = "RASTERIZER_OUTPUT_READY_SLICE3",
                .desc = "Percentage of time in which Rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__rasterizer1__rasterizer_output_ready_slice3__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt2_rasterizer1_RASTERIZER_OUTPUT_READY_SLICE3_availability,
            },

            {
                .name = "RASTERIZER SAMPLE OUTPUT",
                .symbol_name = "RASTERIZER_SAMPLE_OUTPUT",
                .desc = "Number of lit samples emitted by Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt2__rasterizer1__rasterizer_sample_output__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt2_rasterizer2_RASTERIZER_TRANSACTION_OUTPUT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_rasterizer2_RASTERIZER_TRANSACTION_OUTPUT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_rasterizer2_RASTERIZER_TRANSACTION_OUTPUT_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_rasterizer2_RASTERIZER_TRANSACTION_OUTPUT_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_rasterizer2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Rasterizer2";
    metric_set->symbol_name = "Rasterizer2";
    metric_set->hw_config_guid = "57ce566e-b572-4434-981c-558a16bd62d3";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_rasterizer2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__rasterizer2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__rasterizer2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__rasterizer2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__rasterizer2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RASTERIZER TRANSACTION OUTPUT SLICE0",
                .symbol_name = "RASTERIZER_TRANSACTION_OUTPUT_SLICE0",
                .desc = "Number of transactions pushed from Rasterizer to the Z pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__rasterizer2__rasterizer_transaction_output_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
                .availability = acmgt2_rasterizer2_RASTERIZER_TRANSACTION_OUTPUT_SLICE0_availability,
            },

            {
                .name = "RASTERIZER TRANSACTION OUTPUT SLICE1",
                .symbol_name = "RASTERIZER_TRANSACTION_OUTPUT_SLICE1",
                .desc = "Number of transactions pushed from Rasterizer to the Z pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__rasterizer2__rasterizer_transaction_output_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
                .availability = acmgt2_rasterizer2_RASTERIZER_TRANSACTION_OUTPUT_SLICE1_availability,
            },

            {
                .name = "RASTERIZER TRANSACTION OUTPUT SLICE2",
                .symbol_name = "RASTERIZER_TRANSACTION_OUTPUT_SLICE2",
                .desc = "Number of transactions pushed from Rasterizer to the Z pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__rasterizer2__rasterizer_transaction_output_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
                .availability = acmgt2_rasterizer2_RASTERIZER_TRANSACTION_OUTPUT_SLICE2_availability,
            },

            {
                .name = "RASTERIZER TRANSACTION OUTPUT SLICE3",
                .symbol_name = "RASTERIZER_TRANSACTION_OUTPUT_SLICE3",
                .desc = "Number of transactions pushed from Rasterizer to the Z pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__rasterizer2__rasterizer_transaction_output_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
                .availability = acmgt2_rasterizer2_RASTERIZER_TRANSACTION_OUTPUT_SLICE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing1_RT_INPUT_MESSAGE_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing1_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing1_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing1_RT_MESSAGE_STALL_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing1_RT_QUAD_TEST_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing1_RT_REQUEST_COLLISION_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing1_RT_TRANSFORM_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing1_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing1";
    metric_set->symbol_name = "RayTracing1";
    metric_set->hw_config_guid = "2db46c14-6718-46e3-a9a4-b2ba4aa10a3a";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE0",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE0",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing1__rt_input_message_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing1_RT_INPUT_MESSAGE_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE0",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing1__rt_load_store_cache_read_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing1_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE0",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE0",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing1__rt_load_store_cache_write_from_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing1_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE0",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE0",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing1__rt_message_stall_count_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing1_RT_MESSAGE_STALL_COUNT_XECORE0_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE0",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE0",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing1__rt_quad_test_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing1_RT_QUAD_TEST_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE0",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE0",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing1__rt_request_collision_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing1_RT_REQUEST_COLLISION_XECORE0_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE0",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE0",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing1__rt_transform_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing1_RT_TRANSFORM_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE0",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE0",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing1__rt_traversal_input_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing1_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_ray_tracing2_RT_INPUT_MESSAGE_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing2_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing2_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing2_RT_MESSAGE_STALL_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing2_RT_QUAD_TEST_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing2_RT_REQUEST_COLLISION_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing2_RT_TRANSFORM_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing2_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing2";
    metric_set->symbol_name = "RayTracing2";
    metric_set->hw_config_guid = "97513a9f-a2b6-4766-a2c7-530ae3271f9d";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE1",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE1",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing2__rt_input_message_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing2_RT_INPUT_MESSAGE_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE1",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing2__rt_load_store_cache_read_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing2_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE1",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE1",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing2__rt_load_store_cache_write_from_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing2_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE1",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE1",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing2__rt_message_stall_count_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing2_RT_MESSAGE_STALL_COUNT_XECORE1_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE1",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE1",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing2__rt_quad_test_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing2_RT_QUAD_TEST_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE1",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE1",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing2__rt_request_collision_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing2_RT_REQUEST_COLLISION_XECORE1_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE1",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE1",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing2__rt_transform_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing2_RT_TRANSFORM_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE1",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE1",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing2__rt_traversal_input_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing2_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_ray_tracing3_RT_INPUT_MESSAGE_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing3_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing3_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing3_RT_MESSAGE_STALL_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing3_RT_QUAD_TEST_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing3_RT_REQUEST_COLLISION_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing3_RT_TRANSFORM_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing3_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing3";
    metric_set->symbol_name = "RayTracing3";
    metric_set->hw_config_guid = "9ed83fc5-a773-479f-9cf4-146f2aca4e48";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE2",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE2",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing3__rt_input_message_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing3_RT_INPUT_MESSAGE_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE2",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing3__rt_load_store_cache_read_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing3_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE2",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE2",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing3__rt_load_store_cache_write_from_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing3_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE2",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE2",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing3__rt_message_stall_count_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing3_RT_MESSAGE_STALL_COUNT_XECORE2_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE2",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE2",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing3__rt_quad_test_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing3_RT_QUAD_TEST_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE2",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE2",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing3__rt_request_collision_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing3_RT_REQUEST_COLLISION_XECORE2_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE2",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE2",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing3__rt_transform_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing3_RT_TRANSFORM_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE2",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE2",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing3__rt_traversal_input_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing3_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_ray_tracing4_RT_INPUT_MESSAGE_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing4_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing4_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing4_RT_MESSAGE_STALL_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing4_RT_QUAD_TEST_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing4_RT_REQUEST_COLLISION_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing4_RT_TRANSFORM_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing4_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing4";
    metric_set->symbol_name = "RayTracing4";
    metric_set->hw_config_guid = "5564a1fd-d09e-46bd-8f4d-50a38ca7eb32";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing4__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE3",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE3",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing4__rt_input_message_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing4_RT_INPUT_MESSAGE_RAY_COUNT_XECORE3_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE3",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE3",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing4__rt_load_store_cache_read_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing4_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE3_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE3",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE3",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing4__rt_load_store_cache_write_from_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing4_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE3_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE3",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE3",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing4__rt_message_stall_count_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing4_RT_MESSAGE_STALL_COUNT_XECORE3_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE3",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE3",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing4__rt_quad_test_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing4_RT_QUAD_TEST_RAY_COUNT_XECORE3_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE3",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE3",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing4__rt_request_collision_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing4_RT_REQUEST_COLLISION_XECORE3_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE3",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE3",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing4__rt_transform_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing4_RT_TRANSFORM_RAY_COUNT_XECORE3_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE3",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE3",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing4__rt_traversal_input_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing4_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_ray_tracing5_RT_INPUT_MESSAGE_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing5_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing5_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing5_RT_MESSAGE_STALL_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing5_RT_QUAD_TEST_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing5_RT_REQUEST_COLLISION_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing5_RT_TRANSFORM_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing5_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing5_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing5";
    metric_set->symbol_name = "RayTracing5";
    metric_set->hw_config_guid = "d345e009-3b67-4991-89f8-7d57749f8455";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing5_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing5__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing5__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing5__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing5__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE4",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE4",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing5__rt_input_message_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing5_RT_INPUT_MESSAGE_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE4",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing5__rt_load_store_cache_read_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing5_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE4",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE4",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing5__rt_load_store_cache_write_from_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing5_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE4",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE4",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing5__rt_message_stall_count_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing5_RT_MESSAGE_STALL_COUNT_XECORE4_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE4",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE4",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing5__rt_quad_test_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing5_RT_QUAD_TEST_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE4",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE4",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing5__rt_request_collision_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing5_RT_REQUEST_COLLISION_XECORE4_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE4",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE4",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing5__rt_transform_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing5_RT_TRANSFORM_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE4",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE4",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing5__rt_traversal_input_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing5_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_ray_tracing6_RT_INPUT_MESSAGE_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing6_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing6_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing6_RT_MESSAGE_STALL_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing6_RT_QUAD_TEST_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing6_RT_REQUEST_COLLISION_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing6_RT_TRANSFORM_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing6_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing6_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing6";
    metric_set->symbol_name = "RayTracing6";
    metric_set->hw_config_guid = "08c76b7d-54fd-4dd2-8d7b-e84a91850b26";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing6_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing6__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing6__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing6__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing6__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE5",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE5",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing6__rt_input_message_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing6_RT_INPUT_MESSAGE_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE5",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE5",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing6__rt_load_store_cache_read_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing6_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE5",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE5",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing6__rt_load_store_cache_write_from_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing6_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE5",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE5",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing6__rt_message_stall_count_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing6_RT_MESSAGE_STALL_COUNT_XECORE5_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE5",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE5",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing6__rt_quad_test_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing6_RT_QUAD_TEST_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE5",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE5",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing6__rt_request_collision_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing6_RT_REQUEST_COLLISION_XECORE5_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE5",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE5",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing6__rt_transform_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing6_RT_TRANSFORM_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE5",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE5",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing6__rt_traversal_input_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing6_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_ray_tracing7_RT_INPUT_MESSAGE_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing7_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing7_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing7_RT_MESSAGE_STALL_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing7_RT_QUAD_TEST_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing7_RT_REQUEST_COLLISION_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing7_RT_TRANSFORM_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing7_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing7_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing7";
    metric_set->symbol_name = "RayTracing7";
    metric_set->hw_config_guid = "db089729-1516-43ef-b2ab-c2170bbefa69";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing7_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing7__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing7__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing7__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing7__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE6",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE6",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing7__rt_input_message_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing7_RT_INPUT_MESSAGE_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE6",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing7__rt_load_store_cache_read_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing7_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE6",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE6",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing7__rt_load_store_cache_write_from_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing7_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE6",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE6",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing7__rt_message_stall_count_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing7_RT_MESSAGE_STALL_COUNT_XECORE6_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE6",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE6",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing7__rt_quad_test_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing7_RT_QUAD_TEST_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE6",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE6",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing7__rt_request_collision_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing7_RT_REQUEST_COLLISION_XECORE6_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE6",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE6",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing7__rt_transform_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing7_RT_TRANSFORM_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE6",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE6",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing7__rt_traversal_input_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing7_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_ray_tracing8_RT_INPUT_MESSAGE_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing8_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing8_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing8_RT_MESSAGE_STALL_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing8_RT_QUAD_TEST_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing8_RT_REQUEST_COLLISION_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing8_RT_TRANSFORM_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing8_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing8_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing8";
    metric_set->symbol_name = "RayTracing8";
    metric_set->hw_config_guid = "080a531d-76e8-44b4-b17e-6c3557d01be7";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing8_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing8__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing8__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing8__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing8__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE7",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE7",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing8__rt_input_message_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing8_RT_INPUT_MESSAGE_RAY_COUNT_XECORE7_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE7",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing8__rt_load_store_cache_read_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing8_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE7",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE7",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing8__rt_load_store_cache_write_from_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing8_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE7_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE7",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE7",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing8__rt_message_stall_count_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing8_RT_MESSAGE_STALL_COUNT_XECORE7_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE7",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE7",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing8__rt_quad_test_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing8_RT_QUAD_TEST_RAY_COUNT_XECORE7_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE7",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE7",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing8__rt_request_collision_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing8_RT_REQUEST_COLLISION_XECORE7_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE7",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE7",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing8__rt_transform_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing8_RT_TRANSFORM_RAY_COUNT_XECORE7_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE7",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE7",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing8__rt_traversal_input_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing8_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_ray_tracing9_RT_INPUT_MESSAGE_RAY_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing9_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing9_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing9_RT_MESSAGE_STALL_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing9_RT_QUAD_TEST_RAY_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing9_RT_REQUEST_COLLISION_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing9_RT_TRANSFORM_RAY_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing9_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing9_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing9";
    metric_set->symbol_name = "RayTracing9";
    metric_set->hw_config_guid = "8edc7efe-7966-49b1-b318-49de98d12bc7";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing9_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing9__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing9__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing9__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing9__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE8",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE8",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing9__rt_input_message_ray_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing9_RT_INPUT_MESSAGE_RAY_COUNT_XECORE8_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE8",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE8",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing9__rt_load_store_cache_read_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing9_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE8_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE8",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE8",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing9__rt_load_store_cache_write_from_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing9_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE8_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE8",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE8",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing9__rt_message_stall_count_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing9_RT_MESSAGE_STALL_COUNT_XECORE8_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE8",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE8",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing9__rt_quad_test_ray_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing9_RT_QUAD_TEST_RAY_COUNT_XECORE8_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE8",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE8",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing9__rt_request_collision_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing9_RT_REQUEST_COLLISION_XECORE8_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE8",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE8",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing9__rt_transform_ray_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing9_RT_TRANSFORM_RAY_COUNT_XECORE8_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE8",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE8",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing9__rt_traversal_input_ray_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing9_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE8_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_ray_tracing10_RT_INPUT_MESSAGE_RAY_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing10_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing10_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing10_RT_MESSAGE_STALL_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing10_RT_QUAD_TEST_RAY_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing10_RT_REQUEST_COLLISION_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing10_RT_TRANSFORM_RAY_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing10_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing10_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing10";
    metric_set->symbol_name = "RayTracing10";
    metric_set->hw_config_guid = "98044ed5-0502-4b10-b288-db406e6c7345";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing10_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing10__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing10__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing10__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing10__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE9",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE9",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing10__rt_input_message_ray_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing10_RT_INPUT_MESSAGE_RAY_COUNT_XECORE9_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE9",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE9",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing10__rt_load_store_cache_read_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing10_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE9_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE9",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE9",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing10__rt_load_store_cache_write_from_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing10_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE9_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE9",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE9",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing10__rt_message_stall_count_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing10_RT_MESSAGE_STALL_COUNT_XECORE9_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE9",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE9",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing10__rt_quad_test_ray_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing10_RT_QUAD_TEST_RAY_COUNT_XECORE9_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE9",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE9",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing10__rt_request_collision_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing10_RT_REQUEST_COLLISION_XECORE9_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE9",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE9",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing10__rt_transform_ray_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing10_RT_TRANSFORM_RAY_COUNT_XECORE9_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE9",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE9",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing10__rt_traversal_input_ray_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing10_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_ray_tracing11_RT_INPUT_MESSAGE_RAY_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing11_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing11_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing11_RT_MESSAGE_STALL_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing11_RT_QUAD_TEST_RAY_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing11_RT_REQUEST_COLLISION_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing11_RT_TRANSFORM_RAY_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing11_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing11_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing11";
    metric_set->symbol_name = "RayTracing11";
    metric_set->hw_config_guid = "f15f0972-5362-4c24-a379-7d4da15a9cdb";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing11_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing11__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing11__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing11__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing11__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE10",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE10",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing11__rt_input_message_ray_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing11_RT_INPUT_MESSAGE_RAY_COUNT_XECORE10_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE10",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE10",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing11__rt_load_store_cache_read_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing11_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE10_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE10",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE10",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing11__rt_load_store_cache_write_from_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing11_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE10_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE10",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE10",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing11__rt_message_stall_count_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing11_RT_MESSAGE_STALL_COUNT_XECORE10_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE10",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE10",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing11__rt_quad_test_ray_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing11_RT_QUAD_TEST_RAY_COUNT_XECORE10_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE10",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE10",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing11__rt_request_collision_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing11_RT_REQUEST_COLLISION_XECORE10_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE10",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE10",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing11__rt_transform_ray_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing11_RT_TRANSFORM_RAY_COUNT_XECORE10_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE10",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE10",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing11__rt_traversal_input_ray_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing11_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE10_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_ray_tracing12_RT_INPUT_MESSAGE_RAY_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing12_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing12_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing12_RT_MESSAGE_STALL_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing12_RT_QUAD_TEST_RAY_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing12_RT_REQUEST_COLLISION_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing12_RT_TRANSFORM_RAY_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing12_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing12_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing12";
    metric_set->symbol_name = "RayTracing12";
    metric_set->hw_config_guid = "f9ceae49-ee15-4483-8033-5bcbc66c962e";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing12_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing12__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing12__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing12__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing12__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE11",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE11",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing12__rt_input_message_ray_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing12_RT_INPUT_MESSAGE_RAY_COUNT_XECORE11_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE11",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE11",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing12__rt_load_store_cache_read_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing12_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE11_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE11",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE11",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing12__rt_load_store_cache_write_from_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing12_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE11_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE11",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE11",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing12__rt_message_stall_count_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing12_RT_MESSAGE_STALL_COUNT_XECORE11_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE11",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE11",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing12__rt_quad_test_ray_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing12_RT_QUAD_TEST_RAY_COUNT_XECORE11_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE11",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE11",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing12__rt_request_collision_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing12_RT_REQUEST_COLLISION_XECORE11_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE11",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE11",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing12__rt_transform_ray_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing12_RT_TRANSFORM_RAY_COUNT_XECORE11_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE11",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE11",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing12__rt_traversal_input_ray_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing12_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_ray_tracing13_RT_INPUT_MESSAGE_RAY_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing13_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing13_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing13_RT_MESSAGE_STALL_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing13_RT_QUAD_TEST_RAY_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing13_RT_REQUEST_COLLISION_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing13_RT_TRANSFORM_RAY_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing13_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing13_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing13";
    metric_set->symbol_name = "RayTracing13";
    metric_set->hw_config_guid = "61aa5615-f570-4915-a9af-6c9ab3b52719";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing13_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing13__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing13__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing13__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing13__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE12",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE12",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing13__rt_input_message_ray_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing13_RT_INPUT_MESSAGE_RAY_COUNT_XECORE12_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE12",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE12",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing13__rt_load_store_cache_read_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing13_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE12_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE12",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE12",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing13__rt_load_store_cache_write_from_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing13_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE12_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE12",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE12",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing13__rt_message_stall_count_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing13_RT_MESSAGE_STALL_COUNT_XECORE12_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE12",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE12",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing13__rt_quad_test_ray_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing13_RT_QUAD_TEST_RAY_COUNT_XECORE12_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE12",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE12",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing13__rt_request_collision_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing13_RT_REQUEST_COLLISION_XECORE12_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE12",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE12",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing13__rt_transform_ray_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing13_RT_TRANSFORM_RAY_COUNT_XECORE12_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE12",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE12",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing13__rt_traversal_input_ray_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing13_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE12_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_ray_tracing14_RT_INPUT_MESSAGE_RAY_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing14_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing14_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing14_RT_MESSAGE_STALL_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing14_RT_QUAD_TEST_RAY_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing14_RT_REQUEST_COLLISION_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing14_RT_TRANSFORM_RAY_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing14_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing14_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing14";
    metric_set->symbol_name = "RayTracing14";
    metric_set->hw_config_guid = "638c0798-61d0-4943-b160-87b8095d87a3";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing14_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing14__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing14__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing14__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing14__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE13",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE13",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing14__rt_input_message_ray_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing14_RT_INPUT_MESSAGE_RAY_COUNT_XECORE13_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE13",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE13",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing14__rt_load_store_cache_read_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing14_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE13_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE13",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE13",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing14__rt_load_store_cache_write_from_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing14_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE13_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE13",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE13",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing14__rt_message_stall_count_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing14_RT_MESSAGE_STALL_COUNT_XECORE13_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE13",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE13",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing14__rt_quad_test_ray_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing14_RT_QUAD_TEST_RAY_COUNT_XECORE13_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE13",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE13",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing14__rt_request_collision_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing14_RT_REQUEST_COLLISION_XECORE13_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE13",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE13",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing14__rt_transform_ray_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing14_RT_TRANSFORM_RAY_COUNT_XECORE13_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE13",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE13",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing14__rt_traversal_input_ray_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing14_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_ray_tracing15_RT_INPUT_MESSAGE_RAY_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing15_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing15_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing15_RT_MESSAGE_STALL_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing15_RT_QUAD_TEST_RAY_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing15_RT_REQUEST_COLLISION_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing15_RT_TRANSFORM_RAY_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing15_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing15_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing15";
    metric_set->symbol_name = "RayTracing15";
    metric_set->hw_config_guid = "20c09ffa-66e3-45a8-8429-acdfb972e75b";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing15_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing15__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing15__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing15__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing15__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE14",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE14",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing15__rt_input_message_ray_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing15_RT_INPUT_MESSAGE_RAY_COUNT_XECORE14_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE14",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE14",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing15__rt_load_store_cache_read_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing15_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE14_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE14",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE14",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing15__rt_load_store_cache_write_from_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing15_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE14_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE14",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE14",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing15__rt_message_stall_count_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing15_RT_MESSAGE_STALL_COUNT_XECORE14_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE14",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE14",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing15__rt_quad_test_ray_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing15_RT_QUAD_TEST_RAY_COUNT_XECORE14_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE14",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE14",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing15__rt_request_collision_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing15_RT_REQUEST_COLLISION_XECORE14_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE14",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE14",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing15__rt_transform_ray_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing15_RT_TRANSFORM_RAY_COUNT_XECORE14_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE14",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE14",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing15__rt_traversal_input_ray_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing15_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE14_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_ray_tracing16_RT_INPUT_MESSAGE_RAY_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing16_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing16_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing16_RT_MESSAGE_STALL_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing16_RT_QUAD_TEST_RAY_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing16_RT_REQUEST_COLLISION_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing16_RT_TRANSFORM_RAY_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing16_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing16_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing16";
    metric_set->symbol_name = "RayTracing16";
    metric_set->hw_config_guid = "ea6550e2-b1cd-43d9-9f45-79146292d692";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing16_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing16__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing16__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing16__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing16__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE15",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE15",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing16__rt_input_message_ray_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing16_RT_INPUT_MESSAGE_RAY_COUNT_XECORE15_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE15",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE15",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing16__rt_load_store_cache_read_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing16_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE15_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE15",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE15",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing16__rt_load_store_cache_write_from_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing16_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE15_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE15",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE15",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing16__rt_message_stall_count_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing16_RT_MESSAGE_STALL_COUNT_XECORE15_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE15",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE15",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing16__rt_quad_test_ray_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing16_RT_QUAD_TEST_RAY_COUNT_XECORE15_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE15",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE15",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing16__rt_request_collision_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing16_RT_REQUEST_COLLISION_XECORE15_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE15",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE15",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing16__rt_transform_ray_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing16_RT_TRANSFORM_RAY_COUNT_XECORE15_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE15",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE15",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing16__rt_traversal_input_ray_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing16_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_ray_tracing17_RT_INSTANCE_NODE_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing17_RT_INTERNAL_NODE_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing17_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing17_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing17";
    metric_set->symbol_name = "RayTracing17";
    metric_set->hw_config_guid = "d10100fb-ac64-42a1-a418-b03e112ba033";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing17_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing17__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing17__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing17__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing17__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE0",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE0",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing17__rt_instance_node_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing17_RT_INSTANCE_NODE_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE0",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE0",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing17__rt_internal_node_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing17_RT_INTERNAL_NODE_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE0",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE0",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing17__rt_traversal_step_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing17_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_ray_tracing18_RT_INSTANCE_NODE_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing18_RT_INTERNAL_NODE_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing18_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing18_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing18";
    metric_set->symbol_name = "RayTracing18";
    metric_set->hw_config_guid = "f140f11f-5b0e-434d-ae88-cf1acd37ab49";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing18_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing18__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing18__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing18__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing18__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE1",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE1",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing18__rt_instance_node_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing18_RT_INSTANCE_NODE_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE1",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE1",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing18__rt_internal_node_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing18_RT_INTERNAL_NODE_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE1",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE1",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing18__rt_traversal_step_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing18_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_ray_tracing19_RT_INSTANCE_NODE_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing19_RT_INTERNAL_NODE_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing19_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing19_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing19";
    metric_set->symbol_name = "RayTracing19";
    metric_set->hw_config_guid = "011f9af3-43c4-45ac-b584-defd44cd442c";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing19_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing19__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing19__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing19__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing19__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE2",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE2",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing19__rt_instance_node_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing19_RT_INSTANCE_NODE_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE2",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE2",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing19__rt_internal_node_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing19_RT_INTERNAL_NODE_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE2",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE2",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing19__rt_traversal_step_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing19_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_ray_tracing20_RT_INSTANCE_NODE_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing20_RT_INTERNAL_NODE_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing20_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing20_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing20";
    metric_set->symbol_name = "RayTracing20";
    metric_set->hw_config_guid = "fd6ea82c-5618-4a96-b4eb-b7d63f72432f";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing20_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing20__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing20__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing20__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing20__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE3",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE3",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing20__rt_instance_node_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing20_RT_INSTANCE_NODE_RAY_COUNT_XECORE3_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE3",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE3",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing20__rt_internal_node_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing20_RT_INTERNAL_NODE_RAY_COUNT_XECORE3_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE3",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE3",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing20__rt_traversal_step_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing20_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_ray_tracing21_RT_INSTANCE_NODE_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing21_RT_INTERNAL_NODE_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing21_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing21_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing21";
    metric_set->symbol_name = "RayTracing21";
    metric_set->hw_config_guid = "cc205019-d6e9-4570-83f7-596dee6615a2";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing21_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing21__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing21__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing21__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing21__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE4",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE4",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing21__rt_instance_node_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing21_RT_INSTANCE_NODE_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE4",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE4",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing21__rt_internal_node_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing21_RT_INTERNAL_NODE_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE4",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE4",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing21__rt_traversal_step_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing21_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_ray_tracing22_RT_INSTANCE_NODE_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing22_RT_INTERNAL_NODE_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing22_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing22_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing22";
    metric_set->symbol_name = "RayTracing22";
    metric_set->hw_config_guid = "14a7e762-a069-46e6-8c2e-6555813c3047";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing22_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing22__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing22__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing22__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing22__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE5",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE5",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing22__rt_instance_node_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing22_RT_INSTANCE_NODE_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE5",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE5",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing22__rt_internal_node_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing22_RT_INTERNAL_NODE_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE5",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE5",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing22__rt_traversal_step_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing22_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_ray_tracing23_RT_INSTANCE_NODE_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing23_RT_INTERNAL_NODE_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing23_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing23_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing23";
    metric_set->symbol_name = "RayTracing23";
    metric_set->hw_config_guid = "ce74158a-e893-45a0-acd8-32ff5ac3e64c";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing23_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing23__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing23__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing23__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing23__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE6",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE6",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing23__rt_instance_node_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing23_RT_INSTANCE_NODE_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE6",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE6",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing23__rt_internal_node_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing23_RT_INTERNAL_NODE_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE6",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE6",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing23__rt_traversal_step_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing23_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_ray_tracing24_RT_INSTANCE_NODE_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing24_RT_INTERNAL_NODE_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing24_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing24_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing24";
    metric_set->symbol_name = "RayTracing24";
    metric_set->hw_config_guid = "cdbdfbe1-d554-4ec9-9eb0-8a03b5ab8e01";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing24_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing24__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing24__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing24__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing24__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE7",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE7",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing24__rt_instance_node_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing24_RT_INSTANCE_NODE_RAY_COUNT_XECORE7_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE7",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE7",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing24__rt_internal_node_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing24_RT_INTERNAL_NODE_RAY_COUNT_XECORE7_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE7",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE7",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing24__rt_traversal_step_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing24_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_ray_tracing25_RT_INSTANCE_NODE_RAY_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing25_RT_INTERNAL_NODE_RAY_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing25_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing25_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing25";
    metric_set->symbol_name = "RayTracing25";
    metric_set->hw_config_guid = "ff175695-a7d9-4623-9bf2-69b0bd950f3d";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing25_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing25__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing25__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing25__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing25__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE8",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE8",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing25__rt_instance_node_ray_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing25_RT_INSTANCE_NODE_RAY_COUNT_XECORE8_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE8",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE8",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing25__rt_internal_node_ray_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing25_RT_INTERNAL_NODE_RAY_COUNT_XECORE8_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE8",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE8",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing25__rt_traversal_step_ray_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing25_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE8_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_ray_tracing26_RT_INSTANCE_NODE_RAY_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing26_RT_INTERNAL_NODE_RAY_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing26_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing26_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing26";
    metric_set->symbol_name = "RayTracing26";
    metric_set->hw_config_guid = "b091df5b-4f20-4c91-a3d5-d2b376810ec2";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing26_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing26__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing26__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing26__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing26__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE9",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE9",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing26__rt_instance_node_ray_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing26_RT_INSTANCE_NODE_RAY_COUNT_XECORE9_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE9",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE9",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing26__rt_internal_node_ray_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing26_RT_INTERNAL_NODE_RAY_COUNT_XECORE9_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE9",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE9",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing26__rt_traversal_step_ray_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing26_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_ray_tracing27_RT_INSTANCE_NODE_RAY_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing27_RT_INTERNAL_NODE_RAY_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing27_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing27_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing27";
    metric_set->symbol_name = "RayTracing27";
    metric_set->hw_config_guid = "54634c6d-3ef3-4cd8-b80d-9642867ff9de";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing27_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing27__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing27__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing27__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing27__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE10",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE10",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing27__rt_instance_node_ray_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing27_RT_INSTANCE_NODE_RAY_COUNT_XECORE10_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE10",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE10",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing27__rt_internal_node_ray_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing27_RT_INTERNAL_NODE_RAY_COUNT_XECORE10_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE10",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE10",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing27__rt_traversal_step_ray_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing27_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE10_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_ray_tracing28_RT_INSTANCE_NODE_RAY_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing28_RT_INTERNAL_NODE_RAY_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing28_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing28_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing28";
    metric_set->symbol_name = "RayTracing28";
    metric_set->hw_config_guid = "284d68a1-6924-4746-8ac1-8e94a116be75";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing28_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing28__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing28__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing28__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing28__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE11",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE11",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing28__rt_instance_node_ray_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing28_RT_INSTANCE_NODE_RAY_COUNT_XECORE11_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE11",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE11",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing28__rt_internal_node_ray_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing28_RT_INTERNAL_NODE_RAY_COUNT_XECORE11_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE11",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE11",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing28__rt_traversal_step_ray_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing28_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_ray_tracing29_RT_INSTANCE_NODE_RAY_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing29_RT_INTERNAL_NODE_RAY_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing29_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing29_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing29";
    metric_set->symbol_name = "RayTracing29";
    metric_set->hw_config_guid = "8129227a-30cf-40cc-85ea-95614a31975a";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing29_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing29__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing29__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing29__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing29__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE12",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE12",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing29__rt_instance_node_ray_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing29_RT_INSTANCE_NODE_RAY_COUNT_XECORE12_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE12",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE12",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing29__rt_internal_node_ray_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing29_RT_INTERNAL_NODE_RAY_COUNT_XECORE12_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE12",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE12",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing29__rt_traversal_step_ray_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing29_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE12_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_ray_tracing30_RT_INSTANCE_NODE_RAY_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing30_RT_INTERNAL_NODE_RAY_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing30_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing30_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing30";
    metric_set->symbol_name = "RayTracing30";
    metric_set->hw_config_guid = "4de4fb3e-bd28-4e5a-8fd8-01ca378184ce";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing30_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing30__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing30__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing30__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing30__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE13",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE13",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing30__rt_instance_node_ray_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing30_RT_INSTANCE_NODE_RAY_COUNT_XECORE13_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE13",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE13",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing30__rt_internal_node_ray_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing30_RT_INTERNAL_NODE_RAY_COUNT_XECORE13_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE13",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE13",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing30__rt_traversal_step_ray_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing30_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_ray_tracing31_RT_INSTANCE_NODE_RAY_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing31_RT_INTERNAL_NODE_RAY_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing31_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing31_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing31";
    metric_set->symbol_name = "RayTracing31";
    metric_set->hw_config_guid = "5acdb2be-3918-4eed-9bc5-f272bc175a3f";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing31_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing31__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing31__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing31__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing31__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE14",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE14",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing31__rt_instance_node_ray_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing31_RT_INSTANCE_NODE_RAY_COUNT_XECORE14_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE14",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE14",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing31__rt_internal_node_ray_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing31_RT_INTERNAL_NODE_RAY_COUNT_XECORE14_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE14",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE14",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing31__rt_traversal_step_ray_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing31_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE14_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_ray_tracing32_RT_INSTANCE_NODE_RAY_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing32_RT_INTERNAL_NODE_RAY_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing32_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing32_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing32";
    metric_set->symbol_name = "RayTracing32";
    metric_set->hw_config_guid = "10125720-3004-4838-8a03-24fff2d9fb06";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing32_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing32__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing32__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing32__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing32__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE15",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE15",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing32__rt_instance_node_ray_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing32_RT_INSTANCE_NODE_RAY_COUNT_XECORE15_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE15",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE15",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing32__rt_internal_node_ray_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing32_RT_INTERNAL_NODE_RAY_COUNT_XECORE15_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE15",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE15",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing32__rt_traversal_step_ray_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing32_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_ray_tracing33_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing33_RT_QUAD_LEAF_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing33_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing33";
    metric_set->symbol_name = "RayTracing33";
    metric_set->hw_config_guid = "b1e299f2-35c3-4954-8cce-4fd1dd2491db";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing33_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing33__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing33__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing33__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing33__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE0",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE0",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing33__rt_procedural_node_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing33_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE0",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE0",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing33__rt_quad_leaf_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing33_RT_QUAD_LEAF_RAY_COUNT_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_ray_tracing34_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing34_RT_QUAD_LEAF_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing34_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing34";
    metric_set->symbol_name = "RayTracing34";
    metric_set->hw_config_guid = "bf47e090-9786-47b2-bf6d-746b7970001e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing34_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing34__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing34__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing34__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing34__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE1",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE1",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing34__rt_procedural_node_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing34_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE1",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE1",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing34__rt_quad_leaf_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing34_RT_QUAD_LEAF_RAY_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_ray_tracing35_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing35_RT_QUAD_LEAF_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing35_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing35";
    metric_set->symbol_name = "RayTracing35";
    metric_set->hw_config_guid = "df706146-44af-46d0-9ce4-0af556b009e3";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing35_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing35__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing35__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing35__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing35__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE2",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE2",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing35__rt_procedural_node_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing35_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE2",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE2",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing35__rt_quad_leaf_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing35_RT_QUAD_LEAF_RAY_COUNT_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_ray_tracing36_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing36_RT_QUAD_LEAF_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing36_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing36";
    metric_set->symbol_name = "RayTracing36";
    metric_set->hw_config_guid = "d1e152cd-ef8e-48c0-b63c-421e17083a0a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing36_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing36__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing36__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing36__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing36__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE3",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE3",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing36__rt_procedural_node_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing36_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE3_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE3",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE3",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing36__rt_quad_leaf_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing36_RT_QUAD_LEAF_RAY_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_ray_tracing37_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing37_RT_QUAD_LEAF_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing37_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing37";
    metric_set->symbol_name = "RayTracing37";
    metric_set->hw_config_guid = "e5cdc5f8-81f8-442c-a0c2-b94621efc7be";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing37_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing37__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing37__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing37__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing37__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE4",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE4",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing37__rt_procedural_node_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing37_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE4",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE4",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing37__rt_quad_leaf_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing37_RT_QUAD_LEAF_RAY_COUNT_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_ray_tracing38_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing38_RT_QUAD_LEAF_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing38_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing38";
    metric_set->symbol_name = "RayTracing38";
    metric_set->hw_config_guid = "6604e545-3a89-4f6e-a697-65b1f5bcb306";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing38_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing38__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing38__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing38__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing38__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE5",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE5",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing38__rt_procedural_node_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing38_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE5",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE5",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing38__rt_quad_leaf_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing38_RT_QUAD_LEAF_RAY_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_ray_tracing39_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing39_RT_QUAD_LEAF_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing39_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing39";
    metric_set->symbol_name = "RayTracing39";
    metric_set->hw_config_guid = "3b7d7a01-6242-4544-b68b-54eb4b2f59d7";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing39_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing39__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing39__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing39__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing39__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE6",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE6",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing39__rt_procedural_node_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing39_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE6",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE6",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing39__rt_quad_leaf_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing39_RT_QUAD_LEAF_RAY_COUNT_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_ray_tracing40_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing40_RT_QUAD_LEAF_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing40_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing40";
    metric_set->symbol_name = "RayTracing40";
    metric_set->hw_config_guid = "d7617e5d-23ae-482f-95fe-ae8615cf9172";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing40_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing40__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing40__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing40__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing40__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE7",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE7",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing40__rt_procedural_node_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing40_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE7_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE7",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE7",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing40__rt_quad_leaf_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing40_RT_QUAD_LEAF_RAY_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_ray_tracing41_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing41_RT_QUAD_LEAF_RAY_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing41_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing41";
    metric_set->symbol_name = "RayTracing41";
    metric_set->hw_config_guid = "f8410bd7-acba-4fd2-a2f4-9bec43057129";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing41_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing41__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing41__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing41__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing41__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE8",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE8",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing41__rt_procedural_node_ray_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing41_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE8_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE8",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE8",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing41__rt_quad_leaf_ray_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing41_RT_QUAD_LEAF_RAY_COUNT_XECORE8_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_ray_tracing42_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing42_RT_QUAD_LEAF_RAY_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing42_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing42";
    metric_set->symbol_name = "RayTracing42";
    metric_set->hw_config_guid = "c7cf55e8-7633-424a-a524-78c46698b5b3";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing42_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing42__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing42__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing42__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing42__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE9",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE9",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing42__rt_procedural_node_ray_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing42_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE9_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE9",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE9",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing42__rt_quad_leaf_ray_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing42_RT_QUAD_LEAF_RAY_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_ray_tracing43_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing43_RT_QUAD_LEAF_RAY_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing43_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing43";
    metric_set->symbol_name = "RayTracing43";
    metric_set->hw_config_guid = "5f5c6ff1-c38b-4b0a-bba9-187d65965cbd";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing43_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing43__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing43__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing43__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing43__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE10",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE10",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing43__rt_procedural_node_ray_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing43_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE10_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE10",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE10",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing43__rt_quad_leaf_ray_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing43_RT_QUAD_LEAF_RAY_COUNT_XECORE10_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_ray_tracing44_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing44_RT_QUAD_LEAF_RAY_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing44_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing44";
    metric_set->symbol_name = "RayTracing44";
    metric_set->hw_config_guid = "eeb417cc-d7ff-4713-92c8-dac7f5cf865d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing44_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing44__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing44__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing44__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing44__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE11",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE11",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing44__rt_procedural_node_ray_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing44_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE11_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE11",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE11",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing44__rt_quad_leaf_ray_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing44_RT_QUAD_LEAF_RAY_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_ray_tracing45_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing45_RT_QUAD_LEAF_RAY_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing45_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing45";
    metric_set->symbol_name = "RayTracing45";
    metric_set->hw_config_guid = "e7b14d21-de4f-46e5-9be9-619f8d0cac25";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing45_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing45__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing45__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing45__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing45__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE12",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE12",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing45__rt_procedural_node_ray_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing45_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE12_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE12",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE12",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing45__rt_quad_leaf_ray_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing45_RT_QUAD_LEAF_RAY_COUNT_XECORE12_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_ray_tracing46_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing46_RT_QUAD_LEAF_RAY_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing46_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing46";
    metric_set->symbol_name = "RayTracing46";
    metric_set->hw_config_guid = "243b4356-4036-42c6-bec9-40c9f2c15bb0";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing46_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing46__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing46__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing46__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing46__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE13",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE13",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing46__rt_procedural_node_ray_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing46_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE13_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE13",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE13",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing46__rt_quad_leaf_ray_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing46_RT_QUAD_LEAF_RAY_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_ray_tracing47_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing47_RT_QUAD_LEAF_RAY_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing47_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing47";
    metric_set->symbol_name = "RayTracing47";
    metric_set->hw_config_guid = "c1961a4a-56fa-4693-88f8-24c7c58f37fb";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing47_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing47__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing47__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing47__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing47__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE14",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE14",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing47__rt_procedural_node_ray_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing47_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE14_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE14",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE14",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing47__rt_quad_leaf_ray_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing47_RT_QUAD_LEAF_RAY_COUNT_XECORE14_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_ray_tracing48_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing48_RT_QUAD_LEAF_RAY_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing48_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing48";
    metric_set->symbol_name = "RayTracing48";
    metric_set->hw_config_guid = "0c4634e5-207a-4f8d-afd0-b7ee705e9a1c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing48_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing48__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing48__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing48__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing48__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE15",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE15",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing48__rt_procedural_node_ray_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing48_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE15_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE15",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE15",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing48__rt_quad_leaf_ray_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing48_RT_QUAD_LEAF_RAY_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt2_ray_tracing49_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing49_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing49_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing49_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing49_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing49";
    metric_set->symbol_name = "RayTracing49";
    metric_set->hw_config_guid = "3983a842-c461-43e4-86be-43f74d1fc1fc";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing49_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing49__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing49__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing49__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing49__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE0",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE0",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing49__rt_traversal_output_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing49_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE1",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE1",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing49__rt_traversal_output_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing49_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE2",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE2",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing49__rt_traversal_output_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing49_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE3",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE3",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing49__rt_traversal_output_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing49_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing50_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing50_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing50_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing50_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing50_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing50";
    metric_set->symbol_name = "RayTracing50";
    metric_set->hw_config_guid = "8da1e755-69e8-4c30-9d55-317dbd8c843b";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing50_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing50__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing50__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing50__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing50__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE4",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE4",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing50__rt_traversal_output_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing50_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE5",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE5",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing50__rt_traversal_output_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing50_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE6",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE6",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing50__rt_traversal_output_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing50_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE7",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE7",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing50__rt_traversal_output_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing50_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing51_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing51_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing51_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing51_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing51_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing51";
    metric_set->symbol_name = "RayTracing51";
    metric_set->hw_config_guid = "95175ccf-d7f5-47cd-aa92-3598fc431169";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing51_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing51__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing51__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing51__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing51__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE10",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE10",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing51__rt_traversal_output_ray_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing51_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE10_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE11",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE11",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing51__rt_traversal_output_ray_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing51_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE11_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE8",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE8",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing51__rt_traversal_output_ray_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing51_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE8_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE9",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE9",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing51__rt_traversal_output_ray_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing51_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing52_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing52_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing52_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing52_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing52_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing52";
    metric_set->symbol_name = "RayTracing52";
    metric_set->hw_config_guid = "d2d43104-87a6-4fe2-9979-5469dd33f9fd";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing52_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing52__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing52__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing52__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing52__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE12",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE12",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing52__rt_traversal_output_ray_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing52_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE12_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE13",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE13",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing52__rt_traversal_output_ray_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing52_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE13_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE14",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE14",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing52__rt_traversal_output_ray_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing52_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE14_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE15",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE15",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing52__rt_traversal_output_ray_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing52_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing53_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing53_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing53_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing53_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing53_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing53";
    metric_set->symbol_name = "RayTracing53";
    metric_set->hw_config_guid = "a51b5ede-d663-45a2-8ce1-f19dc664a936";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing53_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing53__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing53__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing53__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing53__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE0",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE0",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing53__rt_any_hit_thread_ray_dispatch_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing53_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE0_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE1",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE1",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing53__rt_any_hit_thread_ray_dispatch_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing53_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE1_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE2",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE2",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing53__rt_any_hit_thread_ray_dispatch_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing53_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE2_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE3",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE3",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing53__rt_any_hit_thread_ray_dispatch_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing53_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing54_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing54_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing54_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing54_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing54_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing54";
    metric_set->symbol_name = "RayTracing54";
    metric_set->hw_config_guid = "25676609-7d64-47ca-b92c-9128a9907f65";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing54_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing54__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing54__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing54__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing54__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE4",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE4",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing54__rt_any_hit_thread_ray_dispatch_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing54_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE4_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE5",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE5",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing54__rt_any_hit_thread_ray_dispatch_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing54_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE5_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE6",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE6",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing54__rt_any_hit_thread_ray_dispatch_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing54_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE6_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE7",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE7",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing54__rt_any_hit_thread_ray_dispatch_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing54_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing55_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing55_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing55_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing55_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing55_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing55";
    metric_set->symbol_name = "RayTracing55";
    metric_set->hw_config_guid = "1edc6759-9642-442c-9aa6-850ca7715097";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing55_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing55__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing55__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing55__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing55__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE10",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE10",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing55__rt_any_hit_thread_ray_dispatch_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing55_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE10_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE11",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE11",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing55__rt_any_hit_thread_ray_dispatch_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing55_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE11_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE8",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE8",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing55__rt_any_hit_thread_ray_dispatch_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing55_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE8_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE9",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE9",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing55__rt_any_hit_thread_ray_dispatch_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing55_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing56_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing56_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing56_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing56_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing56_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing56";
    metric_set->symbol_name = "RayTracing56";
    metric_set->hw_config_guid = "ecf6d5e1-928c-49dc-868b-89893073c183";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing56_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing56__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing56__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing56__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing56__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE12",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE12",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing56__rt_any_hit_thread_ray_dispatch_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing56_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE12_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE13",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE13",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing56__rt_any_hit_thread_ray_dispatch_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing56_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE13_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE14",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE14",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing56__rt_any_hit_thread_ray_dispatch_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing56_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE14_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE15",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE15",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing56__rt_any_hit_thread_ray_dispatch_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing56_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing57_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing57_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing57_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing57_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing57_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing57";
    metric_set->symbol_name = "RayTracing57";
    metric_set->hw_config_guid = "f8998902-7ceb-46ca-a62b-881dca4ff1f6";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing57_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing57__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing57__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing57__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing57__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE0",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE0",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing57__rt_callable_thread_ray_dispatch_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing57_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE0_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE1",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE1",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing57__rt_callable_thread_ray_dispatch_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing57_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE1_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE2",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE2",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing57__rt_callable_thread_ray_dispatch_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing57_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE2_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE3",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE3",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing57__rt_callable_thread_ray_dispatch_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing57_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing58_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing58_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing58_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing58_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing58_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing58";
    metric_set->symbol_name = "RayTracing58";
    metric_set->hw_config_guid = "b7b90bb9-b0b5-428d-a175-d9c89ecd35d1";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing58_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing58__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing58__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing58__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing58__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE4",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE4",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing58__rt_callable_thread_ray_dispatch_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing58_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE4_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE5",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE5",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing58__rt_callable_thread_ray_dispatch_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing58_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE5_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE6",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE6",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing58__rt_callable_thread_ray_dispatch_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing58_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE6_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE7",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE7",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing58__rt_callable_thread_ray_dispatch_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing58_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing59_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing59_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing59_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing59_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing59_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing59";
    metric_set->symbol_name = "RayTracing59";
    metric_set->hw_config_guid = "f7cd6361-0226-4e03-8856-cf375bd1264d";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing59_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing59__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing59__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing59__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing59__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE10",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE10",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing59__rt_callable_thread_ray_dispatch_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing59_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE10_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE11",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE11",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing59__rt_callable_thread_ray_dispatch_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing59_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE11_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE8",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE8",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing59__rt_callable_thread_ray_dispatch_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing59_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE8_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE9",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE9",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing59__rt_callable_thread_ray_dispatch_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing59_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing60_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing60_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing60_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing60_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing60_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing60";
    metric_set->symbol_name = "RayTracing60";
    metric_set->hw_config_guid = "945822ee-5469-4db5-b86e-c5f5255ac9fe";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing60_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing60__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing60__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing60__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing60__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE12",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE12",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing60__rt_callable_thread_ray_dispatch_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing60_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE12_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE13",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE13",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing60__rt_callable_thread_ray_dispatch_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing60_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE13_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE14",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE14",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing60__rt_callable_thread_ray_dispatch_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing60_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE14_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE15",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE15",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing60__rt_callable_thread_ray_dispatch_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing60_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing61_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing61_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing61_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing61_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing61_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing61";
    metric_set->symbol_name = "RayTracing61";
    metric_set->hw_config_guid = "8cd0af0d-1298-4414-aa94-5e13b6083af2";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing61_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing61__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing61__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing61__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing61__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE0",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE0",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing61__rt_closest_hit_thread_ray_dispatch_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing61_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE0_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE1",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE1",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing61__rt_closest_hit_thread_ray_dispatch_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing61_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE1_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE2",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE2",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing61__rt_closest_hit_thread_ray_dispatch_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing61_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE2_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE3",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE3",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing61__rt_closest_hit_thread_ray_dispatch_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing61_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing62_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing62_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing62_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing62_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing62_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing62";
    metric_set->symbol_name = "RayTracing62";
    metric_set->hw_config_guid = "bb7ccc48-ff70-4ec5-a35d-9b77ca79034a";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing62_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing62__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing62__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing62__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing62__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE4",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE4",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing62__rt_closest_hit_thread_ray_dispatch_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing62_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE4_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE5",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE5",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing62__rt_closest_hit_thread_ray_dispatch_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing62_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE5_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE6",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE6",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing62__rt_closest_hit_thread_ray_dispatch_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing62_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE6_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE7",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE7",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing62__rt_closest_hit_thread_ray_dispatch_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing62_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing63_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing63_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing63_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing63_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing63_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing63";
    metric_set->symbol_name = "RayTracing63";
    metric_set->hw_config_guid = "f4c111b5-6f5f-4109-9887-0968ddb7901e";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing63_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing63__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing63__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing63__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing63__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE10",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE10",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing63__rt_closest_hit_thread_ray_dispatch_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing63_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE10_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE11",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE11",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing63__rt_closest_hit_thread_ray_dispatch_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing63_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE11_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE8",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE8",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing63__rt_closest_hit_thread_ray_dispatch_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing63_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE8_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE9",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE9",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing63__rt_closest_hit_thread_ray_dispatch_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing63_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing64_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing64_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing64_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing64_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing64_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing64";
    metric_set->symbol_name = "RayTracing64";
    metric_set->hw_config_guid = "dd2c9174-67a1-4114-a71e-921548e9a033";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing64_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing64__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing64__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing64__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing64__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE12",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE12",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing64__rt_closest_hit_thread_ray_dispatch_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing64_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE12_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE13",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE13",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing64__rt_closest_hit_thread_ray_dispatch_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing64_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE13_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE14",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE14",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing64__rt_closest_hit_thread_ray_dispatch_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing64_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE14_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE15",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE15",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing64__rt_closest_hit_thread_ray_dispatch_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing64_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing65_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing65_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing65_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing65_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing65_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing65";
    metric_set->symbol_name = "RayTracing65";
    metric_set->hw_config_guid = "1a5ef45d-9d6c-4cde-804f-bdd054d2527a";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing65_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing65__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing65__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing65__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing65__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE0",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE0",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing65__rt_intersection_thread_ray_dispatch_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing65_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE0_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE1",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE1",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing65__rt_intersection_thread_ray_dispatch_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing65_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE1_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE2",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE2",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing65__rt_intersection_thread_ray_dispatch_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing65_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE2_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE3",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE3",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing65__rt_intersection_thread_ray_dispatch_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing65_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing66_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing66_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing66_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing66_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing66_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing66";
    metric_set->symbol_name = "RayTracing66";
    metric_set->hw_config_guid = "fa54a0b0-a5d0-4423-97c3-37cc477cbcca";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing66_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing66__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing66__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing66__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing66__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE4",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE4",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing66__rt_intersection_thread_ray_dispatch_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing66_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE4_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE5",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE5",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing66__rt_intersection_thread_ray_dispatch_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing66_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE5_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE6",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE6",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing66__rt_intersection_thread_ray_dispatch_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing66_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE6_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE7",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE7",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing66__rt_intersection_thread_ray_dispatch_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing66_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing67_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing67_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing67_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing67_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing67_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing67";
    metric_set->symbol_name = "RayTracing67";
    metric_set->hw_config_guid = "1efaa5e7-98d8-4752-8111-3b293d46b884";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing67_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing67__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing67__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing67__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing67__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE10",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE10",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing67__rt_intersection_thread_ray_dispatch_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing67_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE10_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE11",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE11",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing67__rt_intersection_thread_ray_dispatch_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing67_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE11_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE8",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE8",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing67__rt_intersection_thread_ray_dispatch_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing67_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE8_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE9",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE9",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing67__rt_intersection_thread_ray_dispatch_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing67_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing68_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing68_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing68_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing68_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing68_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing68";
    metric_set->symbol_name = "RayTracing68";
    metric_set->hw_config_guid = "046afd23-c347-4139-9768-ced28fb81d81";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing68_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing68__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing68__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing68__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing68__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE12",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE12",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing68__rt_intersection_thread_ray_dispatch_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing68_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE12_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE13",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE13",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing68__rt_intersection_thread_ray_dispatch_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing68_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE13_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE14",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE14",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing68__rt_intersection_thread_ray_dispatch_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing68_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE14_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE15",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE15",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing68__rt_intersection_thread_ray_dispatch_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing68_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing69_RT_MISS_THREAD_RAY_DISPATCH_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing69_RT_MISS_THREAD_RAY_DISPATCH_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing69_RT_MISS_THREAD_RAY_DISPATCH_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing69_RT_MISS_THREAD_RAY_DISPATCH_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing69_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing69";
    metric_set->symbol_name = "RayTracing69";
    metric_set->hw_config_guid = "7b00995c-f689-4a8a-862d-6391ffa9ceee";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing69_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing69__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing69__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing69__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing69__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE0",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE0",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing69__rt_miss_thread_ray_dispatch_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing69_RT_MISS_THREAD_RAY_DISPATCH_XECORE0_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE1",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE1",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing69__rt_miss_thread_ray_dispatch_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing69_RT_MISS_THREAD_RAY_DISPATCH_XECORE1_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE2",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE2",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing69__rt_miss_thread_ray_dispatch_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing69_RT_MISS_THREAD_RAY_DISPATCH_XECORE2_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE3",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE3",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing69__rt_miss_thread_ray_dispatch_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing69_RT_MISS_THREAD_RAY_DISPATCH_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing70_RT_MISS_THREAD_RAY_DISPATCH_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing70_RT_MISS_THREAD_RAY_DISPATCH_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing70_RT_MISS_THREAD_RAY_DISPATCH_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing70_RT_MISS_THREAD_RAY_DISPATCH_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing70_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing70";
    metric_set->symbol_name = "RayTracing70";
    metric_set->hw_config_guid = "981e8cee-e786-42de-9ca0-2ffbf6eb4ed1";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing70_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing70__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing70__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing70__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing70__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE4",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE4",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing70__rt_miss_thread_ray_dispatch_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing70_RT_MISS_THREAD_RAY_DISPATCH_XECORE4_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE5",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE5",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing70__rt_miss_thread_ray_dispatch_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing70_RT_MISS_THREAD_RAY_DISPATCH_XECORE5_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE6",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE6",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing70__rt_miss_thread_ray_dispatch_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing70_RT_MISS_THREAD_RAY_DISPATCH_XECORE6_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE7",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE7",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing70__rt_miss_thread_ray_dispatch_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing70_RT_MISS_THREAD_RAY_DISPATCH_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing71_RT_MISS_THREAD_RAY_DISPATCH_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing71_RT_MISS_THREAD_RAY_DISPATCH_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing71_RT_MISS_THREAD_RAY_DISPATCH_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing71_RT_MISS_THREAD_RAY_DISPATCH_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing71_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing71";
    metric_set->symbol_name = "RayTracing71";
    metric_set->hw_config_guid = "b02dcfab-bb8d-4327-ae9f-677412a38645";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing71_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing71__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing71__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing71__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing71__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE10",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE10",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing71__rt_miss_thread_ray_dispatch_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing71_RT_MISS_THREAD_RAY_DISPATCH_XECORE10_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE11",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE11",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing71__rt_miss_thread_ray_dispatch_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing71_RT_MISS_THREAD_RAY_DISPATCH_XECORE11_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE8",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE8",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing71__rt_miss_thread_ray_dispatch_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing71_RT_MISS_THREAD_RAY_DISPATCH_XECORE8_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE9",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE9",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing71__rt_miss_thread_ray_dispatch_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing71_RT_MISS_THREAD_RAY_DISPATCH_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing72_RT_MISS_THREAD_RAY_DISPATCH_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing72_RT_MISS_THREAD_RAY_DISPATCH_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing72_RT_MISS_THREAD_RAY_DISPATCH_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing72_RT_MISS_THREAD_RAY_DISPATCH_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing72_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing72";
    metric_set->symbol_name = "RayTracing72";
    metric_set->hw_config_guid = "87ae14d2-1266-4939-a094-0b69e0b7f171";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing72_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing72__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing72__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing72__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing72__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE12",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE12",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing72__rt_miss_thread_ray_dispatch_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing72_RT_MISS_THREAD_RAY_DISPATCH_XECORE12_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE13",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE13",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing72__rt_miss_thread_ray_dispatch_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing72_RT_MISS_THREAD_RAY_DISPATCH_XECORE13_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE14",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE14",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing72__rt_miss_thread_ray_dispatch_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing72_RT_MISS_THREAD_RAY_DISPATCH_XECORE14_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE15",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE15",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing72__rt_miss_thread_ray_dispatch_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing72_RT_MISS_THREAD_RAY_DISPATCH_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing73_RT_BVH_CACHE_MISS_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing73_RT_BVH_CACHE_MISS_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing73_RT_BVH_CACHE_MISS_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing73_RT_BVH_CACHE_MISS_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing73_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing73";
    metric_set->symbol_name = "RayTracing73";
    metric_set->hw_config_guid = "e561fce8-e7a3-44f6-950d-96e2c7e621e3";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing73_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing73__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing73__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing73__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing73__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT BVH CACHE MISS XECORE0",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE0",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing73__rt_bvh_cache_miss_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing73_RT_BVH_CACHE_MISS_XECORE0_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE1",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE1",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing73__rt_bvh_cache_miss_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing73_RT_BVH_CACHE_MISS_XECORE1_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE2",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE2",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing73__rt_bvh_cache_miss_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing73_RT_BVH_CACHE_MISS_XECORE2_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE3",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE3",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing73__rt_bvh_cache_miss_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing73_RT_BVH_CACHE_MISS_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing74_RT_BVH_CACHE_MISS_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing74_RT_BVH_CACHE_MISS_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing74_RT_BVH_CACHE_MISS_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing74_RT_BVH_CACHE_MISS_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing74_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing74";
    metric_set->symbol_name = "RayTracing74";
    metric_set->hw_config_guid = "f396f14f-c1f5-4f46-839a-ac7f00810d4b";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing74_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing74__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing74__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing74__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing74__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT BVH CACHE MISS XECORE4",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE4",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing74__rt_bvh_cache_miss_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing74_RT_BVH_CACHE_MISS_XECORE4_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE5",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE5",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing74__rt_bvh_cache_miss_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing74_RT_BVH_CACHE_MISS_XECORE5_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE6",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE6",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing74__rt_bvh_cache_miss_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing74_RT_BVH_CACHE_MISS_XECORE6_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE7",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE7",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing74__rt_bvh_cache_miss_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing74_RT_BVH_CACHE_MISS_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing75_RT_BVH_CACHE_MISS_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing75_RT_BVH_CACHE_MISS_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing75_RT_BVH_CACHE_MISS_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing75_RT_BVH_CACHE_MISS_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing75_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing75";
    metric_set->symbol_name = "RayTracing75";
    metric_set->hw_config_guid = "028f9e23-485e-4124-b061-6448a3a5b676";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing75_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing75__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing75__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing75__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing75__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT BVH CACHE MISS XECORE10",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE10",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing75__rt_bvh_cache_miss_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing75_RT_BVH_CACHE_MISS_XECORE10_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE11",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE11",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing75__rt_bvh_cache_miss_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing75_RT_BVH_CACHE_MISS_XECORE11_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE8",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE8",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing75__rt_bvh_cache_miss_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing75_RT_BVH_CACHE_MISS_XECORE8_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE9",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE9",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing75__rt_bvh_cache_miss_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing75_RT_BVH_CACHE_MISS_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing76_RT_BVH_CACHE_MISS_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing76_RT_BVH_CACHE_MISS_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing76_RT_BVH_CACHE_MISS_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing76_RT_BVH_CACHE_MISS_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing76_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing76";
    metric_set->symbol_name = "RayTracing76";
    metric_set->hw_config_guid = "57b2791d-0a96-42a3-8e1b-5692658c4f87";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing76_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing76__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing76__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing76__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing76__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT BVH CACHE MISS XECORE12",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE12",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing76__rt_bvh_cache_miss_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing76_RT_BVH_CACHE_MISS_XECORE12_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE13",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE13",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing76__rt_bvh_cache_miss_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing76_RT_BVH_CACHE_MISS_XECORE13_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE14",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE14",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing76__rt_bvh_cache_miss_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing76_RT_BVH_CACHE_MISS_XECORE14_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE15",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE15",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__ray_tracing76__rt_bvh_cache_miss_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing76_RT_BVH_CACHE_MISS_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_ray_tracing77_RT_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing77_RT_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing77_RT_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing77_RT_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing77_RT_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing77_RT_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing77_RT_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing77_RT_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing77_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing77";
    metric_set->symbol_name = "RayTracing77";
    metric_set->hw_config_guid = "a2ff8f41-89ef-4e9a-a7f0-31412cff350d";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing77_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing77__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing77__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing77__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing77__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT AVAILABLE XECORE0",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing77__rt_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing77_RT_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE1",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing77__rt_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing77_RT_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE2",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing77__rt_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing77_RT_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE3",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing77__rt_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing77_RT_INPUT_AVAILABLE_XECORE3_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE4",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing77__rt_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing77_RT_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE5",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing77__rt_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing77_RT_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE6",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing77__rt_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing77_RT_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE7",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing77__rt_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing77_RT_INPUT_AVAILABLE_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_ray_tracing78_RT_INPUT_AVAILABLE_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing78_RT_INPUT_AVAILABLE_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing78_RT_INPUT_AVAILABLE_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing78_RT_INPUT_AVAILABLE_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing78_RT_INPUT_AVAILABLE_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing78_RT_INPUT_AVAILABLE_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing78_RT_INPUT_AVAILABLE_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_ray_tracing78_RT_INPUT_AVAILABLE_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_ray_tracing78_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RayTracing78";
    metric_set->symbol_name = "RayTracing78";
    metric_set->hw_config_guid = "c9ed79c3-88ef-415b-8d59-a4da69888f66";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_ray_tracing78_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__ray_tracing78__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__ray_tracing78__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__ray_tracing78__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__ray_tracing78__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT AVAILABLE XECORE10",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE10",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing78__rt_input_available_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing78_RT_INPUT_AVAILABLE_XECORE10_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE11",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE11",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing78__rt_input_available_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing78_RT_INPUT_AVAILABLE_XECORE11_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE12",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE12",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing78__rt_input_available_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing78_RT_INPUT_AVAILABLE_XECORE12_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE13",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE13",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing78__rt_input_available_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing78_RT_INPUT_AVAILABLE_XECORE13_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE14",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE14",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing78__rt_input_available_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing78_RT_INPUT_AVAILABLE_XECORE14_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE15",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE15",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing78__rt_input_available_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing78_RT_INPUT_AVAILABLE_XECORE15_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE8",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE8",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing78__rt_input_available_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing78_RT_INPUT_AVAILABLE_XECORE8_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE9",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE9",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__ray_tracing78__rt_input_available_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt2_ray_tracing78_RT_INPUT_AVAILABLE_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_sampler1_SAMPLER_OUTPUT_READY_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler1_SAMPLER_OUTPUT_READY_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler1_SAMPLER_OUTPUT_READY_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler1_SAMPLER_OUTPUT_READY_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_sampler1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Sampler1";
    metric_set->symbol_name = "Sampler1";
    metric_set->hw_config_guid = "97b017f6-f65c-4a0c-8078-7a1cb65157f0";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_sampler1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__sampler1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__sampler1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__sampler1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__sampler1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE0",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE0",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler1__sampler_output_ready_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler1_SAMPLER_OUTPUT_READY_XECORE0_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE1",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE1",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler1__sampler_output_ready_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler1_SAMPLER_OUTPUT_READY_XECORE1_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE2",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE2",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler1__sampler_output_ready_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler1_SAMPLER_OUTPUT_READY_XECORE2_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE3",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE3",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler1__sampler_output_ready_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler1_SAMPLER_OUTPUT_READY_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_sampler2_SAMPLER_OUTPUT_READY_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler2_SAMPLER_OUTPUT_READY_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler2_SAMPLER_OUTPUT_READY_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler2_SAMPLER_OUTPUT_READY_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_sampler2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Sampler2";
    metric_set->symbol_name = "Sampler2";
    metric_set->hw_config_guid = "62f6959a-fdae-4cdf-b50e-e818f96d3fa5";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_sampler2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__sampler2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__sampler2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__sampler2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__sampler2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE4",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE4",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler2__sampler_output_ready_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler2_SAMPLER_OUTPUT_READY_XECORE4_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE5",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE5",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler2__sampler_output_ready_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler2_SAMPLER_OUTPUT_READY_XECORE5_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE6",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE6",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler2__sampler_output_ready_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler2_SAMPLER_OUTPUT_READY_XECORE6_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE7",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE7",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler2__sampler_output_ready_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler2_SAMPLER_OUTPUT_READY_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_sampler3_SAMPLER_OUTPUT_READY_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler3_SAMPLER_OUTPUT_READY_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler3_SAMPLER_OUTPUT_READY_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler3_SAMPLER_OUTPUT_READY_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_sampler3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Sampler3";
    metric_set->symbol_name = "Sampler3";
    metric_set->hw_config_guid = "ec2a8d38-54ef-4090-99de-4e2cc5a1892f";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_sampler3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__sampler3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__sampler3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__sampler3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__sampler3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE10",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE10",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler3__sampler_output_ready_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler3_SAMPLER_OUTPUT_READY_XECORE10_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE11",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE11",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler3__sampler_output_ready_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler3_SAMPLER_OUTPUT_READY_XECORE11_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE8",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE8",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler3__sampler_output_ready_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler3_SAMPLER_OUTPUT_READY_XECORE8_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE9",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE9",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler3__sampler_output_ready_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler3_SAMPLER_OUTPUT_READY_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_sampler4_SAMPLER_OUTPUT_READY_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler4_SAMPLER_OUTPUT_READY_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler4_SAMPLER_OUTPUT_READY_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler4_SAMPLER_OUTPUT_READY_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_sampler4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Sampler4";
    metric_set->symbol_name = "Sampler4";
    metric_set->hw_config_guid = "2a10d977-d656-464c-91a0-303aff97e4af";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_sampler4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__sampler4__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__sampler4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__sampler4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__sampler4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE12",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE12",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler4__sampler_output_ready_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler4_SAMPLER_OUTPUT_READY_XECORE12_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE13",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE13",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler4__sampler_output_ready_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler4_SAMPLER_OUTPUT_READY_XECORE13_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE14",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE14",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler4__sampler_output_ready_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler4_SAMPLER_OUTPUT_READY_XECORE14_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE15",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE15",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler4__sampler_output_ready_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler4_SAMPLER_OUTPUT_READY_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_sampler5_SAMPLER_BUSY_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler5_SAMPLER_BUSY_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler5_SAMPLER_BUSY_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler5_SAMPLER_BUSY_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler5_SAMPLER_BUSY_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler5_SAMPLER_BUSY_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler5_SAMPLER_BUSY_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler5_SAMPLER_BUSY_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler5_SAMPLER_BUSY_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler5_SAMPLER_BUSY_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler5_SAMPLER_BUSY_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler5_SAMPLER_BUSY_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler5_SAMPLER_BUSY_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler5_SAMPLER_BUSY_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler5_SAMPLER_BUSY_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler5_SAMPLER_BUSY_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_sampler5_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Sampler5";
    metric_set->symbol_name = "Sampler5";
    metric_set->hw_config_guid = "51dcfdcf-ea8c-4963-ab0b-72013e72e433";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_sampler5_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__sampler5__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__sampler5__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__sampler5__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__sampler5__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER BUSY XECORE0",
                .symbol_name = "SAMPLER_BUSY_XECORE0",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler5__sampler_busy_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler5_SAMPLER_BUSY_XECORE0_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE1",
                .symbol_name = "SAMPLER_BUSY_XECORE1",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler5__sampler_busy_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler5_SAMPLER_BUSY_XECORE1_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE10",
                .symbol_name = "SAMPLER_BUSY_XECORE10",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler5__sampler_busy_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler5_SAMPLER_BUSY_XECORE10_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE11",
                .symbol_name = "SAMPLER_BUSY_XECORE11",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler5__sampler_busy_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler5_SAMPLER_BUSY_XECORE11_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE12",
                .symbol_name = "SAMPLER_BUSY_XECORE12",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler5__sampler_busy_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler5_SAMPLER_BUSY_XECORE12_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE13",
                .symbol_name = "SAMPLER_BUSY_XECORE13",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler5__sampler_busy_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler5_SAMPLER_BUSY_XECORE13_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE14",
                .symbol_name = "SAMPLER_BUSY_XECORE14",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler5__sampler_busy_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler5_SAMPLER_BUSY_XECORE14_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE15",
                .symbol_name = "SAMPLER_BUSY_XECORE15",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler5__sampler_busy_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler5_SAMPLER_BUSY_XECORE15_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE2",
                .symbol_name = "SAMPLER_BUSY_XECORE2",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler5__sampler_busy_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler5_SAMPLER_BUSY_XECORE2_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE3",
                .symbol_name = "SAMPLER_BUSY_XECORE3",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler5__sampler_busy_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler5_SAMPLER_BUSY_XECORE3_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE4",
                .symbol_name = "SAMPLER_BUSY_XECORE4",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler5__sampler_busy_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler5_SAMPLER_BUSY_XECORE4_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE5",
                .symbol_name = "SAMPLER_BUSY_XECORE5",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler5__sampler_busy_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler5_SAMPLER_BUSY_XECORE5_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE6",
                .symbol_name = "SAMPLER_BUSY_XECORE6",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler5__sampler_busy_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler5_SAMPLER_BUSY_XECORE6_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE7",
                .symbol_name = "SAMPLER_BUSY_XECORE7",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler5__sampler_busy_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler5_SAMPLER_BUSY_XECORE7_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE8",
                .symbol_name = "SAMPLER_BUSY_XECORE8",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler5__sampler_busy_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler5_SAMPLER_BUSY_XECORE8_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE9",
                .symbol_name = "SAMPLER_BUSY_XECORE9",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler5__sampler_busy_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler5_SAMPLER_BUSY_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_sampler6_SAMPLER_MEMORY_LATENCY_STALL_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler6_SAMPLER_MEMORY_LATENCY_STALL_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler6_SAMPLER_MEMORY_LATENCY_STALL_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler6_SAMPLER_MEMORY_LATENCY_STALL_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler6_SAMPLER_MEMORY_LATENCY_STALL_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler6_SAMPLER_MEMORY_LATENCY_STALL_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler6_SAMPLER_MEMORY_LATENCY_STALL_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler6_SAMPLER_MEMORY_LATENCY_STALL_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_sampler6_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Sampler6";
    metric_set->symbol_name = "Sampler6";
    metric_set->hw_config_guid = "8203850e-45ae-4f59-81be-45f721f5406a";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_sampler6_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__sampler6__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__sampler6__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__sampler6__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__sampler6__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE0",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE0",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler6__sampler_memory_latency_stall_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler6_SAMPLER_MEMORY_LATENCY_STALL_XECORE0_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE1",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE1",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler6__sampler_memory_latency_stall_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler6_SAMPLER_MEMORY_LATENCY_STALL_XECORE1_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE2",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE2",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler6__sampler_memory_latency_stall_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler6_SAMPLER_MEMORY_LATENCY_STALL_XECORE2_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE3",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE3",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler6__sampler_memory_latency_stall_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler6_SAMPLER_MEMORY_LATENCY_STALL_XECORE3_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE4",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE4",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler6__sampler_memory_latency_stall_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler6_SAMPLER_MEMORY_LATENCY_STALL_XECORE4_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE5",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE5",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler6__sampler_memory_latency_stall_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler6_SAMPLER_MEMORY_LATENCY_STALL_XECORE5_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE6",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE6",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler6__sampler_memory_latency_stall_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler6_SAMPLER_MEMORY_LATENCY_STALL_XECORE6_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE7",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE7",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler6__sampler_memory_latency_stall_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler6_SAMPLER_MEMORY_LATENCY_STALL_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_sampler7_SAMPLER_MEMORY_LATENCY_STALL_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler7_SAMPLER_MEMORY_LATENCY_STALL_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler7_SAMPLER_MEMORY_LATENCY_STALL_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler7_SAMPLER_MEMORY_LATENCY_STALL_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler7_SAMPLER_MEMORY_LATENCY_STALL_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler7_SAMPLER_MEMORY_LATENCY_STALL_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler7_SAMPLER_MEMORY_LATENCY_STALL_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler7_SAMPLER_MEMORY_LATENCY_STALL_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_sampler7_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Sampler7";
    metric_set->symbol_name = "Sampler7";
    metric_set->hw_config_guid = "3e6e7ddd-572c-4628-94a2-b8a8385fc7b0";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_sampler7_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__sampler7__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__sampler7__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__sampler7__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__sampler7__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE10",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE10",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler7__sampler_memory_latency_stall_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler7_SAMPLER_MEMORY_LATENCY_STALL_XECORE10_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE11",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE11",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler7__sampler_memory_latency_stall_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler7_SAMPLER_MEMORY_LATENCY_STALL_XECORE11_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE12",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE12",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler7__sampler_memory_latency_stall_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler7_SAMPLER_MEMORY_LATENCY_STALL_XECORE12_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE13",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE13",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler7__sampler_memory_latency_stall_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler7_SAMPLER_MEMORY_LATENCY_STALL_XECORE13_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE14",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE14",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler7__sampler_memory_latency_stall_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler7_SAMPLER_MEMORY_LATENCY_STALL_XECORE14_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE15",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE15",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler7__sampler_memory_latency_stall_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler7_SAMPLER_MEMORY_LATENCY_STALL_XECORE15_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE8",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE8",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler7__sampler_memory_latency_stall_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler7_SAMPLER_MEMORY_LATENCY_STALL_XECORE8_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE9",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE9",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler7__sampler_memory_latency_stall_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler7_SAMPLER_MEMORY_LATENCY_STALL_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_sampler8_SAMPLER_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler8_SAMPLER_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler8_SAMPLER_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler8_SAMPLER_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler8_SAMPLER_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler8_SAMPLER_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler8_SAMPLER_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler8_SAMPLER_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_sampler8_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Sampler8";
    metric_set->symbol_name = "Sampler8";
    metric_set->hw_config_guid = "5683991d-228c-41e5-812b-98bc82e244b2";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_sampler8_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__sampler8__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__sampler8__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__sampler8__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__sampler8__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE0",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler8__sampler_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler8_SAMPLER_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE1",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler8__sampler_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler8_SAMPLER_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE2",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler8__sampler_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler8_SAMPLER_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE3",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler8__sampler_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler8_SAMPLER_INPUT_AVAILABLE_XECORE3_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE4",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler8__sampler_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler8_SAMPLER_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE5",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler8__sampler_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler8_SAMPLER_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE6",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler8__sampler_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler8_SAMPLER_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE7",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler8__sampler_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler8_SAMPLER_INPUT_AVAILABLE_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_sampler9_SAMPLER_INPUT_AVAILABLE_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler9_SAMPLER_INPUT_AVAILABLE_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler9_SAMPLER_INPUT_AVAILABLE_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler9_SAMPLER_INPUT_AVAILABLE_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler9_SAMPLER_INPUT_AVAILABLE_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler9_SAMPLER_INPUT_AVAILABLE_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler9_SAMPLER_INPUT_AVAILABLE_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler9_SAMPLER_INPUT_AVAILABLE_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_sampler9_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Sampler9";
    metric_set->symbol_name = "Sampler9";
    metric_set->hw_config_guid = "2c897818-565a-4753-a1f6-8f81529b2447";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_sampler9_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__sampler9__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__sampler9__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__sampler9__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__sampler9__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE10",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE10",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler9__sampler_input_available_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler9_SAMPLER_INPUT_AVAILABLE_XECORE10_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE11",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE11",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler9__sampler_input_available_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler9_SAMPLER_INPUT_AVAILABLE_XECORE11_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE12",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE12",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler9__sampler_input_available_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler9_SAMPLER_INPUT_AVAILABLE_XECORE12_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE13",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE13",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler9__sampler_input_available_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler9_SAMPLER_INPUT_AVAILABLE_XECORE13_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE14",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE14",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler9__sampler_input_available_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler9_SAMPLER_INPUT_AVAILABLE_XECORE14_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE15",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE15",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler9__sampler_input_available_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler9_SAMPLER_INPUT_AVAILABLE_XECORE15_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE8",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE8",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler9__sampler_input_available_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler9_SAMPLER_INPUT_AVAILABLE_XECORE8_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE9",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE9",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__sampler9__sampler_input_available_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt2_sampler9_SAMPLER_INPUT_AVAILABLE_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_sampler10_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Sampler10";
    metric_set->symbol_name = "Sampler10";
    metric_set->hw_config_guid = "f74b6a50-22da-4c0e-b621-c0627525e511";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_sampler10_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__sampler10__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__sampler10__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__sampler10__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__sampler10__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE0",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE0",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler10__sampler_texture_cache_access_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE0_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE1",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE1",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler10__sampler_texture_cache_access_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE1_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE10",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE10",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler10__sampler_texture_cache_access_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE10_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE11",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE11",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler10__sampler_texture_cache_access_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE11_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE12",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE12",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler10__sampler_texture_cache_access_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE12_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE13",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE13",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler10__sampler_texture_cache_access_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE13_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE14",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE14",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler10__sampler_texture_cache_access_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE14_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE15",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE15",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler10__sampler_texture_cache_access_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE15_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE2",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE2",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler10__sampler_texture_cache_access_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE2_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE3",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE3",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler10__sampler_texture_cache_access_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE3_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE4",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE4",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler10__sampler_texture_cache_access_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE4_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE5",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE5",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler10__sampler_texture_cache_access_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE5_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE6",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE6",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler10__sampler_texture_cache_access_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE6_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE7",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE7",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler10__sampler_texture_cache_access_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE7_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE8",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE8",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler10__sampler_texture_cache_access_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE8_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE9",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE9",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler10__sampler_texture_cache_access_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler10_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_sampler11_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Sampler11";
    metric_set->symbol_name = "Sampler11";
    metric_set->hw_config_guid = "6edeb7d7-a21c-4d06-bd66-dd804480f1f1";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_sampler11_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__sampler11__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__sampler11__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__sampler11__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__sampler11__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE0",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE0",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler11__sampler_texture_cache_miss_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE0_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE1",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE1",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler11__sampler_texture_cache_miss_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE1_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE10",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE10",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler11__sampler_texture_cache_miss_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE10_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE11",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE11",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler11__sampler_texture_cache_miss_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE11_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE12",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE12",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler11__sampler_texture_cache_miss_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE12_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE13",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE13",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler11__sampler_texture_cache_miss_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE13_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE14",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE14",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler11__sampler_texture_cache_miss_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE14_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE15",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE15",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler11__sampler_texture_cache_miss_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE15_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE2",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE2",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler11__sampler_texture_cache_miss_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE2_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE3",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE3",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler11__sampler_texture_cache_miss_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE3_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE4",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE4",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler11__sampler_texture_cache_miss_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE4_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE5",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE5",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler11__sampler_texture_cache_miss_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE5_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE6",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE6",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler11__sampler_texture_cache_miss_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE6_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE7",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE7",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler11__sampler_texture_cache_miss_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE7_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE8",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE8",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler11__sampler_texture_cache_miss_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE8_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE9",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE9",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__sampler11__sampler_texture_cache_miss_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt2_sampler11_SAMPLER_TEXTURE_CACHE_MISS_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_thread_dispatcher1_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher1_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher1_GPGPU_THREADGROUP_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher1";
    metric_set->symbol_name = "ThreadDispatcher1";
    metric_set->hw_config_guid = "7d691d4b-febf-415b-8d1b-1d623e936c19";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE4",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE4",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher1__async_gpgpu_threadgroup_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher1_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE4_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE8",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE8",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher1__async_gpgpu_thread_exit_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher1_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE8_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE0",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE0",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher1__gpgpu_threadgroup_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher1_GPGPU_THREADGROUP_COUNT_XECORE0_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher2_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher2_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher2_GPGPU_THREADGROUP_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher2";
    metric_set->symbol_name = "ThreadDispatcher2";
    metric_set->hw_config_guid = "04737515-c210-40b6-90b0-2ad6ce51ff72";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE5",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE5",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher2__async_gpgpu_threadgroup_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher2_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE5_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE9",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE9",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher2__async_gpgpu_thread_exit_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher2_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE9_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE1",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE1",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher2__gpgpu_threadgroup_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher2_GPGPU_THREADGROUP_COUNT_XECORE1_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher3_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher3_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher3_GPGPU_THREADGROUP_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher3";
    metric_set->symbol_name = "ThreadDispatcher3";
    metric_set->hw_config_guid = "6215b3ed-0c9a-4171-b8bc-035be8e8b140";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE6",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE6",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher3__async_gpgpu_threadgroup_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher3_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE6_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE10",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE10",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher3__async_gpgpu_thread_exit_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher3_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE10_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE2",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE2",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher3__gpgpu_threadgroup_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher3_GPGPU_THREADGROUP_COUNT_XECORE2_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher4_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher4_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher4_GPGPU_THREADGROUP_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher4";
    metric_set->symbol_name = "ThreadDispatcher4";
    metric_set->hw_config_guid = "cf7b0026-fbed-4f29-ab6a-0f6acbea337b";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE7",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE7",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher4__async_gpgpu_threadgroup_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher4_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE7_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE11",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE11",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher4__async_gpgpu_thread_exit_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher4_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE11_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher4__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE3",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE3",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher4__gpgpu_threadgroup_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher4_GPGPU_THREADGROUP_COUNT_XECORE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher5_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher5_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher5_GPGPU_THREADGROUP_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher5_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher5";
    metric_set->symbol_name = "ThreadDispatcher5";
    metric_set->hw_config_guid = "9fcfbc28-caaf-44ea-84a5-f1c5c2341b2a";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher5_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE8",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE8",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher5__async_gpgpu_threadgroup_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher5_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE8_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE12",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE12",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher5__async_gpgpu_thread_exit_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher5_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE12_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher5__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher5__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE4",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE4",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher5__gpgpu_threadgroup_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher5_GPGPU_THREADGROUP_COUNT_XECORE4_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher5__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher5__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher6_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher6_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher6_GPGPU_THREADGROUP_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher6_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher6";
    metric_set->symbol_name = "ThreadDispatcher6";
    metric_set->hw_config_guid = "c0af81b4-8172-4e9c-8da2-5051e5817de6";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher6_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE9",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE9",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher6__async_gpgpu_threadgroup_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher6_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE9_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE13",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE13",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher6__async_gpgpu_thread_exit_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher6_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE13_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher6__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher6__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE5",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE5",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher6__gpgpu_threadgroup_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher6_GPGPU_THREADGROUP_COUNT_XECORE5_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher6__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher6__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher7_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher7_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher7_GPGPU_THREADGROUP_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher7_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher7";
    metric_set->symbol_name = "ThreadDispatcher7";
    metric_set->hw_config_guid = "74538036-2ddc-486d-914c-ffe5d3ce6cfb";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher7_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE10",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE10",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher7__async_gpgpu_threadgroup_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher7_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE10_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE14",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE14",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher7__async_gpgpu_thread_exit_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher7_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE14_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher7__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher7__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE6",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE6",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher7__gpgpu_threadgroup_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher7_GPGPU_THREADGROUP_COUNT_XECORE6_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher7__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher7__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher8_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher8_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher8_GPGPU_THREADGROUP_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher8_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher8";
    metric_set->symbol_name = "ThreadDispatcher8";
    metric_set->hw_config_guid = "558bd2fd-a7f4-41e5-9ef6-1d529263bcd2";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher8_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE11",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE11",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher8__async_gpgpu_threadgroup_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher8_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE11_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE15",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE15",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher8__async_gpgpu_thread_exit_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher8_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE15_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher8__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher8__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE7",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE7",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher8__gpgpu_threadgroup_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher8_GPGPU_THREADGROUP_COUNT_XECORE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher8__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher8__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher9_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher9_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher9_GPGPU_THREADGROUP_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher9_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher9";
    metric_set->symbol_name = "ThreadDispatcher9";
    metric_set->hw_config_guid = "ac68b4c3-f63a-4dd8-855e-d3fd781a8bde";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher9_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE12",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE12",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher9__async_gpgpu_threadgroup_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher9_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE12_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE0",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE0",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher9__async_gpgpu_thread_exit_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher9_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE0_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher9__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher9__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE8",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE8",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher9__gpgpu_threadgroup_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher9_GPGPU_THREADGROUP_COUNT_XECORE8_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher9__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher9__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher10_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher10_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher10_GPGPU_THREADGROUP_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher10_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher10";
    metric_set->symbol_name = "ThreadDispatcher10";
    metric_set->hw_config_guid = "b969747f-2450-4725-899f-5d0701930ea7";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher10_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE13",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE13",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher10__async_gpgpu_threadgroup_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher10_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE13_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE1",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE1",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher10__async_gpgpu_thread_exit_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher10_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE1_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher10__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher10__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE9",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE9",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher10__gpgpu_threadgroup_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher10_GPGPU_THREADGROUP_COUNT_XECORE9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher10__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher10__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher11_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher11_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher11_GPGPU_THREADGROUP_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher11_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher11";
    metric_set->symbol_name = "ThreadDispatcher11";
    metric_set->hw_config_guid = "b2e80bd3-d852-4c07-86e0-520c90236acf";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher11_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE14",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE14",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher11__async_gpgpu_threadgroup_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher11_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE14_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE2",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE2",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher11__async_gpgpu_thread_exit_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher11_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE2_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher11__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher11__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE10",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE10",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher11__gpgpu_threadgroup_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher11_GPGPU_THREADGROUP_COUNT_XECORE10_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher11__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher11__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher12_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher12_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher12_GPGPU_THREADGROUP_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher12_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher12";
    metric_set->symbol_name = "ThreadDispatcher12";
    metric_set->hw_config_guid = "5622d707-7646-48bc-90e0-af17a55ab1c7";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher12_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE15",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE15",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher12__async_gpgpu_threadgroup_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher12_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE15_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE3",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE3",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher12__async_gpgpu_thread_exit_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher12_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE3_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher12__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher12__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE11",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE11",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher12__gpgpu_threadgroup_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher12_GPGPU_THREADGROUP_COUNT_XECORE11_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher12__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher12__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher13_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher13_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher13_GPGPU_THREADGROUP_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher13_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher13";
    metric_set->symbol_name = "ThreadDispatcher13";
    metric_set->hw_config_guid = "6149c8e0-84f6-4643-ac19-0f5b5a8fa830";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher13_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE0",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE0",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher13__async_gpgpu_threadgroup_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher13_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE0_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE4",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE4",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher13__async_gpgpu_thread_exit_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher13_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE4_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher13__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher13__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE12",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE12",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher13__gpgpu_threadgroup_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher13_GPGPU_THREADGROUP_COUNT_XECORE12_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher13__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher13__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher14_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher14_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher14_GPGPU_THREADGROUP_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher14_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher14";
    metric_set->symbol_name = "ThreadDispatcher14";
    metric_set->hw_config_guid = "3ad2842e-a192-4cb9-aca4-c3dfa9238070";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher14_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE1",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE1",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher14__async_gpgpu_threadgroup_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher14_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE1_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE5",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE5",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher14__async_gpgpu_thread_exit_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher14_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE5_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher14__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher14__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE13",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE13",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher14__gpgpu_threadgroup_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher14_GPGPU_THREADGROUP_COUNT_XECORE13_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher14__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher14__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher15_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher15_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher15_GPGPU_THREADGROUP_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher15_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher15";
    metric_set->symbol_name = "ThreadDispatcher15";
    metric_set->hw_config_guid = "a8b90aef-99fa-443f-8e74-06489d14a031";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher15_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE2",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE2",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher15__async_gpgpu_threadgroup_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher15_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE2_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE6",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE6",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher15__async_gpgpu_thread_exit_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher15_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE6_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher15__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher15__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE14",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE14",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher15__gpgpu_threadgroup_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher15_GPGPU_THREADGROUP_COUNT_XECORE14_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher15__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher15__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher16_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher16_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher16_GPGPU_THREADGROUP_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher16_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher16";
    metric_set->symbol_name = "ThreadDispatcher16";
    metric_set->hw_config_guid = "3c5182e0-c1f6-4e9a-b5a6-752052f23389";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher16_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE3",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE3",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher16__async_gpgpu_threadgroup_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher16_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE3_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE7",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE7",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher16__async_gpgpu_thread_exit_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher16_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE7_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher16__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher16__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE15",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE15",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher16__gpgpu_threadgroup_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher16_GPGPU_THREADGROUP_COUNT_XECORE15_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher16__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher16__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher17_TASK_THREADGROUP_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher17_TASK_THREAD_EXIT_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher17_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher17_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher17";
    metric_set->symbol_name = "ThreadDispatcher17";
    metric_set->hw_config_guid = "72a4eaf8-b31d-4749-85e9-d6670ecfda25";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher17_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher17__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher17__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher17__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher17__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE0",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE0",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher17__task_threadgroup_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher17_TASK_THREADGROUP_COUNT_XECORE0_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE4",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE4",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher17__task_thread_exit_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher17_TASK_THREAD_EXIT_COUNT_XECORE4_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE8",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE8",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher17__threadgroup_dispatch_resource_stall_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher17_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE8_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher18_TASK_THREADGROUP_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher18_TASK_THREAD_EXIT_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher18_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher18_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher18";
    metric_set->symbol_name = "ThreadDispatcher18";
    metric_set->hw_config_guid = "2b0b4fde-719b-49de-a309-aeb1f96e2f6b";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher18_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher18__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher18__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher18__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher18__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE1",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE1",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher18__task_threadgroup_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher18_TASK_THREADGROUP_COUNT_XECORE1_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE5",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE5",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher18__task_thread_exit_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher18_TASK_THREAD_EXIT_COUNT_XECORE5_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE9",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE9",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher18__threadgroup_dispatch_resource_stall_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher18_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher19_TASK_THREADGROUP_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher19_TASK_THREAD_EXIT_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher19_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher19_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher19";
    metric_set->symbol_name = "ThreadDispatcher19";
    metric_set->hw_config_guid = "d25f6c66-eb80-49f5-ba95-74e5bbeffba8";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher19_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher19__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher19__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher19__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher19__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE2",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE2",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher19__task_threadgroup_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher19_TASK_THREADGROUP_COUNT_XECORE2_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE6",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE6",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher19__task_thread_exit_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher19_TASK_THREAD_EXIT_COUNT_XECORE6_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE10",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE10",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher19__threadgroup_dispatch_resource_stall_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher19_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE10_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher20_TASK_THREADGROUP_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher20_TASK_THREAD_EXIT_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher20_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher20_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher20";
    metric_set->symbol_name = "ThreadDispatcher20";
    metric_set->hw_config_guid = "9decfc7a-90a5-4e0c-8f20-be21a3e00e2b";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher20_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher20__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher20__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher20__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher20__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE3",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE3",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher20__task_threadgroup_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher20_TASK_THREADGROUP_COUNT_XECORE3_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE7",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE7",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher20__task_thread_exit_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher20_TASK_THREAD_EXIT_COUNT_XECORE7_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE11",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE11",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher20__threadgroup_dispatch_resource_stall_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher20_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher21_TASK_THREADGROUP_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher21_TASK_THREAD_EXIT_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher21_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher21_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher21";
    metric_set->symbol_name = "ThreadDispatcher21";
    metric_set->hw_config_guid = "f2099f1b-7280-4175-b2a9-a373b7039027";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher21_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher21__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher21__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher21__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher21__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE4",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE4",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher21__task_threadgroup_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher21_TASK_THREADGROUP_COUNT_XECORE4_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE8",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE8",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher21__task_thread_exit_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher21_TASK_THREAD_EXIT_COUNT_XECORE8_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE12",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE12",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher21__threadgroup_dispatch_resource_stall_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher21_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE12_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher22_TASK_THREADGROUP_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher22_TASK_THREAD_EXIT_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher22_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher22_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher22";
    metric_set->symbol_name = "ThreadDispatcher22";
    metric_set->hw_config_guid = "1be88735-2a46-4564-84f3-0c832cd05571";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher22_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher22__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher22__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher22__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher22__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE5",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE5",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher22__task_threadgroup_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher22_TASK_THREADGROUP_COUNT_XECORE5_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE9",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE9",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher22__task_thread_exit_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher22_TASK_THREAD_EXIT_COUNT_XECORE9_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE13",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE13",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher22__threadgroup_dispatch_resource_stall_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher22_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher23_TASK_THREADGROUP_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher23_TASK_THREAD_EXIT_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher23_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher23_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher23";
    metric_set->symbol_name = "ThreadDispatcher23";
    metric_set->hw_config_guid = "71d12693-64c0-4da1-8f5e-fdaf00bcf83e";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher23_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher23__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher23__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher23__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher23__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE6",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE6",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher23__task_threadgroup_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher23_TASK_THREADGROUP_COUNT_XECORE6_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE10",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE10",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher23__task_thread_exit_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher23_TASK_THREAD_EXIT_COUNT_XECORE10_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE14",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE14",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher23__threadgroup_dispatch_resource_stall_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher23_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE14_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher24_TASK_THREADGROUP_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher24_TASK_THREAD_EXIT_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher24_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher24_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher24";
    metric_set->symbol_name = "ThreadDispatcher24";
    metric_set->hw_config_guid = "6ad141b6-faae-40da-bdf4-02247ec1121c";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher24_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher24__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher24__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher24__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher24__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE7",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE7",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher24__task_threadgroup_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher24_TASK_THREADGROUP_COUNT_XECORE7_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE11",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE11",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher24__task_thread_exit_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher24_TASK_THREAD_EXIT_COUNT_XECORE11_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE15",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE15",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher24__threadgroup_dispatch_resource_stall_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher24_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher25_TASK_THREADGROUP_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher25_TASK_THREAD_EXIT_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher25_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher25_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher25";
    metric_set->symbol_name = "ThreadDispatcher25";
    metric_set->hw_config_guid = "74433d30-ffa1-410d-8c87-7cee0acfe4ea";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher25_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher25__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher25__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher25__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher25__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE8",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE8",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher25__task_threadgroup_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher25_TASK_THREADGROUP_COUNT_XECORE8_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE12",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE12",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher25__task_thread_exit_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher25_TASK_THREAD_EXIT_COUNT_XECORE12_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE0",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE0",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher25__threadgroup_dispatch_resource_stall_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher25_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher26_TASK_THREADGROUP_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher26_TASK_THREAD_EXIT_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher26_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher26_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher26";
    metric_set->symbol_name = "ThreadDispatcher26";
    metric_set->hw_config_guid = "5ba834b3-4603-4c43-94da-6e1bacf9500a";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher26_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher26__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher26__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher26__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher26__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE9",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE9",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher26__task_threadgroup_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher26_TASK_THREADGROUP_COUNT_XECORE9_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE13",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE13",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher26__task_thread_exit_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher26_TASK_THREAD_EXIT_COUNT_XECORE13_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE1",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE1",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher26__threadgroup_dispatch_resource_stall_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher26_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher27_TASK_THREADGROUP_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher27_TASK_THREAD_EXIT_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher27_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher27_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher27";
    metric_set->symbol_name = "ThreadDispatcher27";
    metric_set->hw_config_guid = "dcfd59c3-e7b0-402e-a656-ca2a2f2d95dd";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher27_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher27__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher27__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher27__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher27__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE10",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE10",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher27__task_threadgroup_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher27_TASK_THREADGROUP_COUNT_XECORE10_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE14",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE14",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher27__task_thread_exit_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher27_TASK_THREAD_EXIT_COUNT_XECORE14_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE2",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE2",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher27__threadgroup_dispatch_resource_stall_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher27_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher28_TASK_THREADGROUP_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher28_TASK_THREAD_EXIT_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher28_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher28_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher28";
    metric_set->symbol_name = "ThreadDispatcher28";
    metric_set->hw_config_guid = "f4a8f90b-7b27-40e1-9015-6b2b3c60920a";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher28_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher28__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher28__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher28__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher28__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE11",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE11",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher28__task_threadgroup_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher28_TASK_THREADGROUP_COUNT_XECORE11_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE15",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE15",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher28__task_thread_exit_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher28_TASK_THREAD_EXIT_COUNT_XECORE15_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE3",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE3",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher28__threadgroup_dispatch_resource_stall_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher28_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher29_TASK_THREADGROUP_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher29_TASK_THREAD_EXIT_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher29_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher29_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher29";
    metric_set->symbol_name = "ThreadDispatcher29";
    metric_set->hw_config_guid = "e3476c20-6530-4dfe-bbcd-f98065ce0702";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher29_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher29__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher29__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher29__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher29__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE12",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE12",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher29__task_threadgroup_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher29_TASK_THREADGROUP_COUNT_XECORE12_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE0",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE0",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher29__task_thread_exit_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher29_TASK_THREAD_EXIT_COUNT_XECORE0_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE4",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE4",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher29__threadgroup_dispatch_resource_stall_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher29_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher30_TASK_THREADGROUP_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher30_TASK_THREAD_EXIT_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher30_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher30_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher30";
    metric_set->symbol_name = "ThreadDispatcher30";
    metric_set->hw_config_guid = "235cf07d-fa5f-48bf-8906-f089284a77c0";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher30_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher30__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher30__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher30__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher30__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE13",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE13",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher30__task_threadgroup_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher30_TASK_THREADGROUP_COUNT_XECORE13_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE1",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE1",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher30__task_thread_exit_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher30_TASK_THREAD_EXIT_COUNT_XECORE1_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE5",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE5",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher30__threadgroup_dispatch_resource_stall_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher30_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher31_TASK_THREADGROUP_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher31_TASK_THREAD_EXIT_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher31_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher31_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher31";
    metric_set->symbol_name = "ThreadDispatcher31";
    metric_set->hw_config_guid = "60f202e0-3078-4cee-bb6c-7b579827b501";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher31_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher31__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher31__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher31__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher31__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE14",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE14",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher31__task_threadgroup_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher31_TASK_THREADGROUP_COUNT_XECORE14_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE2",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE2",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher31__task_thread_exit_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher31_TASK_THREAD_EXIT_COUNT_XECORE2_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE6",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE6",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher31__threadgroup_dispatch_resource_stall_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher31_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher32_TASK_THREADGROUP_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher32_TASK_THREAD_EXIT_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher32_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher32_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher32";
    metric_set->symbol_name = "ThreadDispatcher32";
    metric_set->hw_config_guid = "68400a0d-dffd-4787-a1f3-7385e2f2f39a";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher32_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher32__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher32__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher32__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher32__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE15",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE15",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher32__task_threadgroup_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher32_TASK_THREADGROUP_COUNT_XECORE15_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE3",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE3",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher32__task_thread_exit_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher32_TASK_THREAD_EXIT_COUNT_XECORE3_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE7",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE7",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher32__threadgroup_dispatch_resource_stall_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher32_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher33_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher33";
    metric_set->symbol_name = "ThreadDispatcher33";
    metric_set->hw_config_guid = "c0fb4de2-f14e-4576-b7b4-b564a6d1eccf";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher33_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher33__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher33__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher33__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher33__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE0",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE1",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE10",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE10",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE10_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE11",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE11",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE11_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE12",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE12",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE12_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE13",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE13",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE13_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE14",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE14",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE14_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE15",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE15",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE15_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE2",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE3",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE3_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE4",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE5",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE6",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE7",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE7_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE8",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE8",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE8_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE9",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE9",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher33_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher34_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher34";
    metric_set->symbol_name = "ThreadDispatcher34";
    metric_set->hw_config_guid = "ebaac92d-ede4-44be-b0d8-d3a292f1c696";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher34_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher34__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher34__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher34__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher34__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE0",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE1",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE10",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE10",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE10_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE11",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE11",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE11_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE12",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE12",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE12_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE13",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE13",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE13_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE14",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE14",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE14_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE15",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE15",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE15_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE2",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE3",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE3_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE4",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE5",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE6",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE7",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE7_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE8",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE8",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE8_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE9",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE9",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher34_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_thread_dispatcher35_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher35_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher35_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher35_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher35_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher35_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher35_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher35_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher35_THREAD_DISPATCH_STALL_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher35_THREAD_DISPATCH_STALL_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher35_THREAD_DISPATCH_STALL_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher35_THREAD_DISPATCH_STALL_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher35_THREAD_DISPATCH_STALL_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher35_THREAD_DISPATCH_STALL_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher35_THREAD_DISPATCH_STALL_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher35_THREAD_DISPATCH_STALL_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher35_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher35";
    metric_set->symbol_name = "ThreadDispatcher35";
    metric_set->hw_config_guid = "310c4352-616a-4995-a8ca-dc1b0b4083e2";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher35_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher35__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher35__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher35__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher35__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE0",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE0",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher35__thread_dispatch_queue0_active_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher35_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE0_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE1",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE1",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher35__thread_dispatch_queue0_active_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher35_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE1_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE2",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE2",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher35__thread_dispatch_queue0_active_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher35_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE2_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE3",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE3",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher35__thread_dispatch_queue0_active_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher35_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE3_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE4",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE4",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher35__thread_dispatch_queue0_active_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher35_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE4_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE5",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE5",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher35__thread_dispatch_queue0_active_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher35_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE5_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE6",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE6",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher35__thread_dispatch_queue0_active_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher35_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE6_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE7",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE7",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher35__thread_dispatch_queue0_active_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher35_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE7_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE0",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE0",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher35__thread_dispatch_stall_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher35_THREAD_DISPATCH_STALL_XECORE0_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE1",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE1",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher35__thread_dispatch_stall_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher35_THREAD_DISPATCH_STALL_XECORE1_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE2",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE2",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher35__thread_dispatch_stall_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher35_THREAD_DISPATCH_STALL_XECORE2_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE3",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE3",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher35__thread_dispatch_stall_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher35_THREAD_DISPATCH_STALL_XECORE3_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE4",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE4",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher35__thread_dispatch_stall_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher35_THREAD_DISPATCH_STALL_XECORE4_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE5",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE5",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher35__thread_dispatch_stall_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher35_THREAD_DISPATCH_STALL_XECORE5_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE6",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE6",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher35__thread_dispatch_stall_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher35_THREAD_DISPATCH_STALL_XECORE6_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE7",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE7",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher35__thread_dispatch_stall_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher35_THREAD_DISPATCH_STALL_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_thread_dispatcher36_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher36_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher36_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher36_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher36_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher36_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher36_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher36_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher36_THREAD_DISPATCH_STALL_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher36_THREAD_DISPATCH_STALL_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher36_THREAD_DISPATCH_STALL_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher36_THREAD_DISPATCH_STALL_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher36_THREAD_DISPATCH_STALL_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher36_THREAD_DISPATCH_STALL_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher36_THREAD_DISPATCH_STALL_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher36_THREAD_DISPATCH_STALL_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher36_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher36";
    metric_set->symbol_name = "ThreadDispatcher36";
    metric_set->hw_config_guid = "70244132-9e7c-42e1-ad19-14b16fd415ac";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher36_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher36__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher36__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher36__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher36__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE10",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE10",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher36__thread_dispatch_queue0_active_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher36_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE10_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE11",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE11",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher36__thread_dispatch_queue0_active_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher36_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE11_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE12",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE12",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher36__thread_dispatch_queue0_active_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher36_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE12_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE13",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE13",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher36__thread_dispatch_queue0_active_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher36_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE13_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE14",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE14",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher36__thread_dispatch_queue0_active_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher36_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE14_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE15",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE15",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher36__thread_dispatch_queue0_active_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher36_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE15_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE8",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE8",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher36__thread_dispatch_queue0_active_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher36_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE8_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE9",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE9",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher36__thread_dispatch_queue0_active_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher36_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE9_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE10",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE10",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher36__thread_dispatch_stall_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher36_THREAD_DISPATCH_STALL_XECORE10_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE11",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE11",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher36__thread_dispatch_stall_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher36_THREAD_DISPATCH_STALL_XECORE11_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE12",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE12",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher36__thread_dispatch_stall_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher36_THREAD_DISPATCH_STALL_XECORE12_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE13",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE13",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher36__thread_dispatch_stall_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher36_THREAD_DISPATCH_STALL_XECORE13_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE14",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE14",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher36__thread_dispatch_stall_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher36_THREAD_DISPATCH_STALL_XECORE14_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE15",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE15",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher36__thread_dispatch_stall_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher36_THREAD_DISPATCH_STALL_XECORE15_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE8",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE8",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher36__thread_dispatch_stall_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher36_THREAD_DISPATCH_STALL_XECORE8_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE9",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE9",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher36__thread_dispatch_stall_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher36_THREAD_DISPATCH_STALL_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_thread_dispatcher37_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher37_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher37_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher37_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher37_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher37_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher37_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher37_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher37_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher37_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher37_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher37_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher37_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher37_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher37_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher37_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher37_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher37";
    metric_set->symbol_name = "ThreadDispatcher37";
    metric_set->hw_config_guid = "c7d9ebf5-268e-4377-852d-0dd8eb89151f";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher37_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher37__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher37__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher37__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher37__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE0",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher37__thread_dispatch_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher37_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE1",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher37__thread_dispatch_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher37_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE2",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher37__thread_dispatch_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher37_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE3",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher37__thread_dispatch_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher37_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE3_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE4",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher37__thread_dispatch_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher37_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE5",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher37__thread_dispatch_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher37_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE6",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher37__thread_dispatch_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher37_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE7",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher37__thread_dispatch_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher37_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE7_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE0",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE0",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher37__thread_dispatch_queue1_active_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher37_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE0_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE1",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE1",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher37__thread_dispatch_queue1_active_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher37_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE1_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE2",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE2",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher37__thread_dispatch_queue1_active_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher37_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE2_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE3",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE3",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher37__thread_dispatch_queue1_active_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher37_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE3_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE4",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE4",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher37__thread_dispatch_queue1_active_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher37_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE4_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE5",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE5",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher37__thread_dispatch_queue1_active_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher37_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE5_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE6",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE6",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher37__thread_dispatch_queue1_active_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher37_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE6_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE7",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE7",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher37__thread_dispatch_queue1_active_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher37_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_thread_dispatcher38_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher38_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher38_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher38_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher38_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher38_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher38_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher38_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher38_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher38_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher38_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher38_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher38_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher38_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher38_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher38_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher38_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher38";
    metric_set->symbol_name = "ThreadDispatcher38";
    metric_set->hw_config_guid = "b7b02568-d2ce-40b8-bcbb-4ecc07ff731e";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher38_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher38__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher38__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher38__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher38__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE10",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE10",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher38__thread_dispatch_input_available_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher38_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE10_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE11",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE11",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher38__thread_dispatch_input_available_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher38_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE11_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE12",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE12",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher38__thread_dispatch_input_available_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher38_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE12_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE13",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE13",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher38__thread_dispatch_input_available_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher38_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE13_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE14",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE14",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher38__thread_dispatch_input_available_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher38_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE14_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE15",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE15",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher38__thread_dispatch_input_available_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher38_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE15_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE8",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE8",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher38__thread_dispatch_input_available_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher38_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE8_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE9",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE9",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher38__thread_dispatch_input_available_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher38_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE9_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE10",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE10",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher38__thread_dispatch_queue1_active_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher38_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE10_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE11",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE11",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher38__thread_dispatch_queue1_active_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher38_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE11_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE12",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE12",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher38__thread_dispatch_queue1_active_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher38_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE12_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE13",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE13",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher38__thread_dispatch_queue1_active_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher38_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE13_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE14",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE14",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher38__thread_dispatch_queue1_active_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher38_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE14_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE15",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE15",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher38__thread_dispatch_queue1_active_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher38_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE15_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE8",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE8",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher38__thread_dispatch_queue1_active_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher38_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE8_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE9",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE9",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher38__thread_dispatch_queue1_active_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher38_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_thread_dispatcher39_THREAD_DISPATCH_PS_ACTIVE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher39_THREAD_DISPATCH_PS_ACTIVE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher39_THREAD_DISPATCH_PS_ACTIVE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher39_THREAD_DISPATCH_PS_ACTIVE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher39_THREAD_DISPATCH_PS_ACTIVE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher39_THREAD_DISPATCH_PS_ACTIVE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher39_THREAD_DISPATCH_PS_ACTIVE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher39_THREAD_DISPATCH_PS_ACTIVE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher39_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher39";
    metric_set->symbol_name = "ThreadDispatcher39";
    metric_set->hw_config_guid = "af83fc4d-719e-460b-8cac-d315583f63a7";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher39_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher39__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher39__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher39__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher39__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE0",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE0",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher39__thread_dispatch_ps_active_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher39_THREAD_DISPATCH_PS_ACTIVE_XECORE0_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE1",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE1",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher39__thread_dispatch_ps_active_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher39_THREAD_DISPATCH_PS_ACTIVE_XECORE1_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE2",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE2",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher39__thread_dispatch_ps_active_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher39_THREAD_DISPATCH_PS_ACTIVE_XECORE2_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE3",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE3",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher39__thread_dispatch_ps_active_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher39_THREAD_DISPATCH_PS_ACTIVE_XECORE3_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE4",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE4",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher39__thread_dispatch_ps_active_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher39_THREAD_DISPATCH_PS_ACTIVE_XECORE4_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE5",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE5",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher39__thread_dispatch_ps_active_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher39_THREAD_DISPATCH_PS_ACTIVE_XECORE5_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE6",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE6",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher39__thread_dispatch_ps_active_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher39_THREAD_DISPATCH_PS_ACTIVE_XECORE6_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE7",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE7",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher39__thread_dispatch_ps_active_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher39_THREAD_DISPATCH_PS_ACTIVE_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_thread_dispatcher40_THREAD_DISPATCH_PS_ACTIVE_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher40_THREAD_DISPATCH_PS_ACTIVE_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher40_THREAD_DISPATCH_PS_ACTIVE_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher40_THREAD_DISPATCH_PS_ACTIVE_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher40_THREAD_DISPATCH_PS_ACTIVE_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher40_THREAD_DISPATCH_PS_ACTIVE_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher40_THREAD_DISPATCH_PS_ACTIVE_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher40_THREAD_DISPATCH_PS_ACTIVE_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher40_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher40";
    metric_set->symbol_name = "ThreadDispatcher40";
    metric_set->hw_config_guid = "3d539f37-55b5-4473-9b4c-2f7d704c0d3b";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher40_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher40__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher40__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher40__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher40__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE10",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE10",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher40__thread_dispatch_ps_active_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher40_THREAD_DISPATCH_PS_ACTIVE_XECORE10_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE11",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE11",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher40__thread_dispatch_ps_active_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher40_THREAD_DISPATCH_PS_ACTIVE_XECORE11_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE12",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE12",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher40__thread_dispatch_ps_active_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher40_THREAD_DISPATCH_PS_ACTIVE_XECORE12_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE13",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE13",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher40__thread_dispatch_ps_active_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher40_THREAD_DISPATCH_PS_ACTIVE_XECORE13_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE14",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE14",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher40__thread_dispatch_ps_active_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher40_THREAD_DISPATCH_PS_ACTIVE_XECORE14_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE15",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE15",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher40__thread_dispatch_ps_active_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher40_THREAD_DISPATCH_PS_ACTIVE_XECORE15_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE8",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE8",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher40__thread_dispatch_ps_active_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher40_THREAD_DISPATCH_PS_ACTIVE_XECORE8_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE9",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE9",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__thread_dispatcher40__thread_dispatch_ps_active_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher40_THREAD_DISPATCH_PS_ACTIVE_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt2_thread_dispatcher41_GPGPU_DISPATCH_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher41_GPGPU_DISPATCH_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher41_GPGPU_DISPATCH_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher41_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher41";
    metric_set->symbol_name = "ThreadDispatcher41";
    metric_set->hw_config_guid = "c6251684-6ce6-462f-807c-657b84a2234f";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher41_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher41__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher41__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU DISPATCH XECORE0",
                .symbol_name = "GPGPU_DISPATCH_XECORE0",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher41__gpgpu_dispatch_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher41_GPGPU_DISPATCH_XECORE0_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE1",
                .symbol_name = "GPGPU_DISPATCH_XECORE1",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher41__gpgpu_dispatch_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher41_GPGPU_DISPATCH_XECORE1_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE2",
                .symbol_name = "GPGPU_DISPATCH_XECORE2",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher41__gpgpu_dispatch_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher41_GPGPU_DISPATCH_XECORE2_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher41__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher41__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher42_GPGPU_DISPATCH_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher42_GPGPU_DISPATCH_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher42_GPGPU_DISPATCH_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher42_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher42";
    metric_set->symbol_name = "ThreadDispatcher42";
    metric_set->hw_config_guid = "55cbe93c-e003-445a-95ca-478e9b8b9b51";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher42_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher42__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher42__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU DISPATCH XECORE3",
                .symbol_name = "GPGPU_DISPATCH_XECORE3",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher42__gpgpu_dispatch_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher42_GPGPU_DISPATCH_XECORE3_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE4",
                .symbol_name = "GPGPU_DISPATCH_XECORE4",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher42__gpgpu_dispatch_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher42_GPGPU_DISPATCH_XECORE4_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE5",
                .symbol_name = "GPGPU_DISPATCH_XECORE5",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher42__gpgpu_dispatch_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher42_GPGPU_DISPATCH_XECORE5_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher42__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher42__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher43_GPGPU_DISPATCH_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher43_GPGPU_DISPATCH_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher43_GPGPU_DISPATCH_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher43_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher43";
    metric_set->symbol_name = "ThreadDispatcher43";
    metric_set->hw_config_guid = "9c9204e8-e9e6-4b93-975e-2fc874b22d9c";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher43_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher43__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher43__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU DISPATCH XECORE6",
                .symbol_name = "GPGPU_DISPATCH_XECORE6",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher43__gpgpu_dispatch_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher43_GPGPU_DISPATCH_XECORE6_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE7",
                .symbol_name = "GPGPU_DISPATCH_XECORE7",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher43__gpgpu_dispatch_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher43_GPGPU_DISPATCH_XECORE7_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE8",
                .symbol_name = "GPGPU_DISPATCH_XECORE8",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher43__gpgpu_dispatch_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher43_GPGPU_DISPATCH_XECORE8_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher43__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher43__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher44_GPGPU_DISPATCH_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher44_GPGPU_DISPATCH_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher44_GPGPU_DISPATCH_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher44_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher44";
    metric_set->symbol_name = "ThreadDispatcher44";
    metric_set->hw_config_guid = "ea77a8e8-375a-46a7-a4cb-b0a40f3ff83a";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher44_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher44__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher44__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU DISPATCH XECORE10",
                .symbol_name = "GPGPU_DISPATCH_XECORE10",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher44__gpgpu_dispatch_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher44_GPGPU_DISPATCH_XECORE10_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE11",
                .symbol_name = "GPGPU_DISPATCH_XECORE11",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher44__gpgpu_dispatch_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher44_GPGPU_DISPATCH_XECORE11_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE9",
                .symbol_name = "GPGPU_DISPATCH_XECORE9",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher44__gpgpu_dispatch_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher44_GPGPU_DISPATCH_XECORE9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher44__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher44__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher45_GPGPU_DISPATCH_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher45_GPGPU_DISPATCH_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_thread_dispatcher45_GPGPU_DISPATCH_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher45_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher45";
    metric_set->symbol_name = "ThreadDispatcher45";
    metric_set->hw_config_guid = "22202c50-f46b-4a14-aab6-15d079655616";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher45_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher45__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher45__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU DISPATCH XECORE12",
                .symbol_name = "GPGPU_DISPATCH_XECORE12",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher45__gpgpu_dispatch_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher45_GPGPU_DISPATCH_XECORE12_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE13",
                .symbol_name = "GPGPU_DISPATCH_XECORE13",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher45__gpgpu_dispatch_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher45_GPGPU_DISPATCH_XECORE13_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE14",
                .symbol_name = "GPGPU_DISPATCH_XECORE14",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher45__gpgpu_dispatch_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher45_GPGPU_DISPATCH_XECORE14_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher45__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher45__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_thread_dispatcher46_GPGPU_DISPATCH_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_thread_dispatcher46_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadDispatcher46";
    metric_set->symbol_name = "ThreadDispatcher46";
    metric_set->hw_config_guid = "4d77eb41-a74f-4e76-a0ac-66a63d2ad7c6";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_thread_dispatcher46_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__thread_dispatcher46__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__thread_dispatcher46__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU DISPATCH XECORE15",
                .symbol_name = "GPGPU_DISPATCH_XECORE15",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__thread_dispatcher46__gpgpu_dispatch_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt2_thread_dispatcher46_GPGPU_DISPATCH_XECORE15_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__thread_dispatcher46__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__thread_dispatcher46__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt2_urb1_URB_CROSS_SLICE_READ_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_urb1_URB_READ_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_urb1_URB_WRITE_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_urb1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "URB1";
    metric_set->symbol_name = "URB1";
    metric_set->hw_config_guid = "f02fbce6-28cf-42d5-a07d-6a5c07e3baf6";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_urb1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__urb1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__urb1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__urb1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__urb1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "URB CROSS SLICE READ SLICE0",
                .symbol_name = "URB_CROSS_SLICE_READ_SLICE0",
                .desc = "Number of URB reads occurred from cross slices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__urb1__urb_cross_slice_read_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt2_urb1_URB_CROSS_SLICE_READ_SLICE0_availability,
            },

            {
                .name = "URB READ SLICE0",
                .symbol_name = "URB_READ_SLICE0",
                .desc = "Number of URB reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__urb1__urb_read_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt2_urb1_URB_READ_SLICE0_availability,
            },

            {
                .name = "URB WRITE SLICE0",
                .symbol_name = "URB_WRITE_SLICE0",
                .desc = "Number of URB writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__urb1__urb_write_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt2_urb1_URB_WRITE_SLICE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_urb2_URB_CROSS_SLICE_READ_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_urb2_URB_READ_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_urb2_URB_WRITE_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_urb2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "URB2";
    metric_set->symbol_name = "URB2";
    metric_set->hw_config_guid = "1f749c36-964c-40d3-ac0f-3b8e24d4149b";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_urb2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__urb2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__urb2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__urb2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__urb2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "URB CROSS SLICE READ SLICE1",
                .symbol_name = "URB_CROSS_SLICE_READ_SLICE1",
                .desc = "Number of URB reads occurred from cross slices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__urb2__urb_cross_slice_read_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt2_urb2_URB_CROSS_SLICE_READ_SLICE1_availability,
            },

            {
                .name = "URB READ SLICE1",
                .symbol_name = "URB_READ_SLICE1",
                .desc = "Number of URB reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__urb2__urb_read_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt2_urb2_URB_READ_SLICE1_availability,
            },

            {
                .name = "URB WRITE SLICE1",
                .symbol_name = "URB_WRITE_SLICE1",
                .desc = "Number of URB writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__urb2__urb_write_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt2_urb2_URB_WRITE_SLICE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_urb3_URB_CROSS_SLICE_READ_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_urb3_URB_READ_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt2_urb3_URB_WRITE_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_urb3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "URB3";
    metric_set->symbol_name = "URB3";
    metric_set->hw_config_guid = "b7679a40-d48d-4994-8342-6277a37840ce";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_urb3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__urb3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__urb3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__urb3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__urb3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "URB CROSS SLICE READ SLICE2",
                .symbol_name = "URB_CROSS_SLICE_READ_SLICE2",
                .desc = "Number of URB reads occurred from cross slices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__urb3__urb_cross_slice_read_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt2_urb3_URB_CROSS_SLICE_READ_SLICE2_availability,
            },

            {
                .name = "URB READ SLICE2",
                .symbol_name = "URB_READ_SLICE2",
                .desc = "Number of URB reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__urb3__urb_read_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt2_urb3_URB_READ_SLICE2_availability,
            },

            {
                .name = "URB WRITE SLICE2",
                .symbol_name = "URB_WRITE_SLICE2",
                .desc = "Number of URB writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__urb3__urb_write_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt2_urb3_URB_WRITE_SLICE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_urb4_URB_CROSS_SLICE_READ_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_urb4_URB_READ_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt2_urb4_URB_WRITE_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_urb4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "URB4";
    metric_set->symbol_name = "URB4";
    metric_set->hw_config_guid = "23924e32-c593-4b9f-905b-908c380fb0b9";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_urb4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__urb4__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__urb4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__urb4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__urb4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "URB CROSS SLICE READ SLICE3",
                .symbol_name = "URB_CROSS_SLICE_READ_SLICE3",
                .desc = "Number of URB reads occurred from cross slices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__urb4__urb_cross_slice_read_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt2_urb4_URB_CROSS_SLICE_READ_SLICE3_availability,
            },

            {
                .name = "URB READ SLICE3",
                .symbol_name = "URB_READ_SLICE3",
                .desc = "Number of URB reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__urb4__urb_read_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt2_urb4_URB_READ_SLICE3_availability,
            },

            {
                .name = "URB WRITE SLICE3",
                .symbol_name = "URB_WRITE_SLICE3",
                .desc = "Number of URB writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__urb4__urb_write_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt2_urb4_URB_WRITE_SLICE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_vector_engine1_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine1_XVE_STALL_ALUWR_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine1_XVE_STALL_BARRIER_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine1_XVE_STALL_INSTFETCH_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine1_XVE_STALL_OTHER_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine1_XVE_STALL_SBID_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine1_XVE_STALL_SENDWR_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine1";
    metric_set->symbol_name = "VectorEngine1";
    metric_set->hw_config_guid = "30376d17-f01b-44cb-b41e-43a606fe4e0d";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine1__xve_shared_function_access_hold_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine1_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE0_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine1__xve_stall_aluwr_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine1_XVE_STALL_ALUWR_XECORE0_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine1__xve_stall_barrier_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine1_XVE_STALL_BARRIER_XECORE0_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine1__xve_stall_instfetch_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine1_XVE_STALL_INSTFETCH_XECORE0_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine1__xve_stall_other_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine1_XVE_STALL_OTHER_XECORE0_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine1__xve_stall_sbid_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine1_XVE_STALL_SBID_XECORE0_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine1__xve_stall_sendwr_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine1_XVE_STALL_SENDWR_XECORE0_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt2_vector_engine2_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine2_XVE_STALL_ALUWR_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine2_XVE_STALL_BARRIER_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine2_XVE_STALL_INSTFETCH_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine2_XVE_STALL_OTHER_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine2_XVE_STALL_SBID_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine2_XVE_STALL_SENDWR_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine2";
    metric_set->symbol_name = "VectorEngine2";
    metric_set->hw_config_guid = "cbc51aeb-65c2-4bb6-8fb5-40a47800bf28";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine2__xve_shared_function_access_hold_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine2_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE1_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine2__xve_stall_aluwr_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine2_XVE_STALL_ALUWR_XECORE1_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine2__xve_stall_barrier_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine2_XVE_STALL_BARRIER_XECORE1_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine2__xve_stall_instfetch_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine2_XVE_STALL_INSTFETCH_XECORE1_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine2__xve_stall_other_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine2_XVE_STALL_OTHER_XECORE1_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine2__xve_stall_sbid_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine2_XVE_STALL_SBID_XECORE1_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine2__xve_stall_sendwr_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine2_XVE_STALL_SENDWR_XECORE1_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt2_vector_engine3_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine3_XVE_STALL_ALUWR_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine3_XVE_STALL_BARRIER_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine3_XVE_STALL_INSTFETCH_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine3_XVE_STALL_OTHER_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine3_XVE_STALL_SBID_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine3_XVE_STALL_SENDWR_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine3";
    metric_set->symbol_name = "VectorEngine3";
    metric_set->hw_config_guid = "48620eda-41d2-4684-b4da-0140d1cdc8ba";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine3__xve_shared_function_access_hold_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine3_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE2_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine3__xve_stall_aluwr_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine3_XVE_STALL_ALUWR_XECORE2_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine3__xve_stall_barrier_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine3_XVE_STALL_BARRIER_XECORE2_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine3__xve_stall_instfetch_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine3_XVE_STALL_INSTFETCH_XECORE2_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine3__xve_stall_other_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine3_XVE_STALL_OTHER_XECORE2_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine3__xve_stall_sbid_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine3_XVE_STALL_SBID_XECORE2_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine3__xve_stall_sendwr_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine3_XVE_STALL_SENDWR_XECORE2_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt2_vector_engine4_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine4_XVE_STALL_ALUWR_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine4_XVE_STALL_BARRIER_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine4_XVE_STALL_INSTFETCH_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine4_XVE_STALL_OTHER_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine4_XVE_STALL_SBID_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine4_XVE_STALL_SENDWR_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine4";
    metric_set->symbol_name = "VectorEngine4";
    metric_set->hw_config_guid = "4f2d3240-5242-48d7-8f25-1064a7044c01";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine4__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine4__xve_shared_function_access_hold_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine4_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE3_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine4__xve_stall_aluwr_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine4_XVE_STALL_ALUWR_XECORE3_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine4__xve_stall_barrier_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine4_XVE_STALL_BARRIER_XECORE3_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine4__xve_stall_instfetch_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine4_XVE_STALL_INSTFETCH_XECORE3_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine4__xve_stall_other_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine4_XVE_STALL_OTHER_XECORE3_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine4__xve_stall_sbid_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine4_XVE_STALL_SBID_XECORE3_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine4__xve_stall_sendwr_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine4_XVE_STALL_SENDWR_XECORE3_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt2_vector_engine5_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine5_XVE_STALL_ALUWR_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine5_XVE_STALL_BARRIER_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine5_XVE_STALL_INSTFETCH_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine5_XVE_STALL_OTHER_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine5_XVE_STALL_SBID_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine5_XVE_STALL_SENDWR_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine5_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine5";
    metric_set->symbol_name = "VectorEngine5";
    metric_set->hw_config_guid = "510e005b-5631-437d-b898-17d89b9df71d";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine5_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine5__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine5__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine5__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine5__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine5__xve_shared_function_access_hold_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine5_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE4_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine5__xve_stall_aluwr_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine5_XVE_STALL_ALUWR_XECORE4_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine5__xve_stall_barrier_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine5_XVE_STALL_BARRIER_XECORE4_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine5__xve_stall_instfetch_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine5_XVE_STALL_INSTFETCH_XECORE4_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine5__xve_stall_other_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine5_XVE_STALL_OTHER_XECORE4_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine5__xve_stall_sbid_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine5_XVE_STALL_SBID_XECORE4_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine5__xve_stall_sendwr_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine5_XVE_STALL_SENDWR_XECORE4_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt2_vector_engine6_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine6_XVE_STALL_ALUWR_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine6_XVE_STALL_BARRIER_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine6_XVE_STALL_INSTFETCH_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine6_XVE_STALL_OTHER_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine6_XVE_STALL_SBID_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine6_XVE_STALL_SENDWR_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine6_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine6";
    metric_set->symbol_name = "VectorEngine6";
    metric_set->hw_config_guid = "c063d6a9-6cb2-449f-8799-322c31d6eb0d";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine6_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine6__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine6__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine6__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine6__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine6__xve_shared_function_access_hold_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine6_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE5_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine6__xve_stall_aluwr_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine6_XVE_STALL_ALUWR_XECORE5_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine6__xve_stall_barrier_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine6_XVE_STALL_BARRIER_XECORE5_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine6__xve_stall_instfetch_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine6_XVE_STALL_INSTFETCH_XECORE5_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine6__xve_stall_other_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine6_XVE_STALL_OTHER_XECORE5_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine6__xve_stall_sbid_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine6_XVE_STALL_SBID_XECORE5_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine6__xve_stall_sendwr_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine6_XVE_STALL_SENDWR_XECORE5_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt2_vector_engine7_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine7_XVE_STALL_ALUWR_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine7_XVE_STALL_BARRIER_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine7_XVE_STALL_INSTFETCH_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine7_XVE_STALL_OTHER_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine7_XVE_STALL_SBID_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine7_XVE_STALL_SENDWR_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine7_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine7";
    metric_set->symbol_name = "VectorEngine7";
    metric_set->hw_config_guid = "fbfb8b12-d3b3-469d-ae93-c026b05b2107";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine7_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine7__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine7__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine7__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine7__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine7__xve_shared_function_access_hold_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine7_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE6_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine7__xve_stall_aluwr_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine7_XVE_STALL_ALUWR_XECORE6_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine7__xve_stall_barrier_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine7_XVE_STALL_BARRIER_XECORE6_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine7__xve_stall_instfetch_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine7_XVE_STALL_INSTFETCH_XECORE6_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine7__xve_stall_other_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine7_XVE_STALL_OTHER_XECORE6_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine7__xve_stall_sbid_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine7_XVE_STALL_SBID_XECORE6_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine7__xve_stall_sendwr_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine7_XVE_STALL_SENDWR_XECORE6_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt2_vector_engine8_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine8_XVE_STALL_ALUWR_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine8_XVE_STALL_BARRIER_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine8_XVE_STALL_INSTFETCH_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine8_XVE_STALL_OTHER_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine8_XVE_STALL_SBID_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine8_XVE_STALL_SENDWR_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine8_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine8";
    metric_set->symbol_name = "VectorEngine8";
    metric_set->hw_config_guid = "2705f48c-206f-43e8-bde7-110fbfb0facd";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine8_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine8__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine8__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine8__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine8__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine8__xve_shared_function_access_hold_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine8_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE7_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine8__xve_stall_aluwr_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine8_XVE_STALL_ALUWR_XECORE7_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine8__xve_stall_barrier_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine8_XVE_STALL_BARRIER_XECORE7_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine8__xve_stall_instfetch_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine8_XVE_STALL_INSTFETCH_XECORE7_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine8__xve_stall_other_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine8_XVE_STALL_OTHER_XECORE7_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine8__xve_stall_sbid_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine8_XVE_STALL_SBID_XECORE7_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine8__xve_stall_sendwr_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine8_XVE_STALL_SENDWR_XECORE7_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt2_vector_engine9_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE8_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine9_XVE_STALL_ALUWR_XECORE8_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine9_XVE_STALL_BARRIER_XECORE8_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine9_XVE_STALL_INSTFETCH_XECORE8_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine9_XVE_STALL_OTHER_XECORE8_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine9_XVE_STALL_SBID_XECORE8_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine9_XVE_STALL_SENDWR_XECORE8_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine9_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine9";
    metric_set->symbol_name = "VectorEngine9";
    metric_set->hw_config_guid = "85cb3e85-43ab-4e7f-8962-ff5e203b079f";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine9_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine9__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine9__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine9__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine9__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE8 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE8_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine9__xve_shared_function_access_hold_xecore8_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine9_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE8_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE8 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE8_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine9__xve_stall_aluwr_xecore8_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine9_XVE_STALL_ALUWR_XECORE8_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE8 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE8_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine9__xve_stall_barrier_xecore8_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine9_XVE_STALL_BARRIER_XECORE8_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE8 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE8_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine9__xve_stall_instfetch_xecore8_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine9_XVE_STALL_INSTFETCH_XECORE8_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE8 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE8_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine9__xve_stall_other_xecore8_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine9_XVE_STALL_OTHER_XECORE8_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE8 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE8_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine9__xve_stall_sbid_xecore8_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine9_XVE_STALL_SBID_XECORE8_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE8 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE8_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine9__xve_stall_sendwr_xecore8_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine9_XVE_STALL_SENDWR_XECORE8_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt2_vector_engine10_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE9_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine10_XVE_STALL_ALUWR_XECORE9_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine10_XVE_STALL_BARRIER_XECORE9_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine10_XVE_STALL_INSTFETCH_XECORE9_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine10_XVE_STALL_OTHER_XECORE9_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine10_XVE_STALL_SBID_XECORE9_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine10_XVE_STALL_SENDWR_XECORE9_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine10_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine10";
    metric_set->symbol_name = "VectorEngine10";
    metric_set->hw_config_guid = "b2c23ce7-cfd8-45c8-bde6-b5d7c248b5b3";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine10_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine10__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine10__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine10__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine10__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE9 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE9_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine10__xve_shared_function_access_hold_xecore9_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine10_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE9_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE9 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE9_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine10__xve_stall_aluwr_xecore9_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine10_XVE_STALL_ALUWR_XECORE9_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE9 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE9_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine10__xve_stall_barrier_xecore9_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine10_XVE_STALL_BARRIER_XECORE9_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE9 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE9_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine10__xve_stall_instfetch_xecore9_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine10_XVE_STALL_INSTFETCH_XECORE9_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE9 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE9_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine10__xve_stall_other_xecore9_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine10_XVE_STALL_OTHER_XECORE9_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE9 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE9_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine10__xve_stall_sbid_xecore9_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine10_XVE_STALL_SBID_XECORE9_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE9 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE9_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine10__xve_stall_sendwr_xecore9_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine10_XVE_STALL_SENDWR_XECORE9_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt2_vector_engine11_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE10_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine11_XVE_STALL_ALUWR_XECORE10_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine11_XVE_STALL_BARRIER_XECORE10_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine11_XVE_STALL_INSTFETCH_XECORE10_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine11_XVE_STALL_OTHER_XECORE10_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine11_XVE_STALL_SBID_XECORE10_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine11_XVE_STALL_SENDWR_XECORE10_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine11_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine11";
    metric_set->symbol_name = "VectorEngine11";
    metric_set->hw_config_guid = "567eef44-e37e-48d9-8f4d-fe2634110051";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine11_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine11__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine11__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine11__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine11__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE10 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE10_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine11__xve_shared_function_access_hold_xecore10_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine11_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE10_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE10 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE10_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine11__xve_stall_aluwr_xecore10_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine11_XVE_STALL_ALUWR_XECORE10_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE10 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE10_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine11__xve_stall_barrier_xecore10_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine11_XVE_STALL_BARRIER_XECORE10_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE10 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE10_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine11__xve_stall_instfetch_xecore10_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine11_XVE_STALL_INSTFETCH_XECORE10_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE10 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE10_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine11__xve_stall_other_xecore10_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine11_XVE_STALL_OTHER_XECORE10_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE10 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE10_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine11__xve_stall_sbid_xecore10_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine11_XVE_STALL_SBID_XECORE10_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE10 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE10_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine11__xve_stall_sendwr_xecore10_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine11_XVE_STALL_SENDWR_XECORE10_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt2_vector_engine12_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE11_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine12_XVE_STALL_ALUWR_XECORE11_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine12_XVE_STALL_BARRIER_XECORE11_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine12_XVE_STALL_INSTFETCH_XECORE11_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine12_XVE_STALL_OTHER_XECORE11_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine12_XVE_STALL_SBID_XECORE11_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine12_XVE_STALL_SENDWR_XECORE11_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine12_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine12";
    metric_set->symbol_name = "VectorEngine12";
    metric_set->hw_config_guid = "d68e64a7-2ddb-4c33-a5d0-a0ff9de398f9";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine12_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine12__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine12__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine12__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine12__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE11 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE11_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine12__xve_shared_function_access_hold_xecore11_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine12_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE11_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE11 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE11_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine12__xve_stall_aluwr_xecore11_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine12_XVE_STALL_ALUWR_XECORE11_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE11 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE11_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine12__xve_stall_barrier_xecore11_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine12_XVE_STALL_BARRIER_XECORE11_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE11 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE11_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine12__xve_stall_instfetch_xecore11_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine12_XVE_STALL_INSTFETCH_XECORE11_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE11 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE11_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine12__xve_stall_other_xecore11_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine12_XVE_STALL_OTHER_XECORE11_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE11 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE11_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine12__xve_stall_sbid_xecore11_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine12_XVE_STALL_SBID_XECORE11_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE11 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE11_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine12__xve_stall_sendwr_xecore11_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine12_XVE_STALL_SENDWR_XECORE11_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt2_vector_engine13_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE12_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine13_XVE_STALL_ALUWR_XECORE12_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine13_XVE_STALL_BARRIER_XECORE12_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine13_XVE_STALL_INSTFETCH_XECORE12_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine13_XVE_STALL_OTHER_XECORE12_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine13_XVE_STALL_SBID_XECORE12_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine13_XVE_STALL_SENDWR_XECORE12_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine13_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine13";
    metric_set->symbol_name = "VectorEngine13";
    metric_set->hw_config_guid = "5123cfe9-f7b0-41ee-a2f2-6e5801ac55f6";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine13_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine13__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine13__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine13__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine13__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE12 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE12_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine13__xve_shared_function_access_hold_xecore12_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine13_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE12_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE12 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE12_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine13__xve_stall_aluwr_xecore12_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine13_XVE_STALL_ALUWR_XECORE12_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE12 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE12_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine13__xve_stall_barrier_xecore12_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine13_XVE_STALL_BARRIER_XECORE12_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE12 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE12_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine13__xve_stall_instfetch_xecore12_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine13_XVE_STALL_INSTFETCH_XECORE12_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE12 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE12_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine13__xve_stall_other_xecore12_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine13_XVE_STALL_OTHER_XECORE12_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE12 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE12_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine13__xve_stall_sbid_xecore12_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine13_XVE_STALL_SBID_XECORE12_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE12 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE12_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine13__xve_stall_sendwr_xecore12_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine13_XVE_STALL_SENDWR_XECORE12_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt2_vector_engine14_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE13_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine14_XVE_STALL_ALUWR_XECORE13_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine14_XVE_STALL_BARRIER_XECORE13_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine14_XVE_STALL_INSTFETCH_XECORE13_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine14_XVE_STALL_OTHER_XECORE13_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine14_XVE_STALL_SBID_XECORE13_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine14_XVE_STALL_SENDWR_XECORE13_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine14_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine14";
    metric_set->symbol_name = "VectorEngine14";
    metric_set->hw_config_guid = "f7b22238-61e9-4c17-a211-90f5feb9dd31";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine14_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine14__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine14__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine14__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine14__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE13 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE13_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine14__xve_shared_function_access_hold_xecore13_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine14_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE13_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE13 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE13_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine14__xve_stall_aluwr_xecore13_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine14_XVE_STALL_ALUWR_XECORE13_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE13 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE13_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine14__xve_stall_barrier_xecore13_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine14_XVE_STALL_BARRIER_XECORE13_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE13 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE13_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine14__xve_stall_instfetch_xecore13_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine14_XVE_STALL_INSTFETCH_XECORE13_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE13 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE13_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine14__xve_stall_other_xecore13_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine14_XVE_STALL_OTHER_XECORE13_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE13 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE13_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine14__xve_stall_sbid_xecore13_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine14_XVE_STALL_SBID_XECORE13_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE13 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE13_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine14__xve_stall_sendwr_xecore13_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine14_XVE_STALL_SENDWR_XECORE13_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt2_vector_engine15_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE14_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine15_XVE_STALL_ALUWR_XECORE14_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine15_XVE_STALL_BARRIER_XECORE14_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine15_XVE_STALL_INSTFETCH_XECORE14_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine15_XVE_STALL_OTHER_XECORE14_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine15_XVE_STALL_SBID_XECORE14_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine15_XVE_STALL_SENDWR_XECORE14_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine15_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine15";
    metric_set->symbol_name = "VectorEngine15";
    metric_set->hw_config_guid = "27f15518-fd8e-48ac-8fa8-f844a09a9cf3";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine15_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine15__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine15__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine15__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine15__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE14 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE14_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine15__xve_shared_function_access_hold_xecore14_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine15_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE14_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE14 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE14_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine15__xve_stall_aluwr_xecore14_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine15_XVE_STALL_ALUWR_XECORE14_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE14 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE14_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine15__xve_stall_barrier_xecore14_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine15_XVE_STALL_BARRIER_XECORE14_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE14 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE14_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine15__xve_stall_instfetch_xecore14_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine15_XVE_STALL_INSTFETCH_XECORE14_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE14 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE14_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine15__xve_stall_other_xecore14_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine15_XVE_STALL_OTHER_XECORE14_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE14 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE14_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine15__xve_stall_sbid_xecore14_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine15_XVE_STALL_SBID_XECORE14_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE14 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE14_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine15__xve_stall_sendwr_xecore14_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine15_XVE_STALL_SENDWR_XECORE14_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt2_vector_engine16_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE15_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine16_XVE_STALL_ALUWR_XECORE15_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine16_XVE_STALL_BARRIER_XECORE15_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine16_XVE_STALL_INSTFETCH_XECORE15_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine16_XVE_STALL_OTHER_XECORE15_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine16_XVE_STALL_SBID_XECORE15_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine16_XVE_STALL_SENDWR_XECORE15_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine16_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine16";
    metric_set->symbol_name = "VectorEngine16";
    metric_set->hw_config_guid = "75bcab1e-545a-41a4-8437-70d37569f798";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine16_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine16__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine16__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine16__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine16__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE15 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE15_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine16__xve_shared_function_access_hold_xecore15_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine16_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE15_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE15 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE15_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine16__xve_stall_aluwr_xecore15_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine16_XVE_STALL_ALUWR_XECORE15_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE15 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE15_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine16__xve_stall_barrier_xecore15_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine16_XVE_STALL_BARRIER_XECORE15_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE15 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE15_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine16__xve_stall_instfetch_xecore15_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine16_XVE_STALL_INSTFETCH_XECORE15_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE15 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE15_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine16__xve_stall_other_xecore15_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine16_XVE_STALL_OTHER_XECORE15_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE15 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE15_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine16__xve_stall_sbid_xecore15_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine16_XVE_STALL_SBID_XECORE15_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE15 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE15_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine16__xve_stall_sendwr_xecore15_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine16_XVE_STALL_SENDWR_XECORE15_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt2_vector_engine17_ICACHE_HIT_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine17_ICACHE_HIT_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine17_ICACHE_HIT_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine17_ICACHE_HIT_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine17_ICACHE_HIT_BANK0_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine17_ICACHE_HIT_BANK0_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine17_ICACHE_HIT_BANK0_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine17_ICACHE_HIT_BANK0_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine17_ICACHE_MISS_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine17_ICACHE_MISS_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine17_ICACHE_MISS_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine17_ICACHE_MISS_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine17_ICACHE_MISS_BANK0_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine17_ICACHE_MISS_BANK0_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine17_ICACHE_MISS_BANK0_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine17_ICACHE_MISS_BANK0_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine17_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine17";
    metric_set->symbol_name = "VectorEngine17";
    metric_set->hw_config_guid = "5f1c4a7a-d5ab-45ad-a4fc-1e64a66839db";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine17_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine17__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine17__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine17__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine17__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK0 XECORE0",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE0",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine17__icache_hit_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine17_ICACHE_HIT_BANK0_XECORE0_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE1",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE1",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine17__icache_hit_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine17_ICACHE_HIT_BANK0_XECORE1_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE2",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE2",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine17__icache_hit_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine17_ICACHE_HIT_BANK0_XECORE2_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE3",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE3",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine17__icache_hit_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine17_ICACHE_HIT_BANK0_XECORE3_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE4",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE4",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine17__icache_hit_bank0_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine17_ICACHE_HIT_BANK0_XECORE4_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE5",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE5",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine17__icache_hit_bank0_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine17_ICACHE_HIT_BANK0_XECORE5_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE6",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE6",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine17__icache_hit_bank0_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine17_ICACHE_HIT_BANK0_XECORE6_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE7",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE7",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine17__icache_hit_bank0_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine17_ICACHE_HIT_BANK0_XECORE7_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE0",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE0",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine17__icache_miss_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine17_ICACHE_MISS_BANK0_XECORE0_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE1",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE1",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine17__icache_miss_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine17_ICACHE_MISS_BANK0_XECORE1_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE2",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE2",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine17__icache_miss_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine17_ICACHE_MISS_BANK0_XECORE2_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE3",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE3",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine17__icache_miss_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine17_ICACHE_MISS_BANK0_XECORE3_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE4",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE4",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine17__icache_miss_bank0_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine17_ICACHE_MISS_BANK0_XECORE4_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE5",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE5",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine17__icache_miss_bank0_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine17_ICACHE_MISS_BANK0_XECORE5_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE6",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE6",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine17__icache_miss_bank0_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine17_ICACHE_MISS_BANK0_XECORE6_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE7",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE7",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine17__icache_miss_bank0_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine17_ICACHE_MISS_BANK0_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_vector_engine18_ICACHE_HIT_BANK0_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine18_ICACHE_HIT_BANK0_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine18_ICACHE_HIT_BANK0_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine18_ICACHE_HIT_BANK0_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine18_ICACHE_HIT_BANK0_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine18_ICACHE_HIT_BANK0_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine18_ICACHE_HIT_BANK0_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine18_ICACHE_HIT_BANK0_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine18_ICACHE_MISS_BANK0_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine18_ICACHE_MISS_BANK0_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine18_ICACHE_MISS_BANK0_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine18_ICACHE_MISS_BANK0_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine18_ICACHE_MISS_BANK0_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine18_ICACHE_MISS_BANK0_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine18_ICACHE_MISS_BANK0_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine18_ICACHE_MISS_BANK0_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine18_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine18";
    metric_set->symbol_name = "VectorEngine18";
    metric_set->hw_config_guid = "c3522b36-01a6-4b3d-b95f-414dbc013ba6";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine18_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine18__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine18__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine18__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine18__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK0 XECORE10",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE10",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine18__icache_hit_bank0_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine18_ICACHE_HIT_BANK0_XECORE10_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE11",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE11",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine18__icache_hit_bank0_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine18_ICACHE_HIT_BANK0_XECORE11_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE12",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE12",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine18__icache_hit_bank0_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine18_ICACHE_HIT_BANK0_XECORE12_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE13",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE13",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine18__icache_hit_bank0_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine18_ICACHE_HIT_BANK0_XECORE13_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE14",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE14",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine18__icache_hit_bank0_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine18_ICACHE_HIT_BANK0_XECORE14_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE15",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE15",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine18__icache_hit_bank0_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine18_ICACHE_HIT_BANK0_XECORE15_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE8",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE8",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine18__icache_hit_bank0_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine18_ICACHE_HIT_BANK0_XECORE8_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE9",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE9",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine18__icache_hit_bank0_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine18_ICACHE_HIT_BANK0_XECORE9_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE10",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE10",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine18__icache_miss_bank0_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine18_ICACHE_MISS_BANK0_XECORE10_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE11",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE11",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine18__icache_miss_bank0_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine18_ICACHE_MISS_BANK0_XECORE11_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE12",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE12",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine18__icache_miss_bank0_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine18_ICACHE_MISS_BANK0_XECORE12_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE13",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE13",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine18__icache_miss_bank0_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine18_ICACHE_MISS_BANK0_XECORE13_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE14",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE14",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine18__icache_miss_bank0_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine18_ICACHE_MISS_BANK0_XECORE14_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE15",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE15",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine18__icache_miss_bank0_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine18_ICACHE_MISS_BANK0_XECORE15_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE8",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE8",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine18__icache_miss_bank0_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine18_ICACHE_MISS_BANK0_XECORE8_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE9",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE9",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine18__icache_miss_bank0_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine18_ICACHE_MISS_BANK0_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_vector_engine19_ICACHE_HIT_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine19_ICACHE_HIT_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine19_ICACHE_HIT_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine19_ICACHE_HIT_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine19_ICACHE_HIT_BANK1_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine19_ICACHE_HIT_BANK1_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine19_ICACHE_HIT_BANK1_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine19_ICACHE_HIT_BANK1_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine19_ICACHE_MISS_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine19_ICACHE_MISS_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine19_ICACHE_MISS_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine19_ICACHE_MISS_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine19_ICACHE_MISS_BANK1_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine19_ICACHE_MISS_BANK1_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine19_ICACHE_MISS_BANK1_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine19_ICACHE_MISS_BANK1_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine19_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine19";
    metric_set->symbol_name = "VectorEngine19";
    metric_set->hw_config_guid = "3e973327-7b3f-4168-afd9-b244050e9ce7";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine19_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine19__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine19__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine19__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine19__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK1 XECORE0",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE0",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine19__icache_hit_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine19_ICACHE_HIT_BANK1_XECORE0_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE1",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE1",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine19__icache_hit_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine19_ICACHE_HIT_BANK1_XECORE1_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE2",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE2",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine19__icache_hit_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine19_ICACHE_HIT_BANK1_XECORE2_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE3",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE3",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine19__icache_hit_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine19_ICACHE_HIT_BANK1_XECORE3_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE4",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE4",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine19__icache_hit_bank1_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine19_ICACHE_HIT_BANK1_XECORE4_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE5",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE5",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine19__icache_hit_bank1_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine19_ICACHE_HIT_BANK1_XECORE5_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE6",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE6",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine19__icache_hit_bank1_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine19_ICACHE_HIT_BANK1_XECORE6_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE7",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE7",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine19__icache_hit_bank1_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine19_ICACHE_HIT_BANK1_XECORE7_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE0",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE0",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine19__icache_miss_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine19_ICACHE_MISS_BANK1_XECORE0_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE1",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE1",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine19__icache_miss_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine19_ICACHE_MISS_BANK1_XECORE1_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE2",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE2",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine19__icache_miss_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine19_ICACHE_MISS_BANK1_XECORE2_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE3",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE3",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine19__icache_miss_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine19_ICACHE_MISS_BANK1_XECORE3_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE4",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE4",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine19__icache_miss_bank1_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine19_ICACHE_MISS_BANK1_XECORE4_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE5",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE5",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine19__icache_miss_bank1_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine19_ICACHE_MISS_BANK1_XECORE5_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE6",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE6",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine19__icache_miss_bank1_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine19_ICACHE_MISS_BANK1_XECORE6_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE7",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE7",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine19__icache_miss_bank1_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine19_ICACHE_MISS_BANK1_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_vector_engine20_ICACHE_HIT_BANK1_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine20_ICACHE_HIT_BANK1_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine20_ICACHE_HIT_BANK1_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine20_ICACHE_HIT_BANK1_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine20_ICACHE_HIT_BANK1_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine20_ICACHE_HIT_BANK1_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine20_ICACHE_HIT_BANK1_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine20_ICACHE_HIT_BANK1_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine20_ICACHE_MISS_BANK1_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine20_ICACHE_MISS_BANK1_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine20_ICACHE_MISS_BANK1_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine20_ICACHE_MISS_BANK1_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine20_ICACHE_MISS_BANK1_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine20_ICACHE_MISS_BANK1_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine20_ICACHE_MISS_BANK1_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine20_ICACHE_MISS_BANK1_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine20_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine20";
    metric_set->symbol_name = "VectorEngine20";
    metric_set->hw_config_guid = "71d2d15b-f26c-4978-908a-f60275fa3562";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine20_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine20__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine20__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine20__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine20__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK1 XECORE10",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE10",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine20__icache_hit_bank1_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine20_ICACHE_HIT_BANK1_XECORE10_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE11",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE11",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine20__icache_hit_bank1_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine20_ICACHE_HIT_BANK1_XECORE11_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE12",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE12",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine20__icache_hit_bank1_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine20_ICACHE_HIT_BANK1_XECORE12_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE13",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE13",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine20__icache_hit_bank1_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine20_ICACHE_HIT_BANK1_XECORE13_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE14",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE14",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine20__icache_hit_bank1_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine20_ICACHE_HIT_BANK1_XECORE14_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE15",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE15",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine20__icache_hit_bank1_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine20_ICACHE_HIT_BANK1_XECORE15_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE8",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE8",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine20__icache_hit_bank1_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine20_ICACHE_HIT_BANK1_XECORE8_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE9",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE9",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine20__icache_hit_bank1_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine20_ICACHE_HIT_BANK1_XECORE9_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE10",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE10",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine20__icache_miss_bank1_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine20_ICACHE_MISS_BANK1_XECORE10_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE11",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE11",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine20__icache_miss_bank1_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine20_ICACHE_MISS_BANK1_XECORE11_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE12",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE12",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine20__icache_miss_bank1_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine20_ICACHE_MISS_BANK1_XECORE12_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE13",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE13",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine20__icache_miss_bank1_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine20_ICACHE_MISS_BANK1_XECORE13_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE14",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE14",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine20__icache_miss_bank1_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine20_ICACHE_MISS_BANK1_XECORE14_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE15",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE15",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine20__icache_miss_bank1_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine20_ICACHE_MISS_BANK1_XECORE15_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE8",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE8",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine20__icache_miss_bank1_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine20_ICACHE_MISS_BANK1_XECORE8_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE9",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE9",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine20__icache_miss_bank1_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine20_ICACHE_MISS_BANK1_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_vector_engine21_ICACHE_HIT_BANK2_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine21_ICACHE_HIT_BANK2_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine21_ICACHE_HIT_BANK2_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine21_ICACHE_HIT_BANK2_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine21_ICACHE_HIT_BANK2_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine21_ICACHE_HIT_BANK2_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine21_ICACHE_HIT_BANK2_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine21_ICACHE_HIT_BANK2_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine21_ICACHE_MISS_BANK2_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine21_ICACHE_MISS_BANK2_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine21_ICACHE_MISS_BANK2_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine21_ICACHE_MISS_BANK2_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine21_ICACHE_MISS_BANK2_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine21_ICACHE_MISS_BANK2_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine21_ICACHE_MISS_BANK2_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine21_ICACHE_MISS_BANK2_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine21_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine21";
    metric_set->symbol_name = "VectorEngine21";
    metric_set->hw_config_guid = "83cf4cf3-b666-44df-8702-7fc3e907164a";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine21_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine21__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine21__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine21__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine21__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK2 XECORE0",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE0",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine21__icache_hit_bank2_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine21_ICACHE_HIT_BANK2_XECORE0_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE1",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE1",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine21__icache_hit_bank2_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine21_ICACHE_HIT_BANK2_XECORE1_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE2",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE2",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine21__icache_hit_bank2_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine21_ICACHE_HIT_BANK2_XECORE2_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE3",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE3",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine21__icache_hit_bank2_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine21_ICACHE_HIT_BANK2_XECORE3_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE4",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE4",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine21__icache_hit_bank2_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine21_ICACHE_HIT_BANK2_XECORE4_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE5",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE5",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine21__icache_hit_bank2_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine21_ICACHE_HIT_BANK2_XECORE5_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE6",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE6",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine21__icache_hit_bank2_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine21_ICACHE_HIT_BANK2_XECORE6_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE7",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE7",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine21__icache_hit_bank2_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine21_ICACHE_HIT_BANK2_XECORE7_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE0",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE0",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine21__icache_miss_bank2_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine21_ICACHE_MISS_BANK2_XECORE0_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE1",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE1",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine21__icache_miss_bank2_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine21_ICACHE_MISS_BANK2_XECORE1_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE2",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE2",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine21__icache_miss_bank2_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine21_ICACHE_MISS_BANK2_XECORE2_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE3",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE3",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine21__icache_miss_bank2_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine21_ICACHE_MISS_BANK2_XECORE3_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE4",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE4",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine21__icache_miss_bank2_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine21_ICACHE_MISS_BANK2_XECORE4_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE5",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE5",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine21__icache_miss_bank2_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine21_ICACHE_MISS_BANK2_XECORE5_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE6",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE6",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine21__icache_miss_bank2_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine21_ICACHE_MISS_BANK2_XECORE6_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE7",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE7",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine21__icache_miss_bank2_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine21_ICACHE_MISS_BANK2_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_vector_engine22_ICACHE_HIT_BANK2_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine22_ICACHE_HIT_BANK2_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine22_ICACHE_HIT_BANK2_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine22_ICACHE_HIT_BANK2_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine22_ICACHE_HIT_BANK2_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine22_ICACHE_HIT_BANK2_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine22_ICACHE_HIT_BANK2_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine22_ICACHE_HIT_BANK2_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine22_ICACHE_MISS_BANK2_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine22_ICACHE_MISS_BANK2_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine22_ICACHE_MISS_BANK2_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine22_ICACHE_MISS_BANK2_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine22_ICACHE_MISS_BANK2_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine22_ICACHE_MISS_BANK2_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine22_ICACHE_MISS_BANK2_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine22_ICACHE_MISS_BANK2_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine22_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine22";
    metric_set->symbol_name = "VectorEngine22";
    metric_set->hw_config_guid = "c6b408ba-0479-40cb-8326-0fb1d709a261";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine22_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine22__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine22__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine22__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine22__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK2 XECORE10",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE10",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine22__icache_hit_bank2_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine22_ICACHE_HIT_BANK2_XECORE10_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE11",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE11",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine22__icache_hit_bank2_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine22_ICACHE_HIT_BANK2_XECORE11_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE12",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE12",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine22__icache_hit_bank2_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine22_ICACHE_HIT_BANK2_XECORE12_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE13",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE13",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine22__icache_hit_bank2_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine22_ICACHE_HIT_BANK2_XECORE13_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE14",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE14",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine22__icache_hit_bank2_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine22_ICACHE_HIT_BANK2_XECORE14_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE15",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE15",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine22__icache_hit_bank2_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine22_ICACHE_HIT_BANK2_XECORE15_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE8",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE8",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine22__icache_hit_bank2_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine22_ICACHE_HIT_BANK2_XECORE8_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE9",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE9",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine22__icache_hit_bank2_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine22_ICACHE_HIT_BANK2_XECORE9_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE10",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE10",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine22__icache_miss_bank2_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine22_ICACHE_MISS_BANK2_XECORE10_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE11",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE11",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine22__icache_miss_bank2_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine22_ICACHE_MISS_BANK2_XECORE11_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE12",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE12",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine22__icache_miss_bank2_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine22_ICACHE_MISS_BANK2_XECORE12_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE13",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE13",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine22__icache_miss_bank2_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine22_ICACHE_MISS_BANK2_XECORE13_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE14",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE14",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine22__icache_miss_bank2_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine22_ICACHE_MISS_BANK2_XECORE14_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE15",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE15",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine22__icache_miss_bank2_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine22_ICACHE_MISS_BANK2_XECORE15_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE8",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE8",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine22__icache_miss_bank2_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine22_ICACHE_MISS_BANK2_XECORE8_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE9",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE9",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine22__icache_miss_bank2_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine22_ICACHE_MISS_BANK2_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_vector_engine23_ICACHE_HIT_BANK3_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine23_ICACHE_HIT_BANK3_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine23_ICACHE_HIT_BANK3_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine23_ICACHE_HIT_BANK3_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine23_ICACHE_HIT_BANK3_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine23_ICACHE_HIT_BANK3_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine23_ICACHE_HIT_BANK3_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine23_ICACHE_HIT_BANK3_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine23_ICACHE_MISS_BANK3_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine23_ICACHE_MISS_BANK3_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine23_ICACHE_MISS_BANK3_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine23_ICACHE_MISS_BANK3_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine23_ICACHE_MISS_BANK3_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine23_ICACHE_MISS_BANK3_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine23_ICACHE_MISS_BANK3_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine23_ICACHE_MISS_BANK3_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine23_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine23";
    metric_set->symbol_name = "VectorEngine23";
    metric_set->hw_config_guid = "1f43061b-db78-405a-9246-6df8ff0592f4";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine23_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine23__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine23__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine23__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine23__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK3 XECORE0",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE0",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine23__icache_hit_bank3_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine23_ICACHE_HIT_BANK3_XECORE0_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE1",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE1",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine23__icache_hit_bank3_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine23_ICACHE_HIT_BANK3_XECORE1_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE2",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE2",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine23__icache_hit_bank3_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine23_ICACHE_HIT_BANK3_XECORE2_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE3",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE3",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine23__icache_hit_bank3_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine23_ICACHE_HIT_BANK3_XECORE3_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE4",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE4",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine23__icache_hit_bank3_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine23_ICACHE_HIT_BANK3_XECORE4_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE5",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE5",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine23__icache_hit_bank3_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine23_ICACHE_HIT_BANK3_XECORE5_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE6",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE6",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine23__icache_hit_bank3_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine23_ICACHE_HIT_BANK3_XECORE6_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE7",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE7",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine23__icache_hit_bank3_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine23_ICACHE_HIT_BANK3_XECORE7_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE0",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE0",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine23__icache_miss_bank3_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine23_ICACHE_MISS_BANK3_XECORE0_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE1",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE1",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine23__icache_miss_bank3_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine23_ICACHE_MISS_BANK3_XECORE1_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE2",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE2",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine23__icache_miss_bank3_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine23_ICACHE_MISS_BANK3_XECORE2_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE3",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE3",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine23__icache_miss_bank3_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine23_ICACHE_MISS_BANK3_XECORE3_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE4",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE4",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine23__icache_miss_bank3_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine23_ICACHE_MISS_BANK3_XECORE4_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE5",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE5",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine23__icache_miss_bank3_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine23_ICACHE_MISS_BANK3_XECORE5_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE6",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE6",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine23__icache_miss_bank3_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine23_ICACHE_MISS_BANK3_XECORE6_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE7",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE7",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine23__icache_miss_bank3_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine23_ICACHE_MISS_BANK3_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_vector_engine24_ICACHE_HIT_BANK3_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine24_ICACHE_HIT_BANK3_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine24_ICACHE_HIT_BANK3_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine24_ICACHE_HIT_BANK3_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine24_ICACHE_HIT_BANK3_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine24_ICACHE_HIT_BANK3_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine24_ICACHE_HIT_BANK3_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine24_ICACHE_HIT_BANK3_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine24_ICACHE_MISS_BANK3_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine24_ICACHE_MISS_BANK3_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine24_ICACHE_MISS_BANK3_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine24_ICACHE_MISS_BANK3_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine24_ICACHE_MISS_BANK3_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine24_ICACHE_MISS_BANK3_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine24_ICACHE_MISS_BANK3_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine24_ICACHE_MISS_BANK3_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine24_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine24";
    metric_set->symbol_name = "VectorEngine24";
    metric_set->hw_config_guid = "7aa880f9-6185-4b35-9d71-45cd71099d1c";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine24_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine24__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine24__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine24__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine24__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK3 XECORE10",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE10",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine24__icache_hit_bank3_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine24_ICACHE_HIT_BANK3_XECORE10_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE11",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE11",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine24__icache_hit_bank3_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine24_ICACHE_HIT_BANK3_XECORE11_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE12",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE12",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine24__icache_hit_bank3_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine24_ICACHE_HIT_BANK3_XECORE12_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE13",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE13",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine24__icache_hit_bank3_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine24_ICACHE_HIT_BANK3_XECORE13_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE14",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE14",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine24__icache_hit_bank3_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine24_ICACHE_HIT_BANK3_XECORE14_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE15",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE15",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine24__icache_hit_bank3_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine24_ICACHE_HIT_BANK3_XECORE15_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE8",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE8",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine24__icache_hit_bank3_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine24_ICACHE_HIT_BANK3_XECORE8_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE9",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE9",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine24__icache_hit_bank3_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine24_ICACHE_HIT_BANK3_XECORE9_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE10",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE10",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine24__icache_miss_bank3_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine24_ICACHE_MISS_BANK3_XECORE10_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE11",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE11",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine24__icache_miss_bank3_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine24_ICACHE_MISS_BANK3_XECORE11_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE12",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE12",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine24__icache_miss_bank3_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine24_ICACHE_MISS_BANK3_XECORE12_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE13",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE13",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine24__icache_miss_bank3_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine24_ICACHE_MISS_BANK3_XECORE13_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE14",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE14",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine24__icache_miss_bank3_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine24_ICACHE_MISS_BANK3_XECORE14_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE15",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE15",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine24__icache_miss_bank3_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine24_ICACHE_MISS_BANK3_XECORE15_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE8",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE8",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine24__icache_miss_bank3_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine24_ICACHE_MISS_BANK3_XECORE8_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE9",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE9",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine24__icache_miss_bank3_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine24_ICACHE_MISS_BANK3_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt2_vector_engine25_XVE_MULTIPLE_PIPE_ACTIVE_XECORE0_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine25_XVE_MULTIPLE_PIPE_ACTIVE_XECORE1_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine25_XVE_MULTIPLE_PIPE_ACTIVE_XECORE2_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine25_XVE_MULTIPLE_PIPE_ACTIVE_XECORE3_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine25_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine25";
    metric_set->symbol_name = "VectorEngine25";
    metric_set->hw_config_guid = "35c22c75-f1bd-4740-854b-b7248e45bb84";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine25_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine25__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine25__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine25__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine25__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE0 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE0_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine25__xve_multiple_pipe_active_xecore0_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine25_XVE_MULTIPLE_PIPE_ACTIVE_XECORE0_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE1 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE1_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine25__xve_multiple_pipe_active_xecore1_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine25_XVE_MULTIPLE_PIPE_ACTIVE_XECORE1_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE2 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE2_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine25__xve_multiple_pipe_active_xecore2_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine25_XVE_MULTIPLE_PIPE_ACTIVE_XECORE2_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE3 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE3_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine25__xve_multiple_pipe_active_xecore3_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine25_XVE_MULTIPLE_PIPE_ACTIVE_XECORE3_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_vector_engine26_XVE_MULTIPLE_PIPE_ACTIVE_XECORE4_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine26_XVE_MULTIPLE_PIPE_ACTIVE_XECORE5_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine26_XVE_MULTIPLE_PIPE_ACTIVE_XECORE6_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine26_XVE_MULTIPLE_PIPE_ACTIVE_XECORE7_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine26_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine26";
    metric_set->symbol_name = "VectorEngine26";
    metric_set->hw_config_guid = "208fe223-385c-4961-b2e7-cb44f3612b79";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine26_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine26__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine26__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine26__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine26__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE4 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE4_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine26__xve_multiple_pipe_active_xecore4_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine26_XVE_MULTIPLE_PIPE_ACTIVE_XECORE4_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE5 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE5_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine26__xve_multiple_pipe_active_xecore5_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine26_XVE_MULTIPLE_PIPE_ACTIVE_XECORE5_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE6 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE6_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine26__xve_multiple_pipe_active_xecore6_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine26_XVE_MULTIPLE_PIPE_ACTIVE_XECORE6_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE7 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE7_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine26__xve_multiple_pipe_active_xecore7_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine26_XVE_MULTIPLE_PIPE_ACTIVE_XECORE7_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_vector_engine27_XVE_MULTIPLE_PIPE_ACTIVE_XECORE10_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine27_XVE_MULTIPLE_PIPE_ACTIVE_XECORE11_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine27_XVE_MULTIPLE_PIPE_ACTIVE_XECORE8_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine27_XVE_MULTIPLE_PIPE_ACTIVE_XECORE9_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine27_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine27";
    metric_set->symbol_name = "VectorEngine27";
    metric_set->hw_config_guid = "b72101b8-7ef1-4bd1-ac6f-5e9ac5d098d6";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine27_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine27__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine27__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine27__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine27__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE10 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE10_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine27__xve_multiple_pipe_active_xecore10_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine27_XVE_MULTIPLE_PIPE_ACTIVE_XECORE10_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE11 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE11_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine27__xve_multiple_pipe_active_xecore11_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine27_XVE_MULTIPLE_PIPE_ACTIVE_XECORE11_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE8 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE8_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine27__xve_multiple_pipe_active_xecore8_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine27_XVE_MULTIPLE_PIPE_ACTIVE_XECORE8_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE9 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE9_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine27__xve_multiple_pipe_active_xecore9_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine27_XVE_MULTIPLE_PIPE_ACTIVE_XECORE9_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_vector_engine28_XVE_MULTIPLE_PIPE_ACTIVE_XECORE12_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine28_XVE_MULTIPLE_PIPE_ACTIVE_XECORE13_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine28_XVE_MULTIPLE_PIPE_ACTIVE_XECORE14_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine28_XVE_MULTIPLE_PIPE_ACTIVE_XECORE15_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine28_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine28";
    metric_set->symbol_name = "VectorEngine28";
    metric_set->hw_config_guid = "fdd412a9-274d-46ab-a27f-f3e107321d24";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine28_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine28__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine28__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine28__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine28__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE12 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE12_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine28__xve_multiple_pipe_active_xecore12_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine28_XVE_MULTIPLE_PIPE_ACTIVE_XECORE12_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE13 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE13_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine28__xve_multiple_pipe_active_xecore13_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine28_XVE_MULTIPLE_PIPE_ACTIVE_XECORE13_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE14 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE14_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine28__xve_multiple_pipe_active_xecore14_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine28_XVE_MULTIPLE_PIPE_ACTIVE_XECORE14_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE15 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE15_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine28__xve_multiple_pipe_active_xecore15_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine28_XVE_MULTIPLE_PIPE_ACTIVE_XECORE15_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt2_vector_engine29_XVE_INST_ISSUED_ALL_XECORE0_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine29_XVE_INST_ISSUED_ALL_XECORE1_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine29_XVE_INST_ISSUED_ALL_XECORE2_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine29_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine29";
    metric_set->symbol_name = "VectorEngine29";
    metric_set->hw_config_guid = "233317d4-03cf-4497-bb57-f9690bc057f4";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine29_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine29__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine29__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine29__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine29__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST ISSUED ALL XECORE0 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE0_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine29__xve_inst_issued_all_xecore0_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine29_XVE_INST_ISSUED_ALL_XECORE0_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE1 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE1_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine29__xve_inst_issued_all_xecore1_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine29_XVE_INST_ISSUED_ALL_XECORE1_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE2 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE2_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine29__xve_inst_issued_all_xecore2_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine29_XVE_INST_ISSUED_ALL_XECORE2_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_vector_engine30_XVE_INST_ISSUED_ALL_XECORE3_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine30_XVE_INST_ISSUED_ALL_XECORE4_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine30_XVE_INST_ISSUED_ALL_XECORE5_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine30_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine30";
    metric_set->symbol_name = "VectorEngine30";
    metric_set->hw_config_guid = "c11f8f0b-35fc-45de-b8d9-06664fa2b65c";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine30_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine30__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine30__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine30__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine30__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST ISSUED ALL XECORE3 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE3_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine30__xve_inst_issued_all_xecore3_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine30_XVE_INST_ISSUED_ALL_XECORE3_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE4 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE4_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine30__xve_inst_issued_all_xecore4_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine30_XVE_INST_ISSUED_ALL_XECORE4_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE5 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE5_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine30__xve_inst_issued_all_xecore5_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine30_XVE_INST_ISSUED_ALL_XECORE5_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_vector_engine31_XVE_INST_ISSUED_ALL_XECORE6_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine31_XVE_INST_ISSUED_ALL_XECORE7_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine31_XVE_INST_ISSUED_ALL_XECORE8_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine31_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine31";
    metric_set->symbol_name = "VectorEngine31";
    metric_set->hw_config_guid = "413fc3f3-9886-46d6-ab81-8cd6537f20e3";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine31_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine31__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine31__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine31__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine31__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST ISSUED ALL XECORE6 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE6_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine31__xve_inst_issued_all_xecore6_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine31_XVE_INST_ISSUED_ALL_XECORE6_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE7 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE7_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine31__xve_inst_issued_all_xecore7_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine31_XVE_INST_ISSUED_ALL_XECORE7_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE8 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE8_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine31__xve_inst_issued_all_xecore8_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine31_XVE_INST_ISSUED_ALL_XECORE8_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_vector_engine32_XVE_INST_ISSUED_ALL_XECORE10_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine32_XVE_INST_ISSUED_ALL_XECORE11_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine32_XVE_INST_ISSUED_ALL_XECORE9_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine32_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine32";
    metric_set->symbol_name = "VectorEngine32";
    metric_set->hw_config_guid = "fc0b9614-6c1b-4e90-976c-41dab7ef47aa";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine32_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine32__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine32__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine32__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine32__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST ISSUED ALL XECORE10 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE10_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine32__xve_inst_issued_all_xecore10_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine32_XVE_INST_ISSUED_ALL_XECORE10_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE11 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE11_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine32__xve_inst_issued_all_xecore11_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine32_XVE_INST_ISSUED_ALL_XECORE11_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE9 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE9_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine32__xve_inst_issued_all_xecore9_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine32_XVE_INST_ISSUED_ALL_XECORE9_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_vector_engine33_XVE_INST_ISSUED_ALL_XECORE12_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine33_XVE_INST_ISSUED_ALL_XECORE13_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt2_vector_engine33_XVE_INST_ISSUED_ALL_XECORE14_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine33_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine33";
    metric_set->symbol_name = "VectorEngine33";
    metric_set->hw_config_guid = "fc0d31b8-0d2d-4674-943a-3b2929dd7053";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine33_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine33__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine33__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine33__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine33__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST ISSUED ALL XECORE12 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE12_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine33__xve_inst_issued_all_xecore12_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine33_XVE_INST_ISSUED_ALL_XECORE12_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE13 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE13_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine33__xve_inst_issued_all_xecore13_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine33_XVE_INST_ISSUED_ALL_XECORE13_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE14 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE14_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine33__xve_inst_issued_all_xecore14_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine33_XVE_INST_ISSUED_ALL_XECORE14_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt2_vector_engine34_XVE_INST_ISSUED_ALL_XECORE15_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt2_add_vector_engine34_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine34";
    metric_set->symbol_name = "VectorEngine34";
    metric_set->hw_config_guid = "0b91a434-3d1a-44b4-aeb8-c0fe350f4ef0";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine34_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine34__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine34__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine34__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine34__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST ISSUED ALL XECORE15 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE15_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine34__xve_inst_issued_all_xecore15_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt2_vector_engine34_XVE_INST_ISSUED_ALL_XECORE15_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt2_add_vector_engine35_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine35";
    metric_set->symbol_name = "VectorEngine35";
    metric_set->hw_config_guid = "bf1e00b6-18c0-409e-8d2c-8105be297da4";
    metric_set->counters = calloc(23, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine35_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine35__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine35__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine35__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine35__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE ACTIVE",
                .symbol_name = "XVE_ACTIVE",
                .desc = "Percentage of time in which at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine35__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE ACTIVE CYCLES",
                .symbol_name = "XVE_ACTIVE_CYCLES",
                .desc = "Number of cycles at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine35__xve_active_cycles__read,
                .max_uint64 = acmgt2__vector_engine35__xve_active_cycles__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ALL",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ALL",
                .desc = "Number of execution slots taken by instructions executed on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine35__xve_inst_executed_alu0_all__read,
                .max_uint64 = acmgt2__vector_engine35__xve_inst_executed_alu0_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine35__xve_inst_executed_alu0_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ALL",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ALL",
                .desc = "Number of execution slots taken by instructions executed on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine35__xve_inst_executed_alu1_all__read,
                .max_uint64 = acmgt2__vector_engine35__xve_inst_executed_alu1_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine35__xve_inst_executed_alu1_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED CONTROL ALL",
                .symbol_name = "XVE_INST_EXECUTED_CONTROL_ALL",
                .desc = "Number of instructions executed on Jump Pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine35__xve_inst_executed_control_all__read,
                .max_uint64 = acmgt2__vector_engine35__xve_inst_executed_control_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED CONTROL ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_CONTROL_ALL_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed on Jump Pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine35__xve_inst_executed_control_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND ALL",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ALL",
                .desc = "Number of instructions executed on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine35__xve_inst_executed_send_all__read,
                .max_uint64 = acmgt2__vector_engine35__xve_inst_executed_send_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ALL_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine35__xve_inst_executed_send_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX ALL",
                .symbol_name = "XVE_INST_EXECUTED_XMX_ALL",
                .desc = "Number of execution slots taken by instructions executed in XMX pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine35__xve_inst_executed_xmx_all__read,
                .max_uint64 = acmgt2__vector_engine35__xve_inst_executed_xmx_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_XMX_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed in XMX pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine35__xve_inst_executed_xmx_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE PIPE ALU0 AND ALU1 ACTIVE",
                .symbol_name = "XVE_PIPE_ALU0_AND_ALU1_ACTIVE",
                .desc = "Percentage of time in which ALU0 and ALU1 pipes are both actively executing a Gen ISA instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine35__xve_pipe_alu0_and_alu1_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE PIPE ALU0 AND ALU1 ACTIVE CYCLES",
                .symbol_name = "XVE_PIPE_ALU0_AND_ALU1_ACTIVE_CYCLES",
                .desc = "Number of cycles in ALU0 and ALU1 pipes are both actively executing a Gen ISA instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine35__xve_pipe_alu0_and_alu1_active_cycles__read,
                .max_uint64 = acmgt2__vector_engine35__xve_pipe_alu0_and_alu1_active_cycles__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE PIPE ALU0 AND XMX ACTIVE",
                .symbol_name = "XVE_PIPE_ALU0_AND_XMX_ACTIVE",
                .desc = "Percentage of time in which ALU0 and XMX pipes are both actively executing a Gen ISA instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine35__xve_pipe_alu0_and_xmx_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE PIPE ALU0 AND XMX ACTIVE CYCLES",
                .symbol_name = "XVE_PIPE_ALU0_AND_XMX_ACTIVE_CYCLES",
                .desc = "Number of cycles ALU0 and XMX pipes are both actively executing a Gen ISA instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine35__xve_pipe_alu0_and_xmx_active_cycles__read,
                .max_uint64 = acmgt2__vector_engine35__xve_pipe_alu0_and_xmx_active_cycles__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine35__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES",
                .symbol_name = "XVE_STALL_CYCLES",
                .desc = "Number of cycles any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine35__xve_stall_cycles__read,
                .max_uint64 = acmgt2__vector_engine35__xve_stall_cycles__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE THREADS OCCUPANCY ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_ALL",
                .desc = "Percentage of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine35__xve_threads_occupancy_all__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE THREADS OCCUPANCY CYCLES ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_CYCLES_ALL",
                .desc = "Number of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine35__xve_threads_occupancy_cycles_all__read,
                .max_uint64 = acmgt2__vector_engine35__xve_threads_occupancy_cycles_all__max,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 23);
}


static void
acmgt2_add_vector_engine36_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine36";
    metric_set->symbol_name = "VectorEngine36";
    metric_set->hw_config_guid = "bbb25709-1345-473f-8233-6df9075eacda";
    metric_set->counters = calloc(27, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine36_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine36__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine36__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine36__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine36__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ASYNC CS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ASYNC_CS",
                .desc = "Number of execution slots taken by instructions executed by Async Compute Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine36__xve_inst_executed_alu0_async_cs__read,
                .max_uint64 = acmgt2__vector_engine36__xve_inst_executed_alu0_async_cs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ASYNC CS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ASYNC_CS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Async Compute Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine36__xve_inst_executed_alu0_async_cs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 CS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_CS",
                .desc = "Number of execution slots taken by instructions executed by Compute Shader (from Render Engine) on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine36__xve_inst_executed_alu0_cs__read,
                .max_uint64 = acmgt2__vector_engine36__xve_inst_executed_alu0_cs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 CS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_CS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Compute Shader (from Render Engine) on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine36__xve_inst_executed_alu0_cs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 DS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_DS",
                .desc = "Number of execution slots taken by instructions executed by Domain Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine36__xve_inst_executed_alu0_ds__read,
                .max_uint64 = acmgt2__vector_engine36__xve_inst_executed_alu0_ds__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 DS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_DS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Domain Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine36__xve_inst_executed_alu0_ds_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 HS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_HS",
                .desc = "Number of execution slots taken by instructions executed by Hull Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine36__xve_inst_executed_alu0_hs__read,
                .max_uint64 = acmgt2__vector_engine36__xve_inst_executed_alu0_hs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 HS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_HS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Hull Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine36__xve_inst_executed_alu0_hs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 FS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_PS",
                .desc = "Number of execution slots taken by instructions executed by Fragment Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine36__xve_inst_executed_alu0_ps__read,
                .max_uint64 = acmgt2__vector_engine36__xve_inst_executed_alu0_ps__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 FS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_PS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Fragment Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine36__xve_inst_executed_alu0_ps_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 VS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_VS",
                .desc = "Number of execution slots taken by instructions executed by Vertex Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine36__xve_inst_executed_alu0_vs__read,
                .max_uint64 = acmgt2__vector_engine36__xve_inst_executed_alu0_vs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 VS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_VS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Vertex Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine36__xve_inst_executed_alu0_vs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ASYNC CS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ASYNC_CS",
                .desc = "Number of execution slots taken by instructions executed by Async Compute Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine36__xve_inst_executed_alu1_async_cs__read,
                .max_uint64 = acmgt2__vector_engine36__xve_inst_executed_alu1_async_cs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ASYNC CS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ASYNC_CS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Async Compute Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine36__xve_inst_executed_alu1_async_cs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 CS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_CS",
                .desc = "Number of execution slots taken by instructions executed by Compute Shader (from Render Engine) on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine36__xve_inst_executed_alu1_cs__read,
                .max_uint64 = acmgt2__vector_engine36__xve_inst_executed_alu1_cs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 CS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_CS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Compute Shader (from Render Engine) on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine36__xve_inst_executed_alu1_cs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 DS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_DS",
                .desc = "Number of execution slots taken by instructions executed by Domain Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine36__xve_inst_executed_alu1_ds__read,
                .max_uint64 = acmgt2__vector_engine36__xve_inst_executed_alu1_ds__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 DS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_DS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Domain Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine36__xve_inst_executed_alu1_ds_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 HS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_HS",
                .desc = "Number of execution slots taken by instructions executed by Hull Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine36__xve_inst_executed_alu1_hs__read,
                .max_uint64 = acmgt2__vector_engine36__xve_inst_executed_alu1_hs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 HS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_HS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Hull Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine36__xve_inst_executed_alu1_hs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 FS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_PS",
                .desc = "Number of execution slots taken by instructions executed by Fragment Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine36__xve_inst_executed_alu1_ps__read,
                .max_uint64 = acmgt2__vector_engine36__xve_inst_executed_alu1_ps__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 FS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_PS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Fragment Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine36__xve_inst_executed_alu1_ps_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 VS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_VS",
                .desc = "Number of execution slots taken by instructions executed by Vertex Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine36__xve_inst_executed_alu1_vs__read,
                .max_uint64 = acmgt2__vector_engine36__xve_inst_executed_alu1_vs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 VS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_VS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Vertex Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine36__xve_inst_executed_alu1_vs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 27);
}


static void
acmgt2_add_vector_engine37_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine37";
    metric_set->symbol_name = "VectorEngine37";
    metric_set->hw_config_guid = "fc1c6f5b-60ad-48c8-b0b7-ed9328548c7a";
    metric_set->counters = calloc(21, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine37_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine37__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine37__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine37__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine37__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST EXECUTED ALU0 RT AHS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_RT_AHS",
                .desc = "Number of execution slots taken by instructions executed by BTD Any Hit Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine37__xve_inst_executed_alu0_rt_ahs__read,
                .max_uint64 = acmgt2__vector_engine37__xve_inst_executed_alu0_rt_ahs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 RT AHS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_RT_AHS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by BTD Any Hit Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine37__xve_inst_executed_alu0_rt_ahs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 RT CHS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_RT_CHS",
                .desc = "Number of execution slots taken by instructions executed by BTD Closest Hit Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine37__xve_inst_executed_alu0_rt_chs__read,
                .max_uint64 = acmgt2__vector_engine37__xve_inst_executed_alu0_rt_chs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 RT CHS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_RT_CHS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by BTD Closest Hit Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine37__xve_inst_executed_alu0_rt_chs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 RT MS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_RT_MS",
                .desc = "Number of execution slots taken by instructions executed by BTD Miss Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine37__xve_inst_executed_alu0_rt_ms__read,
                .max_uint64 = acmgt2__vector_engine37__xve_inst_executed_alu0_rt_ms__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 RT MS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_RT_MS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by BTD Miss Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine37__xve_inst_executed_alu0_rt_ms_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 RT AHS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_RT_AHS",
                .desc = "Number of execution slots taken by instructions executed by BTD Any Hit Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine37__xve_inst_executed_alu1_rt_ahs__read,
                .max_uint64 = acmgt2__vector_engine37__xve_inst_executed_alu1_rt_ahs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 RT AHS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_RT_AHS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by BTD Any Hit Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine37__xve_inst_executed_alu1_rt_ahs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 RT CHS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_RT_CHS",
                .desc = "Number of execution slots taken by instructions executed by BTD Closest Hit Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine37__xve_inst_executed_alu1_rt_chs__read,
                .max_uint64 = acmgt2__vector_engine37__xve_inst_executed_alu1_rt_chs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 RT CHS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_RT_CHS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by BTD Closest Hit Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine37__xve_inst_executed_alu1_rt_chs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 RT MS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_RT_MS",
                .desc = "Number of execution slots taken by instructions executed by BTD Miss Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine37__xve_inst_executed_alu1_rt_ms__read,
                .max_uint64 = acmgt2__vector_engine37__xve_inst_executed_alu1_rt_ms__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 RT MS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_RT_MS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by BTD Miss Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine37__xve_inst_executed_alu1_rt_ms_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND RT AHS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_RT_AHS",
                .desc = "Number of instructions executed by BTD Any Hit Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine37__xve_inst_executed_send_rt_ahs__read,
                .max_uint64 = acmgt2__vector_engine37__xve_inst_executed_send_rt_ahs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND RT AHS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_RT_AHS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by BTD Any Hit Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine37__xve_inst_executed_send_rt_ahs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND RT CHS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_RT_CHS",
                .desc = "Number of instructions executed by BTD Closest Hit Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine37__xve_inst_executed_send_rt_chs__read,
                .max_uint64 = acmgt2__vector_engine37__xve_inst_executed_send_rt_chs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND RT CHS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_RT_CHS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by BTD Closest Hit Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine37__xve_inst_executed_send_rt_chs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND RT MS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_RT_MS",
                .desc = "Number of instructions executed by BTD Miss Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine37__xve_inst_executed_send_rt_ms__read,
                .max_uint64 = acmgt2__vector_engine37__xve_inst_executed_send_rt_ms__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND RT MS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_RT_MS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by BTD Miss Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine37__xve_inst_executed_send_rt_ms_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 21);
}


static void
acmgt2_add_vector_engine38_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine38";
    metric_set->symbol_name = "VectorEngine38";
    metric_set->hw_config_guid = "39a71cf8-2d00-49f4-b8fb-38da2b23da30";
    metric_set->counters = calloc(23, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine38_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine38__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine38__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine38__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine38__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine38__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL ASYNC CS",
                .symbol_name = "XVE_STALL_ASYNC_CS",
                .desc = "Percentage of time in which there are Async Compute Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine38__xve_stall_async_cs__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CS",
                .symbol_name = "XVE_STALL_CS",
                .desc = "Percentage of time in which there are Compute Shader (from Render Engine) threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine38__xve_stall_cs__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES",
                .symbol_name = "XVE_STALL_CYCLES",
                .desc = "Number of cycles any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine38__xve_stall_cycles__read,
                .max_uint64 = acmgt2__vector_engine38__xve_stall_cycles__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES ASYNC CS",
                .symbol_name = "XVE_STALL_CYCLES_ASYNC_CS",
                .desc = "Number of cycles there are Async Compute Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine38__xve_stall_cycles_async_cs__read,
                .max_uint64 = acmgt2__vector_engine38__xve_stall_cycles_async_cs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES CS",
                .symbol_name = "XVE_STALL_CYCLES_CS",
                .desc = "Number of cycles there are Compute Shader (from Render Engine) threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine38__xve_stall_cycles_cs__read,
                .max_uint64 = acmgt2__vector_engine38__xve_stall_cycles_cs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES DS",
                .symbol_name = "XVE_STALL_CYCLES_DS",
                .desc = "Number of cycles there are Domain Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine38__xve_stall_cycles_ds__read,
                .max_uint64 = acmgt2__vector_engine38__xve_stall_cycles_ds__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES HS",
                .symbol_name = "XVE_STALL_CYCLES_HS",
                .desc = "Number of cycles there are Hull Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine38__xve_stall_cycles_hs__read,
                .max_uint64 = acmgt2__vector_engine38__xve_stall_cycles_hs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES MS",
                .symbol_name = "XVE_STALL_CYCLES_MS",
                .desc = "Number of cycles there are Mesh Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine38__xve_stall_cycles_ms__read,
                .max_uint64 = acmgt2__vector_engine38__xve_stall_cycles_ms__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES FS",
                .symbol_name = "XVE_STALL_CYCLES_PS",
                .desc = "Number of cycles there are Fragment Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine38__xve_stall_cycles_ps__read,
                .max_uint64 = acmgt2__vector_engine38__xve_stall_cycles_ps__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES RT",
                .symbol_name = "XVE_STALL_CYCLES_RT",
                .desc = "Number of cycles there are Ray Tracing Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine38__xve_stall_cycles_rt__read,
                .max_uint64 = acmgt2__vector_engine38__xve_stall_cycles_rt__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES TS",
                .symbol_name = "XVE_STALL_CYCLES_TS",
                .desc = "Number of cycles there are Task Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine38__xve_stall_cycles_ts__read,
                .max_uint64 = acmgt2__vector_engine38__xve_stall_cycles_ts__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES VS",
                .symbol_name = "XVE_STALL_CYCLES_VS",
                .desc = "Number of cycles there are Vertex Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine38__xve_stall_cycles_vs__read,
                .max_uint64 = acmgt2__vector_engine38__xve_stall_cycles_vs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL DS",
                .symbol_name = "XVE_STALL_DS",
                .desc = "Percentage of time in which there are Domain Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine38__xve_stall_ds__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL HS",
                .symbol_name = "XVE_STALL_HS",
                .desc = "Percentage of time in which there are Hull Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine38__xve_stall_hs__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL MS",
                .symbol_name = "XVE_STALL_MS",
                .desc = "Percentage of time in which there are Mesh Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine38__xve_stall_ms__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL FS",
                .symbol_name = "XVE_STALL_PS",
                .desc = "Percentage of time in which there are Fragment Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine38__xve_stall_ps__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL RT",
                .symbol_name = "XVE_STALL_RT",
                .desc = "Percentage of time in which there are Ray Tracing Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine38__xve_stall_rt__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL TS",
                .symbol_name = "XVE_STALL_TS",
                .desc = "Percentage of time in which there are Task Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine38__xve_stall_ts__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL VS",
                .symbol_name = "XVE_STALL_VS",
                .desc = "Percentage of time in which there are Vertex Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine38__xve_stall_vs__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 23);
}


static void
acmgt2_add_vector_engine39_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine39";
    metric_set->symbol_name = "VectorEngine39";
    metric_set->hw_config_guid = "d538856d-b249-46ab-b850-9058093d45d6";
    metric_set->counters = calloc(27, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine39_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine39__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine39__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine39__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine39__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ALL",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ALL",
                .desc = "Number of execution slots taken by instructions executed on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine39__xve_inst_executed_alu0_all__read,
                .max_uint64 = acmgt2__vector_engine39__xve_inst_executed_alu0_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine39__xve_inst_executed_alu0_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ALL",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ALL",
                .desc = "Number of execution slots taken by instructions executed on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine39__xve_inst_executed_alu1_all__read,
                .max_uint64 = acmgt2__vector_engine39__xve_inst_executed_alu1_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine39__xve_inst_executed_alu1_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED FP16",
                .symbol_name = "XVE_INST_EXECUTED_FP16",
                .desc = "Number of execution slots taken by FP16 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine39__xve_inst_executed_fp16__read,
                .max_uint64 = acmgt2__vector_engine39__xve_inst_executed_fp16__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED FP16 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_FP16_UTILIZATION",
                .desc = "Percentage of execution slots taken by FP16 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine39__xve_inst_executed_fp16_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED FP32",
                .symbol_name = "XVE_INST_EXECUTED_FP32",
                .desc = "Number of execution slots taken by FP32 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine39__xve_inst_executed_fp32__read,
                .max_uint64 = acmgt2__vector_engine39__xve_inst_executed_fp32__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED FP32 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_FP32_UTILIZATION",
                .desc = "Percentage of execution slots taken by FP32 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine39__xve_inst_executed_fp32_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED FP64",
                .symbol_name = "XVE_INST_EXECUTED_FP64",
                .desc = "The number of FLT64 instructions executed in ALU0 INT64 pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine39__xve_inst_executed_fp64__read,
                .max_uint64 = acmgt2__vector_engine39__xve_inst_executed_fp64__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED FP64 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_FP64_UTILIZATION",
                .desc = "The percentage of time in which FLT64 instruction were processed actively on FPU INT64 pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine39__xve_inst_executed_fp64_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED INT16",
                .symbol_name = "XVE_INST_EXECUTED_INT16",
                .desc = "Number of execution slots taken by INT16 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine39__xve_inst_executed_int16__read,
                .max_uint64 = acmgt2__vector_engine39__xve_inst_executed_int16__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED INT16 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_INT16_UTILIZATION",
                .desc = "Percentage of execution slots taken by INT16 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine39__xve_inst_executed_int16_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED INT32",
                .symbol_name = "XVE_INST_EXECUTED_INT32",
                .desc = "Number of execution slots taken by INT32 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine39__xve_inst_executed_int32__read,
                .max_uint64 = acmgt2__vector_engine39__xve_inst_executed_int32__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED INT32 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_INT32_UTILIZATION",
                .desc = "Percentage of execution slots taken by INT32 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine39__xve_inst_executed_int32_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED MATH",
                .symbol_name = "XVE_INST_EXECUTED_MATH",
                .desc = "Number of execution slots taken by extended math instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine39__xve_inst_executed_math__read,
                .max_uint64 = acmgt2__vector_engine39__xve_inst_executed_math__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED MATH UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_MATH_UTILIZATION",
                .desc = "Percentage of execution slots taken by extended math instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine39__xve_inst_executed_math_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX ALL",
                .symbol_name = "XVE_INST_EXECUTED_XMX_ALL",
                .desc = "Number of execution slots taken by instructions executed in XMX pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine39__xve_inst_executed_xmx_all__read,
                .max_uint64 = acmgt2__vector_engine39__xve_inst_executed_xmx_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_XMX_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed in XMX pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine39__xve_inst_executed_xmx_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX BF16",
                .symbol_name = "XVE_INST_EXECUTED_XMX_BF16",
                .desc = "Number of execution slots taken by BF16 XMX instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine39__xve_inst_executed_xmx_bf16__read,
                .max_uint64 = acmgt2__vector_engine39__xve_inst_executed_xmx_bf16__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX BF16 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_XMX_BF16_UTILIZATION",
                .desc = "Percentage of execution slots taken by BF16 XMX instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine39__xve_inst_executed_xmx_bf16_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX FP16",
                .symbol_name = "XVE_INST_EXECUTED_XMX_FP16",
                .desc = "Number of execution slots taken by FP16 XMX instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine39__xve_inst_executed_xmx_fp16__read,
                .max_uint64 = acmgt2__vector_engine39__xve_inst_executed_xmx_fp16__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX FP16 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_XMX_FP16_UTILIZATION",
                .desc = "Percentage of execution slots taken by FP16 XMX instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine39__xve_inst_executed_xmx_fp16_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX INT8",
                .symbol_name = "XVE_INST_EXECUTED_XMX_INT8",
                .desc = "Number of execution slots taken by INT8 XMX instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine39__xve_inst_executed_xmx_int8__read,
                .max_uint64 = acmgt2__vector_engine39__xve_inst_executed_xmx_int8__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX INT8 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_XMX_INT8_UTILIZATION",
                .desc = "Percentage of execution slots taken by INT8 XMX instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine39__xve_inst_executed_xmx_int8_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 27);
}


static void
acmgt2_add_vector_engine40_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine40";
    metric_set->symbol_name = "VectorEngine40";
    metric_set->hw_config_guid = "7392b735-c76c-4e4d-b936-8ec5fc8877e6";
    metric_set->counters = calloc(23, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine40_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine40__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine40__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine40__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine40__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST EXECUTED SEND ALL",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ALL",
                .desc = "Number of instructions executed on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine40__xve_inst_executed_send_all__read,
                .max_uint64 = acmgt2__vector_engine40__xve_inst_executed_send_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ALL_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine40__xve_inst_executed_send_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND ASYNC CS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ASYNC_CS",
                .desc = "Number of instructions executed by Async Compute Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine40__xve_inst_executed_send_async_cs__read,
                .max_uint64 = acmgt2__vector_engine40__xve_inst_executed_send_async_cs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND ASYNC CS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ASYNC_CS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Async Compute Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine40__xve_inst_executed_send_async_cs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND CS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_CS",
                .desc = "Number of instructions executed by Compute Shader (from Render Engine) threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine40__xve_inst_executed_send_cs__read,
                .max_uint64 = acmgt2__vector_engine40__xve_inst_executed_send_cs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND CS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_CS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Compute Shader (from Render Engine) threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine40__xve_inst_executed_send_cs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND DS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_DS",
                .desc = "Number of instructions executed by Domain Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine40__xve_inst_executed_send_ds__read,
                .max_uint64 = acmgt2__vector_engine40__xve_inst_executed_send_ds__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND DS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_DS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Domain Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine40__xve_inst_executed_send_ds_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND GS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_GS",
                .desc = "Number of instructions executed by Geometry Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine40__xve_inst_executed_send_gs__read,
                .max_uint64 = acmgt2__vector_engine40__xve_inst_executed_send_gs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND GS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_GS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Geometry Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine40__xve_inst_executed_send_gs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND HS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_HS",
                .desc = "Number of instructions executed by Hull Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine40__xve_inst_executed_send_hs__read,
                .max_uint64 = acmgt2__vector_engine40__xve_inst_executed_send_hs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND HS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_HS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Hull Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine40__xve_inst_executed_send_hs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND MS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_MS",
                .desc = "Number of instructions executed by Mesh Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine40__xve_inst_executed_send_ms__read,
                .max_uint64 = acmgt2__vector_engine40__xve_inst_executed_send_ms__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND MS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_MS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Mesh Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine40__xve_inst_executed_send_ms_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND FS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_PS",
                .desc = "Number of instructions executed by Fragment Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine40__xve_inst_executed_send_ps__read,
                .max_uint64 = acmgt2__vector_engine40__xve_inst_executed_send_ps__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND FS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_PS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Fragment Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine40__xve_inst_executed_send_ps_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND TS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_TS",
                .desc = "Number of instructions executed by Task Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine40__xve_inst_executed_send_ts__read,
                .max_uint64 = acmgt2__vector_engine40__xve_inst_executed_send_ts__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND TS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_TS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Task Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine40__xve_inst_executed_send_ts_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND VS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_VS",
                .desc = "Number of instructions executed by Vertex Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine40__xve_inst_executed_send_vs__read,
                .max_uint64 = acmgt2__vector_engine40__xve_inst_executed_send_vs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND VS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_VS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Vertex Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine40__xve_inst_executed_send_vs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 23);
}


static void
acmgt2_add_vector_engine41_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "VectorEngine41";
    metric_set->symbol_name = "VectorEngine41";
    metric_set->hw_config_guid = "02d21db0-db5d-4eae-9ffa-8fa1603ec8f2";
    metric_set->counters = calloc(17, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt2_vector_engine41_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt2__vector_engine41__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt2__vector_engine41__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt2__vector_engine41__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt2__vector_engine41__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST EXECUTED ALU0 GS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_GS",
                .desc = "Number of execution slots taken by instructions executed by Geometry Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine41__xve_inst_executed_alu0_gs__read,
                .max_uint64 = acmgt2__vector_engine41__xve_inst_executed_alu0_gs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 GS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_GS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Geometry Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine41__xve_inst_executed_alu0_gs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 MS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_MS",
                .desc = "Number of execution slots taken by instructions executed by Mesh Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine41__xve_inst_executed_alu0_ms__read,
                .max_uint64 = acmgt2__vector_engine41__xve_inst_executed_alu0_ms__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 MS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_MS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Mesh Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine41__xve_inst_executed_alu0_ms_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 TS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_TS",
                .desc = "Number of execution slots taken by instructions executed by Task Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine41__xve_inst_executed_alu0_ts__read,
                .max_uint64 = acmgt2__vector_engine41__xve_inst_executed_alu0_ts__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 TS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_TS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Task Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine41__xve_inst_executed_alu0_ts_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 GS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_GS",
                .desc = "Number of execution slots taken by instructions executed by Geometry Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine41__xve_inst_executed_alu1_gs__read,
                .max_uint64 = acmgt2__vector_engine41__xve_inst_executed_alu1_gs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 GS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_GS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Geometry Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine41__xve_inst_executed_alu1_gs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 MS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_MS",
                .desc = "Number of execution slots taken by instructions executed by Mesh Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine41__xve_inst_executed_alu1_ms__read,
                .max_uint64 = acmgt2__vector_engine41__xve_inst_executed_alu1_ms__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 MS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_MS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Mesh Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine41__xve_inst_executed_alu1_ms_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 TS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_TS",
                .desc = "Number of execution slots taken by instructions executed by Task Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine41__xve_inst_executed_alu1_ts__read,
                .max_uint64 = acmgt2__vector_engine41__xve_inst_executed_alu1_ts__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 TS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_TS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Task Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine41__xve_inst_executed_alu1_ts_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES GS",
                .symbol_name = "XVE_STALL_CYCLES_GS",
                .desc = "Number of cycles there are Geometry Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt2__vector_engine41__xve_stall_cycles_gs__read,
                .max_uint64 = acmgt2__vector_engine41__xve_stall_cycles_gs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL GS",
                .symbol_name = "XVE_STALL_GS",
                .desc = "Percentage of time in which there are Geometry Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt2__vector_engine41__xve_stall_gs__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 17);
}

void
intel_perf_load_metrics_acmgt2(struct intel_perf *perf)
{
    acmgt2_add_render_basic_metric_set(perf);
    acmgt2_add_compute_basic_metric_set(perf);
    acmgt2_add_async_compute_metric_set(perf);
    acmgt2_add_xve_activity1_metric_set(perf);
    acmgt2_add_gpu_busyness_metric_set(perf);
    acmgt2_add_render_pipe_profile1_metric_set(perf);
    acmgt2_add_render_pipe_profile2_metric_set(perf);
    acmgt2_add_render_pipe_profile3_metric_set(perf);
    acmgt2_add_render_pipe_profile4_metric_set(perf);
    acmgt2_add_l3_1_metric_set(perf);
    acmgt2_add_l3_2_metric_set(perf);
    acmgt2_add_sampler_1_metric_set(perf);
    acmgt2_add_sampler_2_metric_set(perf);
    acmgt2_add_hdc_and_sf1_metric_set(perf);
    acmgt2_add_hdc_and_sf2_metric_set(perf);
    acmgt2_add_hdc_and_sf3_metric_set(perf);
    acmgt2_add_rasterizer_and_pixel_backend1_metric_set(perf);
    acmgt2_add_rasterizer_and_pixel_backend2_metric_set(perf);
    acmgt2_add_rasterizer_and_pixel_backend3_metric_set(perf);
    acmgt2_add_tdl1_metric_set(perf);
    acmgt2_add_tdl2_metric_set(perf);
    acmgt2_add_tdl3_metric_set(perf);
    acmgt2_add_tdl4_metric_set(perf);
    acmgt2_add_tdl5_metric_set(perf);
    acmgt2_add_tdl6_metric_set(perf);
    acmgt2_add_tdl7_metric_set(perf);
    acmgt2_add_tdl8_metric_set(perf);
    acmgt2_add_test_oa_metric_set(perf);
    acmgt2_add_amfs1_metric_set(perf);
    acmgt2_add_amfs2_metric_set(perf);
    acmgt2_add_amfs3_metric_set(perf);
    acmgt2_add_amfs4_metric_set(perf);
    acmgt2_add_amfs5_metric_set(perf);
    acmgt2_add_color_pipe1_metric_set(perf);
    acmgt2_add_color_pipe2_metric_set(perf);
    acmgt2_add_color_pipe3_metric_set(perf);
    acmgt2_add_color_pipe4_metric_set(perf);
    acmgt2_add_color_pipe5_metric_set(perf);
    acmgt2_add_color_pipe6_metric_set(perf);
    acmgt2_add_color_pipe7_metric_set(perf);
    acmgt2_add_color_pipe8_metric_set(perf);
    acmgt2_add_color_pipe9_metric_set(perf);
    acmgt2_add_color_pipe10_metric_set(perf);
    acmgt2_add_color_pipe11_metric_set(perf);
    acmgt2_add_color_pipe12_metric_set(perf);
    acmgt2_add_color_pipe13_metric_set(perf);
    acmgt2_add_color_pipe14_metric_set(perf);
    acmgt2_add_color_pipe15_metric_set(perf);
    acmgt2_add_color_pipe16_metric_set(perf);
    acmgt2_add_color_pipe17_metric_set(perf);
    acmgt2_add_dataport1_metric_set(perf);
    acmgt2_add_dataport2_metric_set(perf);
    acmgt2_add_dataport3_metric_set(perf);
    acmgt2_add_dataport4_metric_set(perf);
    acmgt2_add_dataport5_metric_set(perf);
    acmgt2_add_dataport6_metric_set(perf);
    acmgt2_add_dataport7_metric_set(perf);
    acmgt2_add_dataport8_metric_set(perf);
    acmgt2_add_dataport9_metric_set(perf);
    acmgt2_add_dataport10_metric_set(perf);
    acmgt2_add_dataport11_metric_set(perf);
    acmgt2_add_dataport12_metric_set(perf);
    acmgt2_add_dataport13_metric_set(perf);
    acmgt2_add_dataport14_metric_set(perf);
    acmgt2_add_dataport15_metric_set(perf);
    acmgt2_add_dataport16_metric_set(perf);
    acmgt2_add_dataport17_metric_set(perf);
    acmgt2_add_dataport18_metric_set(perf);
    acmgt2_add_dataport19_metric_set(perf);
    acmgt2_add_dataport20_metric_set(perf);
    acmgt2_add_dataport21_metric_set(perf);
    acmgt2_add_dataport22_metric_set(perf);
    acmgt2_add_dataport23_metric_set(perf);
    acmgt2_add_dataport24_metric_set(perf);
    acmgt2_add_dataport25_metric_set(perf);
    acmgt2_add_dataport26_metric_set(perf);
    acmgt2_add_dataport27_metric_set(perf);
    acmgt2_add_dataport28_metric_set(perf);
    acmgt2_add_dataport29_metric_set(perf);
    acmgt2_add_dataport30_metric_set(perf);
    acmgt2_add_dataport31_metric_set(perf);
    acmgt2_add_dataport32_metric_set(perf);
    acmgt2_add_dataport33_metric_set(perf);
    acmgt2_add_dataport34_metric_set(perf);
    acmgt2_add_dataport35_metric_set(perf);
    acmgt2_add_dataport36_metric_set(perf);
    acmgt2_add_dataport37_metric_set(perf);
    acmgt2_add_dataport38_metric_set(perf);
    acmgt2_add_dataport39_metric_set(perf);
    acmgt2_add_dataport40_metric_set(perf);
    acmgt2_add_dataport41_metric_set(perf);
    acmgt2_add_depth_pipe1_metric_set(perf);
    acmgt2_add_depth_pipe2_metric_set(perf);
    acmgt2_add_depth_pipe3_metric_set(perf);
    acmgt2_add_depth_pipe4_metric_set(perf);
    acmgt2_add_depth_pipe5_metric_set(perf);
    acmgt2_add_depth_pipe6_metric_set(perf);
    acmgt2_add_depth_pipe7_metric_set(perf);
    acmgt2_add_depth_pipe8_metric_set(perf);
    acmgt2_add_depth_pipe9_metric_set(perf);
    acmgt2_add_depth_pipe10_metric_set(perf);
    acmgt2_add_depth_pipe11_metric_set(perf);
    acmgt2_add_depth_pipe12_metric_set(perf);
    acmgt2_add_depth_pipe13_metric_set(perf);
    acmgt2_add_depth_pipe14_metric_set(perf);
    acmgt2_add_depth_pipe15_metric_set(perf);
    acmgt2_add_depth_pipe16_metric_set(perf);
    acmgt2_add_depth_pipe17_metric_set(perf);
    acmgt2_add_depth_pipe18_metric_set(perf);
    acmgt2_add_depth_pipe19_metric_set(perf);
    acmgt2_add_depth_pipe20_metric_set(perf);
    acmgt2_add_depth_pipe21_metric_set(perf);
    acmgt2_add_depth_pipe22_metric_set(perf);
    acmgt2_add_depth_pipe23_metric_set(perf);
    acmgt2_add_depth_pipe24_metric_set(perf);
    acmgt2_add_depth_pipe25_metric_set(perf);
    acmgt2_add_depth_pipe26_metric_set(perf);
    acmgt2_add_depth_pipe27_metric_set(perf);
    acmgt2_add_depth_pipe28_metric_set(perf);
    acmgt2_add_depth_pipe29_metric_set(perf);
    acmgt2_add_depth_pipe30_metric_set(perf);
    acmgt2_add_depth_pipe31_metric_set(perf);
    acmgt2_add_depth_pipe32_metric_set(perf);
    acmgt2_add_depth_pipe33_metric_set(perf);
    acmgt2_add_depth_pipe34_metric_set(perf);
    acmgt2_add_depth_pipe35_metric_set(perf);
    acmgt2_add_depth_pipe36_metric_set(perf);
    acmgt2_add_depth_pipe37_metric_set(perf);
    acmgt2_add_depth_pipe38_metric_set(perf);
    acmgt2_add_depth_pipe39_metric_set(perf);
    acmgt2_add_depth_pipe40_metric_set(perf);
    acmgt2_add_depth_pipe41_metric_set(perf);
    acmgt2_add_depth_pipe42_metric_set(perf);
    acmgt2_add_depth_pipe43_metric_set(perf);
    acmgt2_add_depth_pipe44_metric_set(perf);
    acmgt2_add_depth_pipe45_metric_set(perf);
    acmgt2_add_depth_pipe46_metric_set(perf);
    acmgt2_add_depth_pipe47_metric_set(perf);
    acmgt2_add_depth_pipe48_metric_set(perf);
    acmgt2_add_depth_pipe49_metric_set(perf);
    acmgt2_add_depth_pipe50_metric_set(perf);
    acmgt2_add_front_end1_metric_set(perf);
    acmgt2_add_geometry1_metric_set(perf);
    acmgt2_add_geometry2_metric_set(perf);
    acmgt2_add_geometry3_metric_set(perf);
    acmgt2_add_geometry4_metric_set(perf);
    acmgt2_add_geometry5_metric_set(perf);
    acmgt2_add_l1_cache1_metric_set(perf);
    acmgt2_add_l1_cache2_metric_set(perf);
    acmgt2_add_l1_cache3_metric_set(perf);
    acmgt2_add_l1_cache4_metric_set(perf);
    acmgt2_add_l1_cache5_metric_set(perf);
    acmgt2_add_l1_cache6_metric_set(perf);
    acmgt2_add_l1_cache7_metric_set(perf);
    acmgt2_add_l1_cache8_metric_set(perf);
    acmgt2_add_l1_cache9_metric_set(perf);
    acmgt2_add_l1_cache10_metric_set(perf);
    acmgt2_add_l1_cache11_metric_set(perf);
    acmgt2_add_l1_cache12_metric_set(perf);
    acmgt2_add_l1_cache13_metric_set(perf);
    acmgt2_add_l1_cache14_metric_set(perf);
    acmgt2_add_l1_cache15_metric_set(perf);
    acmgt2_add_l1_cache16_metric_set(perf);
    acmgt2_add_l1_cache17_metric_set(perf);
    acmgt2_add_l1_cache18_metric_set(perf);
    acmgt2_add_l1_cache19_metric_set(perf);
    acmgt2_add_l1_cache20_metric_set(perf);
    acmgt2_add_l1_cache21_metric_set(perf);
    acmgt2_add_l1_cache22_metric_set(perf);
    acmgt2_add_l1_cache23_metric_set(perf);
    acmgt2_add_l1_cache24_metric_set(perf);
    acmgt2_add_l1_cache25_metric_set(perf);
    acmgt2_add_l1_cache26_metric_set(perf);
    acmgt2_add_l1_cache27_metric_set(perf);
    acmgt2_add_l1_cache28_metric_set(perf);
    acmgt2_add_l1_cache29_metric_set(perf);
    acmgt2_add_l1_cache30_metric_set(perf);
    acmgt2_add_l1_cache31_metric_set(perf);
    acmgt2_add_l1_cache32_metric_set(perf);
    acmgt2_add_l1_cache33_metric_set(perf);
    acmgt2_add_l1_cache34_metric_set(perf);
    acmgt2_add_l1_cache35_metric_set(perf);
    acmgt2_add_l1_cache36_metric_set(perf);
    acmgt2_add_l1_cache37_metric_set(perf);
    acmgt2_add_l1_cache38_metric_set(perf);
    acmgt2_add_l1_cache39_metric_set(perf);
    acmgt2_add_l1_cache40_metric_set(perf);
    acmgt2_add_l1_cache41_metric_set(perf);
    acmgt2_add_l1_cache42_metric_set(perf);
    acmgt2_add_l1_cache43_metric_set(perf);
    acmgt2_add_l1_cache44_metric_set(perf);
    acmgt2_add_l1_cache45_metric_set(perf);
    acmgt2_add_l1_cache46_metric_set(perf);
    acmgt2_add_l1_cache47_metric_set(perf);
    acmgt2_add_l1_cache48_metric_set(perf);
    acmgt2_add_l1_cache49_metric_set(perf);
    acmgt2_add_l1_cache50_metric_set(perf);
    acmgt2_add_l1_cache51_metric_set(perf);
    acmgt2_add_l1_cache52_metric_set(perf);
    acmgt2_add_l1_cache53_metric_set(perf);
    acmgt2_add_l1_cache54_metric_set(perf);
    acmgt2_add_l1_cache55_metric_set(perf);
    acmgt2_add_l1_cache56_metric_set(perf);
    acmgt2_add_l1_cache57_metric_set(perf);
    acmgt2_add_l1_cache58_metric_set(perf);
    acmgt2_add_l1_cache59_metric_set(perf);
    acmgt2_add_l1_cache60_metric_set(perf);
    acmgt2_add_l1_cache61_metric_set(perf);
    acmgt2_add_l1_cache62_metric_set(perf);
    acmgt2_add_l1_cache63_metric_set(perf);
    acmgt2_add_l1_cache64_metric_set(perf);
    acmgt2_add_l1_cache65_metric_set(perf);
    acmgt2_add_l1_cache66_metric_set(perf);
    acmgt2_add_l1_cache67_metric_set(perf);
    acmgt2_add_l1_cache68_metric_set(perf);
    acmgt2_add_l1_cache69_metric_set(perf);
    acmgt2_add_l1_cache70_metric_set(perf);
    acmgt2_add_l1_cache71_metric_set(perf);
    acmgt2_add_l1_cache72_metric_set(perf);
    acmgt2_add_l1_cache73_metric_set(perf);
    acmgt2_add_l1_cache74_metric_set(perf);
    acmgt2_add_l1_cache75_metric_set(perf);
    acmgt2_add_l1_cache76_metric_set(perf);
    acmgt2_add_l1_cache77_metric_set(perf);
    acmgt2_add_l1_cache78_metric_set(perf);
    acmgt2_add_l1_cache79_metric_set(perf);
    acmgt2_add_l1_cache80_metric_set(perf);
    acmgt2_add_l1_cache81_metric_set(perf);
    acmgt2_add_l1_cache82_metric_set(perf);
    acmgt2_add_l1_cache83_metric_set(perf);
    acmgt2_add_l1_cache84_metric_set(perf);
    acmgt2_add_l1_cache85_metric_set(perf);
    acmgt2_add_l1_cache86_metric_set(perf);
    acmgt2_add_l1_cache87_metric_set(perf);
    acmgt2_add_l1_cache88_metric_set(perf);
    acmgt2_add_l1_cache89_metric_set(perf);
    acmgt2_add_l1_cache90_metric_set(perf);
    acmgt2_add_l1_cache91_metric_set(perf);
    acmgt2_add_l1_cache92_metric_set(perf);
    acmgt2_add_l1_cache93_metric_set(perf);
    acmgt2_add_l1_cache94_metric_set(perf);
    acmgt2_add_l1_cache95_metric_set(perf);
    acmgt2_add_l1_cache96_metric_set(perf);
    acmgt2_add_l1_cache97_metric_set(perf);
    acmgt2_add_l1_cache98_metric_set(perf);
    acmgt2_add_l1_cache99_metric_set(perf);
    acmgt2_add_l1_cache100_metric_set(perf);
    acmgt2_add_l1_cache101_metric_set(perf);
    acmgt2_add_l1_cache102_metric_set(perf);
    acmgt2_add_l1_cache103_metric_set(perf);
    acmgt2_add_l1_cache104_metric_set(perf);
    acmgt2_add_l1_cache105_metric_set(perf);
    acmgt2_add_l1_cache106_metric_set(perf);
    acmgt2_add_l1_cache107_metric_set(perf);
    acmgt2_add_l1_cache108_metric_set(perf);
    acmgt2_add_l1_cache109_metric_set(perf);
    acmgt2_add_l1_cache110_metric_set(perf);
    acmgt2_add_l1_cache111_metric_set(perf);
    acmgt2_add_l1_cache112_metric_set(perf);
    acmgt2_add_l1_cache113_metric_set(perf);
    acmgt2_add_l1_cache114_metric_set(perf);
    acmgt2_add_l1_cache115_metric_set(perf);
    acmgt2_add_l1_cache116_metric_set(perf);
    acmgt2_add_l1_cache117_metric_set(perf);
    acmgt2_add_l1_cache118_metric_set(perf);
    acmgt2_add_l1_cache119_metric_set(perf);
    acmgt2_add_l1_cache120_metric_set(perf);
    acmgt2_add_l1_cache121_metric_set(perf);
    acmgt2_add_l1_cache122_metric_set(perf);
    acmgt2_add_l1_cache123_metric_set(perf);
    acmgt2_add_l1_cache124_metric_set(perf);
    acmgt2_add_l1_cache125_metric_set(perf);
    acmgt2_add_l1_cache126_metric_set(perf);
    acmgt2_add_l1_cache127_metric_set(perf);
    acmgt2_add_l1_cache128_metric_set(perf);
    acmgt2_add_l1_cache129_metric_set(perf);
    acmgt2_add_l1_cache130_metric_set(perf);
    acmgt2_add_l1_cache131_metric_set(perf);
    acmgt2_add_l1_cache132_metric_set(perf);
    acmgt2_add_l1_cache133_metric_set(perf);
    acmgt2_add_l1_cache134_metric_set(perf);
    acmgt2_add_l1_cache135_metric_set(perf);
    acmgt2_add_l1_cache136_metric_set(perf);
    acmgt2_add_l1_cache137_metric_set(perf);
    acmgt2_add_l1_cache138_metric_set(perf);
    acmgt2_add_l1_cache139_metric_set(perf);
    acmgt2_add_l1_cache140_metric_set(perf);
    acmgt2_add_l1_cache141_metric_set(perf);
    acmgt2_add_l1_cache142_metric_set(perf);
    acmgt2_add_l1_cache143_metric_set(perf);
    acmgt2_add_l1_cache144_metric_set(perf);
    acmgt2_add_l1_cache145_metric_set(perf);
    acmgt2_add_l1_cache146_metric_set(perf);
    acmgt2_add_l1_cache147_metric_set(perf);
    acmgt2_add_l1_cache148_metric_set(perf);
    acmgt2_add_l1_cache149_metric_set(perf);
    acmgt2_add_l1_cache150_metric_set(perf);
    acmgt2_add_l1_cache151_metric_set(perf);
    acmgt2_add_l1_cache152_metric_set(perf);
    acmgt2_add_l1_cache153_metric_set(perf);
    acmgt2_add_l1_cache154_metric_set(perf);
    acmgt2_add_l1_cache155_metric_set(perf);
    acmgt2_add_l1_cache156_metric_set(perf);
    acmgt2_add_l3_cache1_metric_set(perf);
    acmgt2_add_l3_cache2_metric_set(perf);
    acmgt2_add_l3_cache3_metric_set(perf);
    acmgt2_add_l3_cache4_metric_set(perf);
    acmgt2_add_l3_cache5_metric_set(perf);
    acmgt2_add_l3_cache6_metric_set(perf);
    acmgt2_add_l3_cache7_metric_set(perf);
    acmgt2_add_l3_cache8_metric_set(perf);
    acmgt2_add_l3_cache9_metric_set(perf);
    acmgt2_add_l3_cache10_metric_set(perf);
    acmgt2_add_l3_cache11_metric_set(perf);
    acmgt2_add_l3_cache12_metric_set(perf);
    acmgt2_add_l3_cache13_metric_set(perf);
    acmgt2_add_l3_cache14_metric_set(perf);
    acmgt2_add_l3_cache15_metric_set(perf);
    acmgt2_add_l3_cache16_metric_set(perf);
    acmgt2_add_l3_cache17_metric_set(perf);
    acmgt2_add_l3_cache18_metric_set(perf);
    acmgt2_add_l3_cache19_metric_set(perf);
    acmgt2_add_l3_cache20_metric_set(perf);
    acmgt2_add_l3_cache21_metric_set(perf);
    acmgt2_add_l3_cache22_metric_set(perf);
    acmgt2_add_memory1_metric_set(perf);
    acmgt2_add_memory2_metric_set(perf);
    acmgt2_add_memory3_metric_set(perf);
    acmgt2_add_memory4_metric_set(perf);
    acmgt2_add_memory5_metric_set(perf);
    acmgt2_add_memory6_metric_set(perf);
    acmgt2_add_memory7_metric_set(perf);
    acmgt2_add_memory8_metric_set(perf);
    acmgt2_add_memory9_metric_set(perf);
    acmgt2_add_memory10_metric_set(perf);
    acmgt2_add_memory11_metric_set(perf);
    acmgt2_add_memory12_metric_set(perf);
    acmgt2_add_memory13_metric_set(perf);
    acmgt2_add_memory14_metric_set(perf);
    acmgt2_add_rasterizer1_metric_set(perf);
    acmgt2_add_rasterizer2_metric_set(perf);
    acmgt2_add_ray_tracing1_metric_set(perf);
    acmgt2_add_ray_tracing2_metric_set(perf);
    acmgt2_add_ray_tracing3_metric_set(perf);
    acmgt2_add_ray_tracing4_metric_set(perf);
    acmgt2_add_ray_tracing5_metric_set(perf);
    acmgt2_add_ray_tracing6_metric_set(perf);
    acmgt2_add_ray_tracing7_metric_set(perf);
    acmgt2_add_ray_tracing8_metric_set(perf);
    acmgt2_add_ray_tracing9_metric_set(perf);
    acmgt2_add_ray_tracing10_metric_set(perf);
    acmgt2_add_ray_tracing11_metric_set(perf);
    acmgt2_add_ray_tracing12_metric_set(perf);
    acmgt2_add_ray_tracing13_metric_set(perf);
    acmgt2_add_ray_tracing14_metric_set(perf);
    acmgt2_add_ray_tracing15_metric_set(perf);
    acmgt2_add_ray_tracing16_metric_set(perf);
    acmgt2_add_ray_tracing17_metric_set(perf);
    acmgt2_add_ray_tracing18_metric_set(perf);
    acmgt2_add_ray_tracing19_metric_set(perf);
    acmgt2_add_ray_tracing20_metric_set(perf);
    acmgt2_add_ray_tracing21_metric_set(perf);
    acmgt2_add_ray_tracing22_metric_set(perf);
    acmgt2_add_ray_tracing23_metric_set(perf);
    acmgt2_add_ray_tracing24_metric_set(perf);
    acmgt2_add_ray_tracing25_metric_set(perf);
    acmgt2_add_ray_tracing26_metric_set(perf);
    acmgt2_add_ray_tracing27_metric_set(perf);
    acmgt2_add_ray_tracing28_metric_set(perf);
    acmgt2_add_ray_tracing29_metric_set(perf);
    acmgt2_add_ray_tracing30_metric_set(perf);
    acmgt2_add_ray_tracing31_metric_set(perf);
    acmgt2_add_ray_tracing32_metric_set(perf);
    acmgt2_add_ray_tracing33_metric_set(perf);
    acmgt2_add_ray_tracing34_metric_set(perf);
    acmgt2_add_ray_tracing35_metric_set(perf);
    acmgt2_add_ray_tracing36_metric_set(perf);
    acmgt2_add_ray_tracing37_metric_set(perf);
    acmgt2_add_ray_tracing38_metric_set(perf);
    acmgt2_add_ray_tracing39_metric_set(perf);
    acmgt2_add_ray_tracing40_metric_set(perf);
    acmgt2_add_ray_tracing41_metric_set(perf);
    acmgt2_add_ray_tracing42_metric_set(perf);
    acmgt2_add_ray_tracing43_metric_set(perf);
    acmgt2_add_ray_tracing44_metric_set(perf);
    acmgt2_add_ray_tracing45_metric_set(perf);
    acmgt2_add_ray_tracing46_metric_set(perf);
    acmgt2_add_ray_tracing47_metric_set(perf);
    acmgt2_add_ray_tracing48_metric_set(perf);
    acmgt2_add_ray_tracing49_metric_set(perf);
    acmgt2_add_ray_tracing50_metric_set(perf);
    acmgt2_add_ray_tracing51_metric_set(perf);
    acmgt2_add_ray_tracing52_metric_set(perf);
    acmgt2_add_ray_tracing53_metric_set(perf);
    acmgt2_add_ray_tracing54_metric_set(perf);
    acmgt2_add_ray_tracing55_metric_set(perf);
    acmgt2_add_ray_tracing56_metric_set(perf);
    acmgt2_add_ray_tracing57_metric_set(perf);
    acmgt2_add_ray_tracing58_metric_set(perf);
    acmgt2_add_ray_tracing59_metric_set(perf);
    acmgt2_add_ray_tracing60_metric_set(perf);
    acmgt2_add_ray_tracing61_metric_set(perf);
    acmgt2_add_ray_tracing62_metric_set(perf);
    acmgt2_add_ray_tracing63_metric_set(perf);
    acmgt2_add_ray_tracing64_metric_set(perf);
    acmgt2_add_ray_tracing65_metric_set(perf);
    acmgt2_add_ray_tracing66_metric_set(perf);
    acmgt2_add_ray_tracing67_metric_set(perf);
    acmgt2_add_ray_tracing68_metric_set(perf);
    acmgt2_add_ray_tracing69_metric_set(perf);
    acmgt2_add_ray_tracing70_metric_set(perf);
    acmgt2_add_ray_tracing71_metric_set(perf);
    acmgt2_add_ray_tracing72_metric_set(perf);
    acmgt2_add_ray_tracing73_metric_set(perf);
    acmgt2_add_ray_tracing74_metric_set(perf);
    acmgt2_add_ray_tracing75_metric_set(perf);
    acmgt2_add_ray_tracing76_metric_set(perf);
    acmgt2_add_ray_tracing77_metric_set(perf);
    acmgt2_add_ray_tracing78_metric_set(perf);
    acmgt2_add_sampler1_metric_set(perf);
    acmgt2_add_sampler2_metric_set(perf);
    acmgt2_add_sampler3_metric_set(perf);
    acmgt2_add_sampler4_metric_set(perf);
    acmgt2_add_sampler5_metric_set(perf);
    acmgt2_add_sampler6_metric_set(perf);
    acmgt2_add_sampler7_metric_set(perf);
    acmgt2_add_sampler8_metric_set(perf);
    acmgt2_add_sampler9_metric_set(perf);
    acmgt2_add_sampler10_metric_set(perf);
    acmgt2_add_sampler11_metric_set(perf);
    acmgt2_add_thread_dispatcher1_metric_set(perf);
    acmgt2_add_thread_dispatcher2_metric_set(perf);
    acmgt2_add_thread_dispatcher3_metric_set(perf);
    acmgt2_add_thread_dispatcher4_metric_set(perf);
    acmgt2_add_thread_dispatcher5_metric_set(perf);
    acmgt2_add_thread_dispatcher6_metric_set(perf);
    acmgt2_add_thread_dispatcher7_metric_set(perf);
    acmgt2_add_thread_dispatcher8_metric_set(perf);
    acmgt2_add_thread_dispatcher9_metric_set(perf);
    acmgt2_add_thread_dispatcher10_metric_set(perf);
    acmgt2_add_thread_dispatcher11_metric_set(perf);
    acmgt2_add_thread_dispatcher12_metric_set(perf);
    acmgt2_add_thread_dispatcher13_metric_set(perf);
    acmgt2_add_thread_dispatcher14_metric_set(perf);
    acmgt2_add_thread_dispatcher15_metric_set(perf);
    acmgt2_add_thread_dispatcher16_metric_set(perf);
    acmgt2_add_thread_dispatcher17_metric_set(perf);
    acmgt2_add_thread_dispatcher18_metric_set(perf);
    acmgt2_add_thread_dispatcher19_metric_set(perf);
    acmgt2_add_thread_dispatcher20_metric_set(perf);
    acmgt2_add_thread_dispatcher21_metric_set(perf);
    acmgt2_add_thread_dispatcher22_metric_set(perf);
    acmgt2_add_thread_dispatcher23_metric_set(perf);
    acmgt2_add_thread_dispatcher24_metric_set(perf);
    acmgt2_add_thread_dispatcher25_metric_set(perf);
    acmgt2_add_thread_dispatcher26_metric_set(perf);
    acmgt2_add_thread_dispatcher27_metric_set(perf);
    acmgt2_add_thread_dispatcher28_metric_set(perf);
    acmgt2_add_thread_dispatcher29_metric_set(perf);
    acmgt2_add_thread_dispatcher30_metric_set(perf);
    acmgt2_add_thread_dispatcher31_metric_set(perf);
    acmgt2_add_thread_dispatcher32_metric_set(perf);
    acmgt2_add_thread_dispatcher33_metric_set(perf);
    acmgt2_add_thread_dispatcher34_metric_set(perf);
    acmgt2_add_thread_dispatcher35_metric_set(perf);
    acmgt2_add_thread_dispatcher36_metric_set(perf);
    acmgt2_add_thread_dispatcher37_metric_set(perf);
    acmgt2_add_thread_dispatcher38_metric_set(perf);
    acmgt2_add_thread_dispatcher39_metric_set(perf);
    acmgt2_add_thread_dispatcher40_metric_set(perf);
    acmgt2_add_thread_dispatcher41_metric_set(perf);
    acmgt2_add_thread_dispatcher42_metric_set(perf);
    acmgt2_add_thread_dispatcher43_metric_set(perf);
    acmgt2_add_thread_dispatcher44_metric_set(perf);
    acmgt2_add_thread_dispatcher45_metric_set(perf);
    acmgt2_add_thread_dispatcher46_metric_set(perf);
    acmgt2_add_urb1_metric_set(perf);
    acmgt2_add_urb2_metric_set(perf);
    acmgt2_add_urb3_metric_set(perf);
    acmgt2_add_urb4_metric_set(perf);
    acmgt2_add_vector_engine1_metric_set(perf);
    acmgt2_add_vector_engine2_metric_set(perf);
    acmgt2_add_vector_engine3_metric_set(perf);
    acmgt2_add_vector_engine4_metric_set(perf);
    acmgt2_add_vector_engine5_metric_set(perf);
    acmgt2_add_vector_engine6_metric_set(perf);
    acmgt2_add_vector_engine7_metric_set(perf);
    acmgt2_add_vector_engine8_metric_set(perf);
    acmgt2_add_vector_engine9_metric_set(perf);
    acmgt2_add_vector_engine10_metric_set(perf);
    acmgt2_add_vector_engine11_metric_set(perf);
    acmgt2_add_vector_engine12_metric_set(perf);
    acmgt2_add_vector_engine13_metric_set(perf);
    acmgt2_add_vector_engine14_metric_set(perf);
    acmgt2_add_vector_engine15_metric_set(perf);
    acmgt2_add_vector_engine16_metric_set(perf);
    acmgt2_add_vector_engine17_metric_set(perf);
    acmgt2_add_vector_engine18_metric_set(perf);
    acmgt2_add_vector_engine19_metric_set(perf);
    acmgt2_add_vector_engine20_metric_set(perf);
    acmgt2_add_vector_engine21_metric_set(perf);
    acmgt2_add_vector_engine22_metric_set(perf);
    acmgt2_add_vector_engine23_metric_set(perf);
    acmgt2_add_vector_engine24_metric_set(perf);
    acmgt2_add_vector_engine25_metric_set(perf);
    acmgt2_add_vector_engine26_metric_set(perf);
    acmgt2_add_vector_engine27_metric_set(perf);
    acmgt2_add_vector_engine28_metric_set(perf);
    acmgt2_add_vector_engine29_metric_set(perf);
    acmgt2_add_vector_engine30_metric_set(perf);
    acmgt2_add_vector_engine31_metric_set(perf);
    acmgt2_add_vector_engine32_metric_set(perf);
    acmgt2_add_vector_engine33_metric_set(perf);
    acmgt2_add_vector_engine34_metric_set(perf);
    acmgt2_add_vector_engine35_metric_set(perf);
    acmgt2_add_vector_engine36_metric_set(perf);
    acmgt2_add_vector_engine37_metric_set(perf);
    acmgt2_add_vector_engine38_metric_set(perf);
    acmgt2_add_vector_engine39_metric_set(perf);
    acmgt2_add_vector_engine40_metric_set(perf);
    acmgt2_add_vector_engine41_metric_set(perf);
}
