/* Autogenerated file, DO NOT EDIT manually! generated by perf-metricset-codegen.py
 *
 * Copyright (c) 2018 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include <stddef.h>
#include <stdint.h>
#include <stdlib.h>
#include <stdbool.h>
#include <assert.h>

#include "i915_drm.h"

#include "i915_perf_metrics_acmgt3.h"
#include "i915_perf_equations.h"
#include "i915_perf_registers_acmgt3.h"

static bool acmgt3_render_basic_Sampler00Bottleneck_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_render_basic_Sampler00Busy_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_render_basic_SamplerBottleneck_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & 1) {
        return true;
    }
    return false;
}
static bool acmgt3_render_basic_SamplersBusy_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & 1) {
        return true;
    }
    return false;
}

static void
acmgt3_add_render_basic_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Render Metrics Basic";
    metric_set->symbol_name = "RenderBasic";
    metric_set->hw_config_guid = "47b237c5-ed48-465b-b869-0d7ef59a6982";
    metric_set->counters = calloc(40, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_render_basic_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__render_basic__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__render_basic__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CS Threads Dispatched",
                .symbol_name = "CsThreads",
                .desc = "The total number of compute shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__render_basic__cs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "DS Threads Dispatched",
                .symbol_name = "DsThreads",
                .desc = "The total number of domain shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__render_basic__ds_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "Early Depth Test Fails",
                .symbol_name = "EarlyDepthTestFails",
                .desc = "The total number of pixels dropped on early depth test.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt3__render_basic__early_depth_test_fails__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_basic__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__render_basic__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__render_basic__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS Threads Dispatched",
                .symbol_name = "GsThreads",
                .desc = "The total number of geometry shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__render_basic__gs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "GTI Read Throughput",
                .symbol_name = "GtiReadThroughput",
                .desc = "The total number of GPU memory bytes read from GTI.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__render_basic__gti_read_throughput__read,
                .max_uint64 = acmgt3__render_basic__gti_read_throughput__max,
                .group = "Memory",
            },

            {
                .name = "GTI Write Throughput",
                .symbol_name = "GtiWriteThroughput",
                .desc = "The total number of GPU memory bytes written to GTI.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__render_basic__gti_write_throughput__read,
                .max_uint64 = acmgt3__render_basic__gti_write_throughput__max,
                .group = "Memory",
            },

            {
                .name = "Early Hi-Depth Test Fails",
                .symbol_name = "HiDepthTestFails",
                .desc = "The total number of pixels dropped on early hierarchical depth test.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt3__render_basic__hi_depth_test_fails__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
            },

            {
                .name = "HS Threads Dispatched",
                .symbol_name = "HsThreads",
                .desc = "The total number of hull shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__render_basic__hs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "Pixels Failing Tests",
                .symbol_name = "PixelsFailingPostPsTests",
                .desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt3__render_basic__pixels_failing_post_ps_tests__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
            },

            {
                .name = "FS EM Pipe Active",
                .symbol_name = "PsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a fragment shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_basic__ps_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "FS FPU Pipe Active",
                .symbol_name = "PsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a fragment shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_basic__ps_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "FS Send Pipe Active",
                .symbol_name = "PsSendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing a fragment shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_basic__ps_send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "FS Threads Dispatched",
                .symbol_name = "PsThreads",
                .desc = "The total number of fragment shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__render_basic__ps_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "Rasterized Pixels",
                .symbol_name = "RasterizedPixels",
                .desc = "The total number of rasterized pixels.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt3__render_basic__rasterized_pixels__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
            },

            {
                .name = "Sampler00 Bottleneck",
                .symbol_name = "Sampler00Bottleneck",
                .desc = "The percentage of time in which Slice0 Sampler0 has been slowing down the pipe when processing XVE requests.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_basic__sampler00_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_render_basic_Sampler00Bottleneck_availability,
            },

            {
                .name = "Sampler Slice0 Xe Core0 is busy",
                .symbol_name = "Sampler00Busy",
                .desc = "The percentage of time when sampler slice0 Xe core0 is busy",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_basic__sampler00_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_render_basic_Sampler00Busy_availability,
            },

            {
                .name = "Samplers Bottleneck",
                .symbol_name = "SamplerBottleneck",
                .desc = "The percentage of time in which samplers have been slowing down the pipe when processing XVE requests.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_basic__sampler_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_render_basic_SamplerBottleneck_availability,
            },

            {
                .name = "Sampler Texels Misses",
                .symbol_name = "SamplerTexelMisses",
                .desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_TEXELS,
                .read_uint64 = acmgt3__render_basic__sampler_texel_misses__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
            },

            {
                .name = "Sampler Texels",
                .symbol_name = "SamplerTexels",
                .desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_TEXELS,
                .read_uint64 = acmgt3__render_basic__sampler_texels__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
            },

            {
                .name = "Samplers Busy",
                .symbol_name = "SamplersBusy",
                .desc = "The percentage of time in which samplers or L1 cache are not idle.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_basic__samplers_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_render_basic_SamplersBusy_availability,
            },

            {
                .name = "Samples Blended",
                .symbol_name = "SamplesBlended",
                .desc = "The total number of blended samples or pixels written to all render targets.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt3__render_basic__samples_blended__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
            },

            {
                .name = "Samples Killed in FS",
                .symbol_name = "SamplesKilledInPs",
                .desc = "The total number of samples or pixels dropped in fragment shaders.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt3__render_basic__samples_killed_in_ps__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
            },

            {
                .name = "Samples Written",
                .symbol_name = "SamplesWritten",
                .desc = "The total number of samples or pixels written to all render targets.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt3__render_basic__samples_written__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
            },

            {
                .name = "Shader Atomic Memory Accesses",
                .symbol_name = "ShaderAtomics",
                .desc = "The total number of shader atomic memory accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt3__render_basic__shader_atomics__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "Shader Barrier Messages",
                .symbol_name = "ShaderBarriers",
                .desc = "The total number of shader barrier messages.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt3__render_basic__shader_barriers__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "Shader Memory Accesses",
                .symbol_name = "ShaderMemoryAccesses",
                .desc = "The total number of shader memory accesses to L3.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt3__render_basic__shader_memory_accesses__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "SLM Bytes Read",
                .symbol_name = "SlmReads",
                .desc = "The total number of reads from shared local memory.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt3__render_basic__slm_reads__read,
                .max_uint64 = acmgt3__render_basic__slm_reads__max,
                .group = "L1Cache",
            },

            {
                .name = "SLM Writes",
                .symbol_name = "SlmWrites",
                .desc = "The total number of writes into shared local memory.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt3__render_basic__slm_writes__read,
                .max_uint64 = acmgt3__render_basic__slm_writes__max,
                .group = "L1Cache",
            },

            {
                .name = "VS EM Pipe Active",
                .symbol_name = "VsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a vertex shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_basic__vs_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "VS FPU Pipe Active",
                .symbol_name = "VsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a vertex shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_basic__vs_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "VS Send Pipe Active",
                .symbol_name = "VsSendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing a vertex shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_basic__vs_send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "VS Threads Dispatched",
                .symbol_name = "VsThreads",
                .desc = "The total number of vertex shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__render_basic__vs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "XVE Active",
                .symbol_name = "XveActive",
                .desc = "The percentage of time in which the Execution Units were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_basic__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "EM And FPU Pipes Active",
                .symbol_name = "XveFpuEmActive",
                .desc = "The percentage of time in which XVE EM INT and FPU INT64 pipelines were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_basic__xve_fpu_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Stall",
                .symbol_name = "XveStall",
                .desc = "The percentage of time in which the Execution Units were stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_basic__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Thread Occupancy",
                .symbol_name = "XveThreadOccupancy",
                .desc = "The percentage of time in which hardware threads occupied XVEs.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_basic__xve_thread_occupancy__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 40);
}


static void
acmgt3_add_compute_basic_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Compute Metrics Basic";
    metric_set->symbol_name = "ComputeBasic";
    metric_set->hw_config_guid = "1643fb69-a674-4438-8b44-840e988877bd";
    metric_set->counters = calloc(27, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_compute_basic_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__compute_basic__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__compute_basic__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CS Threads Dispatched",
                .symbol_name = "CsThreads",
                .desc = "The total number of compute shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__compute_basic__cs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "EM Pipe Active",
                .symbol_name = "EmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__compute_basic__em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE FPU Pipe Active",
                .symbol_name = "FpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__compute_basic__fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__compute_basic__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__compute_basic__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__compute_basic__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GTI Read Throughput",
                .symbol_name = "GtiReadThroughput",
                .desc = "The total number of GPU memory bytes read from GTI.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__compute_basic__gti_read_throughput__read,
                .max_uint64 = acmgt3__compute_basic__gti_read_throughput__max,
                .group = "Memory",
            },

            {
                .name = "GTI Write Throughput",
                .symbol_name = "GtiWriteThroughput",
                .desc = "The total number of GPU memory bytes written to GTI.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__compute_basic__gti_write_throughput__read,
                .max_uint64 = acmgt3__compute_basic__gti_write_throughput__max,
                .group = "Memory",
            },

            {
                .name = "Sampler Texels Misses",
                .symbol_name = "SamplerTexelMisses",
                .desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_TEXELS,
                .read_uint64 = acmgt3__compute_basic__sampler_texel_misses__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
            },

            {
                .name = "Sampler Texels",
                .symbol_name = "SamplerTexels",
                .desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_TEXELS,
                .read_uint64 = acmgt3__compute_basic__sampler_texels__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
            },

            {
                .name = "Send Pipe Active",
                .symbol_name = "SendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__compute_basic__send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "Shader Atomic Memory Accesses",
                .symbol_name = "ShaderAtomics",
                .desc = "The total number of shader atomic memory accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt3__compute_basic__shader_atomics__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "Shader Barrier Messages",
                .symbol_name = "ShaderBarriers",
                .desc = "The total number of shader barrier messages.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt3__compute_basic__shader_barriers__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "Shader Memory Accesses",
                .symbol_name = "ShaderMemoryAccesses",
                .desc = "The total number of shader memory accesses to L3.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt3__compute_basic__shader_memory_accesses__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "SLM Bytes Read",
                .symbol_name = "SlmReads",
                .desc = "The total number of reads from shared local memory.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt3__compute_basic__slm_reads__read,
                .max_uint64 = acmgt3__compute_basic__slm_reads__max,
                .group = "L1Cache",
            },

            {
                .name = "SLM Writes",
                .symbol_name = "SlmWrites",
                .desc = "The total number of writes into shared local memory.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt3__compute_basic__slm_writes__read,
                .max_uint64 = acmgt3__compute_basic__slm_writes__max,
                .group = "L1Cache",
            },

            {
                .name = "XMX Pipe Active",
                .symbol_name = "XmxActive",
                .desc = "The percentage of time in which XVE XMX pipeline was actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__compute_basic__xmx_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Active",
                .symbol_name = "XveActive",
                .desc = "The percentage of time in which the Execution Units were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__compute_basic__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE AVG IPC Rate",
                .symbol_name = "XveAvgIpcRate",
                .desc = "The average rate of IPC calculated for 2 FPU pipelines.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NUMBER,
                .read_float = acmgt3__compute_basic__xve_avg_ipc_rate__read,
                .max_float = acmgt3__compute_basic__xve_avg_ipc_rate__max,
                .group = "VectorEngine",
            },

            {
                .name = "EM And FPU Pipes Active",
                .symbol_name = "XveFpuEmActive",
                .desc = "The percentage of time in which XVE EM INT and FPU INT64 pipelines were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__compute_basic__xve_fpu_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "FPU FLT16 Instruction",
                .symbol_name = "XveFpuFlt16",
                .desc = "The percentage of time in which FLT16 instruction were processed actively on FPU INT64 pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__compute_basic__xve_fpu_flt16__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "FPU FLT32 Instruction",
                .symbol_name = "XveFpuFlt32",
                .desc = "The percentage of time in which FLT32 instruction were processed actively on FPU INT64 pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__compute_basic__xve_fpu_flt32__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "FPU FLT64 Instruction",
                .symbol_name = "XveFpuFlt64",
                .desc = "The percentage of time in which FLT64 instruction were processed actively on FPU INT64 pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__compute_basic__xve_fpu_flt64__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XMX And FPU Pipes Active",
                .symbol_name = "XveFpuXmxActive",
                .desc = "The percentage of time in which XVE XMX and FPU INT64 pipelines were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__compute_basic__xve_fpu_xmx_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Stall",
                .symbol_name = "XveStall",
                .desc = "The percentage of time in which the Execution Units were stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__compute_basic__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Thread Occupancy",
                .symbol_name = "XveThreadOccupancy",
                .desc = "The percentage of time in which hardware threads occupied XVEs.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__compute_basic__xve_thread_occupancy__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 27);
}


static void
acmgt3_add_async_compute_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "AsyncCompute";
    metric_set->symbol_name = "AsyncCompute";
    metric_set->hw_config_guid = "a4b6cfe0-e514-49d2-857c-38f3487ea62a";
    metric_set->counters = calloc(23, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_async_compute_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC CS EM Pipe Active",
                .symbol_name = "AsyncCsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a compute shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__async_compute__async_cs_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "ASYNC CS FPU Pipe Active",
                .symbol_name = "AsyncCsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a compute shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__async_compute__async_cs_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__async_compute__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__async_compute__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CS EM Pipe Active",
                .symbol_name = "CsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a compute shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__async_compute__cs_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "CS FPU Pipe Active",
                .symbol_name = "CsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a compute shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__async_compute__cs_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "CS Threads Dispatched",
                .symbol_name = "CsThreads",
                .desc = "The total number of compute shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__async_compute__cs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "DS Threads Dispatched",
                .symbol_name = "DsThreads",
                .desc = "The total number of domain shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__async_compute__ds_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "EM Pipe Active",
                .symbol_name = "EmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__async_compute__em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE FPU Pipe Active",
                .symbol_name = "FpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__async_compute__fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__async_compute__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__async_compute__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__async_compute__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS Threads Dispatched",
                .symbol_name = "GsThreads",
                .desc = "The total number of geometry shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__async_compute__gs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "HS Threads Dispatched",
                .symbol_name = "HsThreads",
                .desc = "The total number of hull shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__async_compute__hs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "FS EM Pipe Active",
                .symbol_name = "PsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a fragment shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__async_compute__ps_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "FS FPU Pipe Active",
                .symbol_name = "PsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a fragment shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__async_compute__ps_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "FS Threads Dispatched",
                .symbol_name = "PsThreads",
                .desc = "The total number of fragment shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__async_compute__ps_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "VS EM Pipe Active",
                .symbol_name = "VsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a vertex shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__async_compute__vs_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "VS FPU Pipe Active",
                .symbol_name = "VsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a vertex shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__async_compute__vs_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "VS Threads Dispatched",
                .symbol_name = "VsThreads",
                .desc = "The total number of vertex shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__async_compute__vs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "XVE Active",
                .symbol_name = "XveActive",
                .desc = "The percentage of time in which the Execution Units were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__async_compute__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Stall",
                .symbol_name = "XveStall",
                .desc = "The percentage of time in which the Execution Units were stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__async_compute__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Thread Occupancy",
                .symbol_name = "XveThreadOccupancy",
                .desc = "The percentage of time in which hardware threads occupied XVEs.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__async_compute__xve_thread_occupancy__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 23);
}


static void
acmgt3_add_xve_activity1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "XveActivity1";
    metric_set->symbol_name = "XveActivity1";
    metric_set->hw_config_guid = "026653d5-37d2-4970-bffd-b1c64dc03dec";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_xve_activity1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__xve_activity1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__xve_activity1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CS Send Pipe Active",
                .symbol_name = "CsSendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing a compute shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__xve_activity1__cs_send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "CS Threads Dispatched",
                .symbol_name = "CsThreads",
                .desc = "The total number of compute shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__xve_activity1__cs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "DS EM Pipe Active",
                .symbol_name = "DsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a domain shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__xve_activity1__ds_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "DS FPU Pipe Active",
                .symbol_name = "DsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a domain shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__xve_activity1__ds_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "DS Send Pipe Active",
                .symbol_name = "DsSendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing a domain shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__xve_activity1__ds_send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "DS Threads Dispatched",
                .symbol_name = "DsThreads",
                .desc = "The total number of domain shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__xve_activity1__ds_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__xve_activity1__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__xve_activity1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__xve_activity1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS EM Pipe Active",
                .symbol_name = "GsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a geometry shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__xve_activity1__gs_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "GS FPU Pipe Active",
                .symbol_name = "GsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a geometry shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__xve_activity1__gs_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "GS Send Pipe Active",
                .symbol_name = "GsSendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing a geometry shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__xve_activity1__gs_send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "GS Threads Dispatched",
                .symbol_name = "GsThreads",
                .desc = "The total number of geometry shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__xve_activity1__gs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "HS EM Pipe Active",
                .symbol_name = "HsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a hull shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__xve_activity1__hs_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "HS FPU Pipe Active",
                .symbol_name = "HsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a hull shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__xve_activity1__hs_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "HS Send Pipe Active",
                .symbol_name = "HsSendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing a hull shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__xve_activity1__hs_send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "HS Threads Dispatched",
                .symbol_name = "HsThreads",
                .desc = "The total number of hull shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__xve_activity1__hs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "FS Threads Dispatched",
                .symbol_name = "PsThreads",
                .desc = "The total number of fragment shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__xve_activity1__ps_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "VS Threads Dispatched",
                .symbol_name = "VsThreads",
                .desc = "The total number of vertex shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__xve_activity1__vs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}


static void
acmgt3_add_gpu_busyness_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "GpuBusyness";
    metric_set->symbol_name = "GpuBusyness";
    metric_set->hw_config_guid = "a20872dc-9d91-4ec5-966b-3ae75cb581b7";
    metric_set->counters = calloc(25, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_gpu_busyness_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "Any compute engine busy",
                .symbol_name = "AnyComputeEngineBusy",
                .desc = "The percentage of time when any compute engine is busy",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__gpu_busyness__any_compute_engine_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__gpu_busyness__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__gpu_busyness__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "Blitter Ring Busy",
                .symbol_name = "BlitterBusy",
                .desc = "The percentage of time when blitter command streamer was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__gpu_busyness__blitter_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "ComputeEngine0 Ring Busy",
                .symbol_name = "ComputeEngine0Busy",
                .desc = "The percentage of time when compute command streamer 0 was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__gpu_busyness__compute_engine0_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "ComputeEngine1 Ring Busy",
                .symbol_name = "ComputeEngine1Busy",
                .desc = "The percentage of time when compute command streamer 1 was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__gpu_busyness__compute_engine1_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "ComputeEngine2 Ring Busy",
                .symbol_name = "ComputeEngine2Busy",
                .desc = "The percentage of time when compute command streamer 2 was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__gpu_busyness__compute_engine2_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "ComputeEngine3 Ring Busy",
                .symbol_name = "ComputeEngine3Busy",
                .desc = "The percentage of time when compute command streamer 3 was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__gpu_busyness__compute_engine3_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "CS Threads Dispatched",
                .symbol_name = "CsThreads",
                .desc = "The total number of compute shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__gpu_busyness__cs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "DS Threads Dispatched",
                .symbol_name = "DsThreads",
                .desc = "The total number of domain shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__gpu_busyness__ds_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__gpu_busyness__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__gpu_busyness__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__gpu_busyness__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS Threads Dispatched",
                .symbol_name = "GsThreads",
                .desc = "The total number of geometry shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__gpu_busyness__gs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "HS Threads Dispatched",
                .symbol_name = "HsThreads",
                .desc = "The total number of hull shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__gpu_busyness__hs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "FS Threads Dispatched",
                .symbol_name = "PsThreads",
                .desc = "The total number of fragment shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__gpu_busyness__ps_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "Render and any compute engines are simultaneously busy",
                .symbol_name = "RenderAndAnyComputeEngineBusy",
                .desc = "The percentage of time when render and any compute engines are simultaneously busy",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__gpu_busyness__render_and_any_compute_engine_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "Render Ring Busy",
                .symbol_name = "RenderBusy",
                .desc = "The percentage of time when render command streamer was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__gpu_busyness__render_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "Vdbox00 Ring Busy",
                .symbol_name = "Vdbox00Busy",
                .desc = "The percentage of time when vdbox00 command streamer was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__gpu_busyness__vdbox00_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "Media",
            },

            {
                .name = "Vdbox10 Ring Busy",
                .symbol_name = "Vdbox10Busy",
                .desc = "The percentage of time when vdbox10 command streamer was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__gpu_busyness__vdbox10_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "Media",
            },

            {
                .name = "Vebox0 Ring Busy",
                .symbol_name = "Vebox0Busy",
                .desc = "The percentage of time when vebox0 command streamer was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__gpu_busyness__vebox0_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "Media",
            },

            {
                .name = "Vebox1 Ring Busy",
                .symbol_name = "Vebox1Busy",
                .desc = "The percentage of time when vebox1 command streamer was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__gpu_busyness__vebox1_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "Media",
            },

            {
                .name = "VS Threads Dispatched",
                .symbol_name = "VsThreads",
                .desc = "The total number of vertex shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__gpu_busyness__vs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "XVE Active",
                .symbol_name = "XveActive",
                .desc = "The percentage of time in which the Execution Units were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__gpu_busyness__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Stall",
                .symbol_name = "XveStall",
                .desc = "The percentage of time in which the Execution Units were stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__gpu_busyness__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Thread Occupancy",
                .symbol_name = "XveThreadOccupancy",
                .desc = "The percentage of time in which hardware threads occupied XVEs.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__gpu_busyness__xve_thread_occupancy__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 25);
}


static void
acmgt3_add_test_oa_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set TestOa";
    metric_set->symbol_name = "TestOa";
    metric_set->hw_config_guid = "7389b9c9-de73-468d-83a8-b27776215e6b";
    metric_set->counters = calloc(13, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_test_oa_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__test_oa__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__test_oa__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "TestCounter0",
                .symbol_name = "Counter0",
                .desc = "HW test counter 0. Factor: 0.0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__test_oa__counter0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter1",
                .symbol_name = "Counter1",
                .desc = "HW test counter 1. Factor: 1.0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__test_oa__counter1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter2",
                .symbol_name = "Counter2",
                .desc = "HW test counter 2. Factor: 1.0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__test_oa__counter2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter3",
                .symbol_name = "Counter3",
                .desc = "HW test counter 3. Factor: 0.5",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__test_oa__counter3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter4",
                .symbol_name = "Counter4",
                .desc = "HW test counter 4. Factor: 0.3333",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__test_oa__counter4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter5",
                .symbol_name = "Counter5",
                .desc = "HW test counter 5. Factor: 0.3333",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__test_oa__counter5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter6",
                .symbol_name = "Counter6",
                .desc = "HW test counter 6. Factor: 0.16666",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__test_oa__counter6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter7",
                .symbol_name = "Counter7",
                .desc = "HW test counter 7. Factor: 0.6666",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__test_oa__counter7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter8",
                .symbol_name = "Counter8",
                .desc = "HW test counter 8. Should be equal to 1 in IOStream or in OAG query mode",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__test_oa__counter8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter9 - OAR enable",
                .symbol_name = "Counter9",
                .desc = "HW test counter 9. Should be equal to 1 in query.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__test_oa__counter9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__test_oa__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__test_oa__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 13);
}

static bool acmgt3_hdc_and_sf__slice01_NonSamplerShader00AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice01_NonSamplerShader01AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice01_NonSamplerShader02AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice01_NonSamplerShader03AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice01_NonSamplerShader10AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice01_NonSamplerShader11AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice01_NonSamplerShader12AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice01_NonSamplerShader13AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_hdc_and_sf__slice01_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set HDCAndSF for Slice01";
    metric_set->symbol_name = "HDCAndSF_Slice01";
    metric_set->hw_config_guid = "ba8ef361-332f-42f2-9c66-f8531db5e511";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_hdc_and_sf__slice01_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__hdc_and_sf__slice01__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__hdc_and_sf__slice01__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice01__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__hdc_and_sf__slice01__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__hdc_and_sf__slice01__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice0 Xe Core0 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader00AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Xe Core0)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice01__non_sampler_shader00_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice01_NonSamplerShader00AccessStalledOnL3_availability,
            },

            {
                .name = "Slice0 Xe Core1 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader01AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Xe Core1)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice01__non_sampler_shader01_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice01_NonSamplerShader01AccessStalledOnL3_availability,
            },

            {
                .name = "Slice0 Xe Core2 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader02AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Xe Core2)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice01__non_sampler_shader02_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice01_NonSamplerShader02AccessStalledOnL3_availability,
            },

            {
                .name = "Slice0 Xe Core3 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader03AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Xe Core3)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice01__non_sampler_shader03_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice01_NonSamplerShader03AccessStalledOnL3_availability,
            },

            {
                .name = "Slice1 Xe Core0 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader10AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice1 Xe Core0)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice01__non_sampler_shader10_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice01_NonSamplerShader10AccessStalledOnL3_availability,
            },

            {
                .name = "Slice1 Xe Core1 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader11AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice1 Xe Core1)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice01__non_sampler_shader11_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice01_NonSamplerShader11AccessStalledOnL3_availability,
            },

            {
                .name = "Slice1 Xe Core2 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader12AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice1 Xe Core2)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice01__non_sampler_shader12_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice01_NonSamplerShader12AccessStalledOnL3_availability,
            },

            {
                .name = "Slice1 Xe Core3 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader13AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice1 Xe Core3)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice01__non_sampler_shader13_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice01_NonSamplerShader13AccessStalledOnL3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt3_hdc_and_sf__slice23_NonSamplerShader20AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice23_NonSamplerShader21AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice23_NonSamplerShader22AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice23_NonSamplerShader23AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice23_NonSamplerShader30AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice23_NonSamplerShader31AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice23_NonSamplerShader32AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice23_NonSamplerShader33AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_hdc_and_sf__slice23_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set HDCAndSF for Slice23";
    metric_set->symbol_name = "HDCAndSF_Slice23";
    metric_set->hw_config_guid = "a950a603-f683-4f26-a83d-a7ebbe218afb";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_hdc_and_sf__slice23_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__hdc_and_sf__slice23__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__hdc_and_sf__slice23__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice23__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__hdc_and_sf__slice23__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__hdc_and_sf__slice23__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice2 Xe Core0 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader20AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice2 Xe Core0)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice23__non_sampler_shader20_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice23_NonSamplerShader20AccessStalledOnL3_availability,
            },

            {
                .name = "Slice2 Xe Core1 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader21AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice2 Xe Core1)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice23__non_sampler_shader21_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice23_NonSamplerShader21AccessStalledOnL3_availability,
            },

            {
                .name = "Slice2 Xe Core2 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader22AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice2 Xe Core2)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice23__non_sampler_shader22_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice23_NonSamplerShader22AccessStalledOnL3_availability,
            },

            {
                .name = "Slice2 Xe Core3 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader23AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice2 Xe Core3)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice23__non_sampler_shader23_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice23_NonSamplerShader23AccessStalledOnL3_availability,
            },

            {
                .name = "Slice3 Xe Core0 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader30AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice3 Xe Core0)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice23__non_sampler_shader30_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice23_NonSamplerShader30AccessStalledOnL3_availability,
            },

            {
                .name = "Slice3 Xe Core1 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader31AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice3 Xe Core1)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice23__non_sampler_shader31_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice23_NonSamplerShader31AccessStalledOnL3_availability,
            },

            {
                .name = "Slice3 Xe Core2 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader32AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice3 Xe Core2)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice23__non_sampler_shader32_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice23_NonSamplerShader32AccessStalledOnL3_availability,
            },

            {
                .name = "Slice3 Xe Core3 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader33AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice3 Xe Core3)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice23__non_sampler_shader33_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice23_NonSamplerShader33AccessStalledOnL3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt3_hdc_and_sf__slice45_NonSamplerShader40AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice45_NonSamplerShader41AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice45_NonSamplerShader42AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice45_NonSamplerShader43AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice45_NonSamplerShader50AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice45_NonSamplerShader51AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice45_NonSamplerShader52AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice45_NonSamplerShader53AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_hdc_and_sf__slice45_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set HDCAndSF for Slice45";
    metric_set->symbol_name = "HDCAndSF_Slice45";
    metric_set->hw_config_guid = "60f4dc32-a7b6-4301-8d34-be04b1c94e38";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_hdc_and_sf__slice45_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__hdc_and_sf__slice45__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__hdc_and_sf__slice45__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice45__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__hdc_and_sf__slice45__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__hdc_and_sf__slice45__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice4 Xe Core0 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader40AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice4 Xe Core0)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice45__non_sampler_shader40_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice45_NonSamplerShader40AccessStalledOnL3_availability,
            },

            {
                .name = "Slice4 Xe Core1 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader41AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice4 Xe Core1)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice45__non_sampler_shader41_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice45_NonSamplerShader41AccessStalledOnL3_availability,
            },

            {
                .name = "Slice4 Xe Core2 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader42AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice4 Xe Core2)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice45__non_sampler_shader42_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice45_NonSamplerShader42AccessStalledOnL3_availability,
            },

            {
                .name = "Slice4 Xe Core3 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader43AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice4 Xe Core3)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice45__non_sampler_shader43_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice45_NonSamplerShader43AccessStalledOnL3_availability,
            },

            {
                .name = "Slice5 Xe Core0 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader50AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice5 Xe Core0)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice45__non_sampler_shader50_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice45_NonSamplerShader50AccessStalledOnL3_availability,
            },

            {
                .name = "Slice5 Xe Core1 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader51AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice5 Xe Core1)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice45__non_sampler_shader51_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice45_NonSamplerShader51AccessStalledOnL3_availability,
            },

            {
                .name = "Slice5 Xe Core2 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader52AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice5 Xe Core2)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice45__non_sampler_shader52_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice45_NonSamplerShader52AccessStalledOnL3_availability,
            },

            {
                .name = "Slice5 Xe Core3 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader53AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice5 Xe Core3)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice45__non_sampler_shader53_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice45_NonSamplerShader53AccessStalledOnL3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt3_hdc_and_sf__slice67_NonSamplerShader60AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice67_NonSamplerShader61AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice67_NonSamplerShader62AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice67_NonSamplerShader63AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice67_NonSamplerShader70AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice67_NonSamplerShader71AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice67_NonSamplerShader72AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_hdc_and_sf__slice67_NonSamplerShader73AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_hdc_and_sf__slice67_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set HDCAndSF for Slice67";
    metric_set->symbol_name = "HDCAndSF_Slice67";
    metric_set->hw_config_guid = "7666a6f3-801d-4082-ab47-f534b4dad494";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_hdc_and_sf__slice67_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__hdc_and_sf__slice67__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__hdc_and_sf__slice67__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice67__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__hdc_and_sf__slice67__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__hdc_and_sf__slice67__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice6 Xe Core0 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader60AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice6 Xe Core0)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice67__non_sampler_shader60_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice67_NonSamplerShader60AccessStalledOnL3_availability,
            },

            {
                .name = "Slice6 Xe Core1 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader61AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice6 Xe Core1)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice67__non_sampler_shader61_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice67_NonSamplerShader61AccessStalledOnL3_availability,
            },

            {
                .name = "Slice6 Xe Core2 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader62AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice6 Xe Core2)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice67__non_sampler_shader62_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice67_NonSamplerShader62AccessStalledOnL3_availability,
            },

            {
                .name = "Slice6 Xe Core3 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader63AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice6 Xe Core3)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice67__non_sampler_shader63_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice67_NonSamplerShader63AccessStalledOnL3_availability,
            },

            {
                .name = "Slice7 Xe Core0 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader70AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice7 Xe Core0)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice67__non_sampler_shader70_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice67_NonSamplerShader70AccessStalledOnL3_availability,
            },

            {
                .name = "Slice7 Xe Core1 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader71AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice7 Xe Core1)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice67__non_sampler_shader71_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice67_NonSamplerShader71AccessStalledOnL3_availability,
            },

            {
                .name = "Slice7 Xe Core2 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader72AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice7 Xe Core2)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice67__non_sampler_shader72_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice67_NonSamplerShader72AccessStalledOnL3_availability,
            },

            {
                .name = "Slice7 Xe Core3 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader73AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice7 Xe Core3)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf__slice67__non_sampler_shader73_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_hdc_and_sf__slice67_NonSamplerShader73AccessStalledOnL3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}


static void
acmgt3_add_hdc_and_sf1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set HDCAndSF1";
    metric_set->symbol_name = "HDCAndSF1";
    metric_set->hw_config_guid = "5357c0dc-c0cb-4ee0-bb6e-2d0882d357a6";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_hdc_and_sf1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__hdc_and_sf1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__hdc_and_sf1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "SQ00 is full",
                .symbol_name = "GTRequestQueue00Full",
                .desc = "The percentage of time when IDI0 SQ00 is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf1__gt_request_queue00_full__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "SQ10 is full",
                .symbol_name = "GTRequestQueue10Full",
                .desc = "The percentage of time when IDI0 SQ10 is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf1__gt_request_queue10_full__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "SQ20 is full",
                .symbol_name = "GTRequestQueue20Full",
                .desc = "The percentage of time when IDI0 SQ20 is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf1__gt_request_queue20_full__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "SQ30 is full",
                .symbol_name = "GTRequestQueue30Full",
                .desc = "The percentage of time when IDI0 SQ30 is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf1__gt_request_queue30_full__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "SQ40 is full",
                .symbol_name = "GTRequestQueue40Full",
                .desc = "The percentage of time when IDI0 SQ40 is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf1__gt_request_queue40_full__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "SQ50 is full",
                .symbol_name = "GTRequestQueue50Full",
                .desc = "The percentage of time when IDI0 SQ50 is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf1__gt_request_queue50_full__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "SQ60 is full",
                .symbol_name = "GTRequestQueue60Full",
                .desc = "The percentage of time when IDI0 SQ60 is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf1__gt_request_queue60_full__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "SQ70 is full",
                .symbol_name = "GTRequestQueue70Full",
                .desc = "The percentage of time when IDI0 SQ70 is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf1__gt_request_queue70_full__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf1__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__hdc_and_sf1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__hdc_and_sf1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Polygon (Slice0) Data Ready",
                .symbol_name = "Poly0DataReady",
                .desc = "The percentage of time in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf1__poly0_data_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Polygon (Slice1) Data Ready",
                .symbol_name = "Poly1DataReady",
                .desc = "The percentage of time in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf1__poly1_data_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Polygon (Slice2) Data Ready",
                .symbol_name = "Poly2DataReady",
                .desc = "The percentage of time in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf1__poly2_data_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Polygon (Slice3) Data Ready",
                .symbol_name = "Poly3DataReady",
                .desc = "The percentage of time in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf1__poly3_data_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Polygon (Slice4) Data Ready",
                .symbol_name = "Poly4DataReady",
                .desc = "The percentage of time in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf1__poly4_data_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Polygon (Slice5) Data Ready",
                .symbol_name = "Poly5DataReady",
                .desc = "The percentage of time in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf1__poly5_data_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Polygon (Slice6) Data Ready",
                .symbol_name = "Poly6DataReady",
                .desc = "The percentage of time in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf1__poly6_data_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Polygon (Slice7) Data Ready",
                .symbol_name = "Poly7DataReady",
                .desc = "The percentage of time in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__hdc_and_sf1__poly7_data_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}


static void
acmgt3_add_l3__slice01_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3_Slice01";
    metric_set->symbol_name = "L3_Slice01";
    metric_set->hw_config_guid = "b0c45d01-03a9-46c2-a04f-2c6a7a5d73d7";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_l3__slice01_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__l3__slice01__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__l3__slice01__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice01__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__l3__slice01__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__l3__slice01__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Quad0 L3 Bank0 Input Available",
                .symbol_name = "L30Bank0InputAvailable",
                .desc = "The percentage of time in which Quad0 L3 bank0 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice01__l30_bank0_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad0 L3 Bank0 Output Ready",
                .symbol_name = "L30Bank0OutputReady",
                .desc = "The percentage of time in which quad0 L3 bank0 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice01__l30_bank0_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad0 L3 Bank1 Input Available",
                .symbol_name = "L30Bank1InputAvailable",
                .desc = "The percentage of time in which Quad0 L3 bank1 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice01__l30_bank1_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad0 L3 Bank1 Output Ready",
                .symbol_name = "L30Bank1OutputReady",
                .desc = "The percentage of time in which quad0 L3 bank1 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice01__l30_bank1_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad0 L3 Bank2 Input Available",
                .symbol_name = "L30Bank2InputAvailable",
                .desc = "The percentage of time in which Quad0 L3 bank2 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice01__l30_bank2_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad0 L3 Bank2 Output Ready",
                .symbol_name = "L30Bank2OutputReady",
                .desc = "The percentage of time in which quad0 L3 bank2 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice01__l30_bank2_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad0 L3 Bank3 Input Available",
                .symbol_name = "L30Bank3InputAvailable",
                .desc = "The percentage of time in which Quad0 L3 bank3 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice01__l30_bank3_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad0 L3 Bank3 Output Ready",
                .symbol_name = "L30Bank3OutputReady",
                .desc = "The percentage of time in which quad0 L3 bank3 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice01__l30_bank3_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad0 L3 Bank4 Input Available",
                .symbol_name = "L30Bank4InputAvailable",
                .desc = "The percentage of time in which Quad0 L3 bank4 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice01__l30_bank4_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad0 L3 Bank4 Output Ready",
                .symbol_name = "L30Bank4OutputReady",
                .desc = "The percentage of time in which quad0 L3 bank4 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice01__l30_bank4_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad0 L3 Bank5 Input Available",
                .symbol_name = "L30Bank5InputAvailable",
                .desc = "The percentage of time in which Quad0 L3 bank5 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice01__l30_bank5_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad0 L3 Bank5 Output Ready",
                .symbol_name = "L30Bank5OutputReady",
                .desc = "The percentage of time in which quad0 L3 bank5 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice01__l30_bank5_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad0 L3 Bank6 Input Available",
                .symbol_name = "L30Bank6InputAvailable",
                .desc = "The percentage of time in which Quad0 L3 bank6 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice01__l30_bank6_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad0 L3 Bank6 Output Ready",
                .symbol_name = "L30Bank6OutputReady",
                .desc = "The percentage of time in which quad0 L3 bank6 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice01__l30_bank6_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad0 L3 Bank7 Input Available",
                .symbol_name = "L30Bank7InputAvailable",
                .desc = "The percentage of time in which Quad0 L3 bank7 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice01__l30_bank7_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad0 L3 Bank7 Output Ready",
                .symbol_name = "L30Bank7OutputReady",
                .desc = "The percentage of time in which quad0 L3 bank7 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice01__l30_bank7_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}


static void
acmgt3_add_l3__slice23_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3_Slice23";
    metric_set->symbol_name = "L3_Slice23";
    metric_set->hw_config_guid = "0c42d17c-81b7-4058-9864-65db72b70e27";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_l3__slice23_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__l3__slice23__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__l3__slice23__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice23__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__l3__slice23__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__l3__slice23__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Quad1 L3 Bank0 Input Available",
                .symbol_name = "L31Bank0InputAvailable",
                .desc = "The percentage of time in which Quad1 L3 bank0 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice23__l31_bank0_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank0 Output Ready",
                .symbol_name = "L31Bank0OutputReady",
                .desc = "The percentage of time in which quad1 L3 bank0 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice23__l31_bank0_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank1 Input Available",
                .symbol_name = "L31Bank1InputAvailable",
                .desc = "The percentage of time in which Quad1 L3 bank1 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice23__l31_bank1_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank1 Output Ready",
                .symbol_name = "L31Bank1OutputReady",
                .desc = "The percentage of time in which quad1 L3 bank1 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice23__l31_bank1_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank2 Input Available",
                .symbol_name = "L31Bank2InputAvailable",
                .desc = "The percentage of time in which Quad1 L3 bank2 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice23__l31_bank2_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank2 Output Ready",
                .symbol_name = "L31Bank2OutputReady",
                .desc = "The percentage of time in which quad1 L3 bank2 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice23__l31_bank2_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank3 Input Available",
                .symbol_name = "L31Bank3InputAvailable",
                .desc = "The percentage of time in which Quad1 L3 bank3 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice23__l31_bank3_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank3 Output Ready",
                .symbol_name = "L31Bank3OutputReady",
                .desc = "The percentage of time in which quad1 L3 bank3 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice23__l31_bank3_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank4 Input Available",
                .symbol_name = "L31Bank4InputAvailable",
                .desc = "The percentage of time in which Quad1 L3 bank4 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice23__l31_bank4_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank4 Output Ready",
                .symbol_name = "L31Bank4OutputReady",
                .desc = "The percentage of time in which quad1 L3 bank4 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice23__l31_bank4_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank5 Input Available",
                .symbol_name = "L31Bank5InputAvailable",
                .desc = "The percentage of time in which Quad1 L3 bank5 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice23__l31_bank5_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank5 Output Ready",
                .symbol_name = "L31Bank5OutputReady",
                .desc = "The percentage of time in which quad1 L3 bank5 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice23__l31_bank5_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank6 Input Available",
                .symbol_name = "L31Bank6InputAvailable",
                .desc = "The percentage of time in which Quad1 L3 bank6 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice23__l31_bank6_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank6 Output Ready",
                .symbol_name = "L31Bank6OutputReady",
                .desc = "The percentage of time in which quad1 L3 bank6 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice23__l31_bank6_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank7 Input Available",
                .symbol_name = "L31Bank7InputAvailable",
                .desc = "The percentage of time in which Quad1 L3 bank7 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice23__l31_bank7_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank7 Output Ready",
                .symbol_name = "L31Bank7OutputReady",
                .desc = "The percentage of time in which quad1 L3 bank7 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice23__l31_bank7_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}


static void
acmgt3_add_l3__slice45_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3_Slice45";
    metric_set->symbol_name = "L3_Slice45";
    metric_set->hw_config_guid = "59ce881a-3c51-45e0-96b4-3b565220f3a7";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_l3__slice45_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__l3__slice45__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__l3__slice45__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice45__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__l3__slice45__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__l3__slice45__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Quad2 L3 Bank0 Input Available",
                .symbol_name = "L32Bank0InputAvailable",
                .desc = "The percentage of time in which Quad2 L3 bank0 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice45__l32_bank0_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank0 Output Ready",
                .symbol_name = "L32Bank0OutputReady",
                .desc = "The percentage of time in which quad2 L3 bank0 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice45__l32_bank0_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank1 Input Available",
                .symbol_name = "L32Bank1InputAvailable",
                .desc = "The percentage of time in which Quad2 L3 bank1 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice45__l32_bank1_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank1 Output Ready",
                .symbol_name = "L32Bank1OutputReady",
                .desc = "The percentage of time in which quad2 L3 bank1 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice45__l32_bank1_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank2 Input Available",
                .symbol_name = "L32Bank2InputAvailable",
                .desc = "The percentage of time in which Quad2 L3 bank2 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice45__l32_bank2_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank2 Output Ready",
                .symbol_name = "L32Bank2OutputReady",
                .desc = "The percentage of time in which quad2 L3 bank2 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice45__l32_bank2_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank3 Input Available",
                .symbol_name = "L32Bank3InputAvailable",
                .desc = "The percentage of time in which Quad2 L3 bank3 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice45__l32_bank3_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank3 Output Ready",
                .symbol_name = "L32Bank3OutputReady",
                .desc = "The percentage of time in which quad2 L3 bank3 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice45__l32_bank3_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank4 Input Available",
                .symbol_name = "L32Bank4InputAvailable",
                .desc = "The percentage of time in which Quad2 L3 bank4 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice45__l32_bank4_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank4 Output Ready",
                .symbol_name = "L32Bank4OutputReady",
                .desc = "The percentage of time in which quad2 L3 bank4 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice45__l32_bank4_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank5 Input Available",
                .symbol_name = "L32Bank5InputAvailable",
                .desc = "The percentage of time in which Quad2 L3 bank5 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice45__l32_bank5_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank5 Output Ready",
                .symbol_name = "L32Bank5OutputReady",
                .desc = "The percentage of time in which quad2 L3 bank5 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice45__l32_bank5_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank6 Input Available",
                .symbol_name = "L32Bank6InputAvailable",
                .desc = "The percentage of time in which Quad2 L3 bank6 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice45__l32_bank6_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank6 Output Ready",
                .symbol_name = "L32Bank6OutputReady",
                .desc = "The percentage of time in which quad2 L3 bank6 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice45__l32_bank6_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank7 Input Available",
                .symbol_name = "L32Bank7InputAvailable",
                .desc = "The percentage of time in which Quad2 L3 bank7 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice45__l32_bank7_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad2 L3 Bank7 Output Ready",
                .symbol_name = "L32Bank7OutputReady",
                .desc = "The percentage of time in which quad2 L3 bank7 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice45__l32_bank7_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}


static void
acmgt3_add_l3__slice67_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3_Slice67";
    metric_set->symbol_name = "L3_Slice67";
    metric_set->hw_config_guid = "36b86585-1933-4c0f-9fd0-6dfe61480d8d";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_l3__slice67_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__l3__slice67__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__l3__slice67__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice67__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__l3__slice67__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__l3__slice67__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Quad3 L3 Bank0 Input Available",
                .symbol_name = "L33Bank0InputAvailable",
                .desc = "The percentage of time in which Quad3 L3 bank0 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice67__l33_bank0_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad3 L3 Bank0 Output Ready",
                .symbol_name = "L33Bank0OutputReady",
                .desc = "The percentage of time in which quad3 L3 bank0 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice67__l33_bank0_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad3 L3 Bank1 Input Available",
                .symbol_name = "L33Bank1InputAvailable",
                .desc = "The percentage of time in which Quad3 L3 bank1 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice67__l33_bank1_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad3 L3 Bank1 Output Ready",
                .symbol_name = "L33Bank1OutputReady",
                .desc = "The percentage of time in which quad3 L3 bank1 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice67__l33_bank1_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad3 L3 Bank2 Input Available",
                .symbol_name = "L33Bank2InputAvailable",
                .desc = "The percentage of time in which Quad3 L3 bank2 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice67__l33_bank2_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad3 L3 Bank2 Output Ready",
                .symbol_name = "L33Bank2OutputReady",
                .desc = "The percentage of time in which quad3 L3 bank2 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice67__l33_bank2_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad3 L3 Bank3 Input Available",
                .symbol_name = "L33Bank3InputAvailable",
                .desc = "The percentage of time in which Quad3 L3 bank3 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice67__l33_bank3_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad3 L3 Bank3 Output Ready",
                .symbol_name = "L33Bank3OutputReady",
                .desc = "The percentage of time in which quad3 L3 bank3 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice67__l33_bank3_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad3 L3 Bank4 Input Available",
                .symbol_name = "L33Bank4InputAvailable",
                .desc = "The percentage of time in which Quad3 L3 bank4 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice67__l33_bank4_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad3 L3 Bank4 Output Ready",
                .symbol_name = "L33Bank4OutputReady",
                .desc = "The percentage of time in which quad3 L3 bank4 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice67__l33_bank4_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad3 L3 Bank5 Input Available",
                .symbol_name = "L33Bank5InputAvailable",
                .desc = "The percentage of time in which Quad3 L3 bank5 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice67__l33_bank5_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad3 L3 Bank5 Output Ready",
                .symbol_name = "L33Bank5OutputReady",
                .desc = "The percentage of time in which quad3 L3 bank5 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice67__l33_bank5_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad3 L3 Bank6 Input Available",
                .symbol_name = "L33Bank6InputAvailable",
                .desc = "The percentage of time in which Quad3 L3 bank6 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice67__l33_bank6_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad3 L3 Bank6 Output Ready",
                .symbol_name = "L33Bank6OutputReady",
                .desc = "The percentage of time in which quad3 L3 bank6 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice67__l33_bank6_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad3 L3 Bank7 Input Available",
                .symbol_name = "L33Bank7InputAvailable",
                .desc = "The percentage of time in which Quad3 L3 bank7 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice67__l33_bank7_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad3 L3 Bank7 Output Ready",
                .symbol_name = "L33Bank7OutputReady",
                .desc = "The percentage of time in which quad3 L3 bank7 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l3__slice67__l33_bank7_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt3_rasterizer_and_pixel_backend1_Rasterizer0InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_rasterizer_and_pixel_backend1_Rasterizer1OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_rasterizer_and_pixel_backend1_Rasterizer2InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_rasterizer_and_pixel_backend1_Rasterizer3OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_rasterizer_and_pixel_backend1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set RasterizerAndPixelBackend1";
    metric_set->symbol_name = "RasterizerAndPixelBackend1";
    metric_set->hw_config_guid = "99a4388a-a104-4bbb-b8b2-7b827644a16b";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_rasterizer_and_pixel_backend1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend1__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__rasterizer_and_pixel_backend1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__rasterizer_and_pixel_backend1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice0 Pipe0 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData00Ready",
                .desc = "The percentage of time in which slice0  pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend1__pixel_data00_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice0 Pipe1 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData01Ready",
                .desc = "The percentage of time in which slice0  pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend1__pixel_data01_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice2 Pipe0 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData20Ready",
                .desc = "The percentage of time in which slice2  pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend1__pixel_data20_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice2 Pipe1 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData21Ready",
                .desc = "The percentage of time in which slice2  pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend1__pixel_data21_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice0 Rasterizer Input Available",
                .symbol_name = "Rasterizer0InputAvailable",
                .desc = "The percentage of time in which slice0 rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend1__rasterizer0_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_rasterizer_and_pixel_backend1_Rasterizer0InputAvailable_availability,
            },

            {
                .name = "Slice1 Rasterizer Output Ready",
                .symbol_name = "Rasterizer1OutputReady",
                .desc = "The percentage of time in which slice1 rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend1__rasterizer1_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_rasterizer_and_pixel_backend1_Rasterizer1OutputReady_availability,
            },

            {
                .name = "Slice2 Rasterizer Input Available",
                .symbol_name = "Rasterizer2InputAvailable",
                .desc = "The percentage of time in which slice2 rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend1__rasterizer2_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_rasterizer_and_pixel_backend1_Rasterizer2InputAvailable_availability,
            },

            {
                .name = "Slice3 Rasterizer Output Ready",
                .symbol_name = "Rasterizer3OutputReady",
                .desc = "The percentage of time in which slice3 rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend1__rasterizer3_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_rasterizer_and_pixel_backend1_Rasterizer3OutputReady_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt3_rasterizer_and_pixel_backend2_Rasterizer0OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_rasterizer_and_pixel_backend2_Rasterizer1InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_rasterizer_and_pixel_backend2_Rasterizer2OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_rasterizer_and_pixel_backend2_Rasterizer3InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_rasterizer_and_pixel_backend2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set RasterizerAndPixelBackend2";
    metric_set->symbol_name = "RasterizerAndPixelBackend2";
    metric_set->hw_config_guid = "c5db2948-d89c-468c-b52e-f2323a099c92";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_rasterizer_and_pixel_backend2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend2__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__rasterizer_and_pixel_backend2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__rasterizer_and_pixel_backend2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice1 Pipe0 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData10Ready",
                .desc = "The percentage of time in which slice1  pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend2__pixel_data10_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice1 Pipe1 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData11Ready",
                .desc = "The percentage of time in which slice1  pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend2__pixel_data11_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice3 Pipe0 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData30Ready",
                .desc = "The percentage of time in which slice3  pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend2__pixel_data30_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice3 Pipe1 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData31Ready",
                .desc = "The percentage of time in which slice3  pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend2__pixel_data31_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice0 Rasterizer Output Ready",
                .symbol_name = "Rasterizer0OutputReady",
                .desc = "The percentage of time in which slice0 rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend2__rasterizer0_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_rasterizer_and_pixel_backend2_Rasterizer0OutputReady_availability,
            },

            {
                .name = "Slice1 Rasterizer Input Available",
                .symbol_name = "Rasterizer1InputAvailable",
                .desc = "The percentage of time in which slice1 rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend2__rasterizer1_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_rasterizer_and_pixel_backend2_Rasterizer1InputAvailable_availability,
            },

            {
                .name = "Slice2 Rasterizer Output Ready",
                .symbol_name = "Rasterizer2OutputReady",
                .desc = "The percentage of time in which slice2 rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend2__rasterizer2_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_rasterizer_and_pixel_backend2_Rasterizer2OutputReady_availability,
            },

            {
                .name = "Slice3 Rasterizer Input Available",
                .symbol_name = "Rasterizer3InputAvailable",
                .desc = "The percentage of time in which slice3 rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend2__rasterizer3_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_rasterizer_and_pixel_backend2_Rasterizer3InputAvailable_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt3_rasterizer_and_pixel_backend3_Rasterizer4InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_rasterizer_and_pixel_backend3_Rasterizer5OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_rasterizer_and_pixel_backend3_Rasterizer6InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_rasterizer_and_pixel_backend3_Rasterizer7OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_rasterizer_and_pixel_backend3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set RasterizerAndPixelBackend3";
    metric_set->symbol_name = "RasterizerAndPixelBackend3";
    metric_set->hw_config_guid = "d8d668a7-3468-4ff2-84ab-f285b2468295";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_rasterizer_and_pixel_backend3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__rasterizer_and_pixel_backend3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__rasterizer_and_pixel_backend3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend3__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__rasterizer_and_pixel_backend3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__rasterizer_and_pixel_backend3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice4 Pipe0 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData40Ready",
                .desc = "The percentage of time in which slice4  pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend3__pixel_data40_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice4 Pipe1 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData41Ready",
                .desc = "The percentage of time in which slice4  pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend3__pixel_data41_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice6 Pipe0 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData60Ready",
                .desc = "The percentage of time in which slice6  pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend3__pixel_data60_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice6 Pipe1 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData61Ready",
                .desc = "The percentage of time in which slice6  pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend3__pixel_data61_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice4 Rasterizer Input Available",
                .symbol_name = "Rasterizer4InputAvailable",
                .desc = "The percentage of time in which slice4 rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend3__rasterizer4_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_rasterizer_and_pixel_backend3_Rasterizer4InputAvailable_availability,
            },

            {
                .name = "Slice5 Rasterizer Output Ready",
                .symbol_name = "Rasterizer5OutputReady",
                .desc = "The percentage of time in which slice5 rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend3__rasterizer5_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_rasterizer_and_pixel_backend3_Rasterizer5OutputReady_availability,
            },

            {
                .name = "Slice6 Rasterizer Input Available",
                .symbol_name = "Rasterizer6InputAvailable",
                .desc = "The percentage of time in which slice6 rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend3__rasterizer6_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_rasterizer_and_pixel_backend3_Rasterizer6InputAvailable_availability,
            },

            {
                .name = "Slice7 Rasterizer Output Ready",
                .symbol_name = "Rasterizer7OutputReady",
                .desc = "The percentage of time in which slice7 rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend3__rasterizer7_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_rasterizer_and_pixel_backend3_Rasterizer7OutputReady_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt3_rasterizer_and_pixel_backend4_Rasterizer4OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_rasterizer_and_pixel_backend4_Rasterizer5InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_rasterizer_and_pixel_backend4_Rasterizer6OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_rasterizer_and_pixel_backend4_Rasterizer7InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_rasterizer_and_pixel_backend4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set RasterizerAndPixelBackend4";
    metric_set->symbol_name = "RasterizerAndPixelBackend4";
    metric_set->hw_config_guid = "0c4bf00d-3ee4-4804-9f61-5b78f9810d6b";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_rasterizer_and_pixel_backend4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__rasterizer_and_pixel_backend4__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__rasterizer_and_pixel_backend4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend4__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__rasterizer_and_pixel_backend4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__rasterizer_and_pixel_backend4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice5 Pipe0 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData50Ready",
                .desc = "The percentage of time in which slice5  pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend4__pixel_data50_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice5 Pipe1 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData51Ready",
                .desc = "The percentage of time in which slice5  pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend4__pixel_data51_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice7 Pipe0 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData70Ready",
                .desc = "The percentage of time in which slice7  pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend4__pixel_data70_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice7 Pipe1 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData71Ready",
                .desc = "The percentage of time in which slice7  pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend4__pixel_data71_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice4 Rasterizer Output Ready",
                .symbol_name = "Rasterizer4OutputReady",
                .desc = "The percentage of time in which slice4 rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend4__rasterizer4_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_rasterizer_and_pixel_backend4_Rasterizer4OutputReady_availability,
            },

            {
                .name = "Slice5 Rasterizer Input Available",
                .symbol_name = "Rasterizer5InputAvailable",
                .desc = "The percentage of time in which slice5 rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend4__rasterizer5_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_rasterizer_and_pixel_backend4_Rasterizer5InputAvailable_availability,
            },

            {
                .name = "Slice6 Rasterizer Output Ready",
                .symbol_name = "Rasterizer6OutputReady",
                .desc = "The percentage of time in which slice6 rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend4__rasterizer6_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_rasterizer_and_pixel_backend4_Rasterizer6OutputReady_availability,
            },

            {
                .name = "Slice7 Rasterizer Input Available",
                .symbol_name = "Rasterizer7InputAvailable",
                .desc = "The percentage of time in which slice7 rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend4__rasterizer7_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_rasterizer_and_pixel_backend4_Rasterizer7InputAvailable_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}


static void
acmgt3_add_rasterizer_and_pixel_backend5_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "RasterizerAndPixelBackend5";
    metric_set->symbol_name = "RasterizerAndPixelBackend5";
    metric_set->hw_config_guid = "0eef4659-956d-4a4e-840c-dca20176165a";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_rasterizer_and_pixel_backend5_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__rasterizer_and_pixel_backend5__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__rasterizer_and_pixel_backend5__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend5__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__rasterizer_and_pixel_backend5__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__rasterizer_and_pixel_backend5__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PS00 Output Available",
                .symbol_name = "PSOutput00Available",
                .desc = "The percentage of time in which PS00 output is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend5__ps_output00_available__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "PS01 Output Available",
                .symbol_name = "PSOutput01Available",
                .desc = "The percentage of time in which PS01 output is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend5__ps_output01_available__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "PS10 Output Available",
                .symbol_name = "PSOutput10Available",
                .desc = "The percentage of time in which PS10 output is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend5__ps_output10_available__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "PS11 Output Available",
                .symbol_name = "PSOutput11Available",
                .desc = "The percentage of time in which PS11 output is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend5__ps_output11_available__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "PS20 Output Available",
                .symbol_name = "PSOutput20Available",
                .desc = "The percentage of time in which PS20 output is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend5__ps_output20_available__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "PS21 Output Available",
                .symbol_name = "PSOutput21Available",
                .desc = "The percentage of time in which PS21 output is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend5__ps_output21_available__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "PS30 Output Available",
                .symbol_name = "PSOutput30Available",
                .desc = "The percentage of time in which PS30 output is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend5__ps_output30_available__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "PS31 Output Available",
                .symbol_name = "PSOutput31Available",
                .desc = "The percentage of time in which PS31 output is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend5__ps_output31_available__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "Pixel Values 00 Ready",
                .symbol_name = "PixelValues00Ready",
                .desc = "The percentage of time in which pixel values 00 are ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend5__pixel_values00_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "Pixel Values 01 Ready",
                .symbol_name = "PixelValues01Ready",
                .desc = "The percentage of time in which pixel values 01 are ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend5__pixel_values01_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "Pixel Values 10 Ready",
                .symbol_name = "PixelValues10Ready",
                .desc = "The percentage of time in which pixel values 10 are ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend5__pixel_values10_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "Pixel Values 11 Ready",
                .symbol_name = "PixelValues11Ready",
                .desc = "The percentage of time in which pixel values 11 are ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend5__pixel_values11_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "Pixel Values 20 Ready",
                .symbol_name = "PixelValues20Ready",
                .desc = "The percentage of time in which pixel values 20 are ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend5__pixel_values20_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "Pixel Values 21 Ready",
                .symbol_name = "PixelValues21Ready",
                .desc = "The percentage of time in which pixel values 21 are ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend5__pixel_values21_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "Pixel Values 30 Ready",
                .symbol_name = "PixelValues30Ready",
                .desc = "The percentage of time in which pixel values 30 are ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend5__pixel_values30_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "Pixel Values 31 Ready",
                .symbol_name = "PixelValues31Ready",
                .desc = "The percentage of time in which pixel values 31 are ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__rasterizer_and_pixel_backend5__pixel_values31_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}


static void
acmgt3_add_render_pipe_profile__slice0_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Render Metrics for 3D Pipeline Profile";
    metric_set->symbol_name = "RenderPipeProfile_Slice0";
    metric_set->hw_config_guid = "ac9c3eb4-c49e-4297-8126-3d0a78a056f8";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_render_pipe_profile__slice0_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__render_pipe_profile__slice0__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__render_pipe_profile__slice0__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "BC00 Bottleneck",
                .symbol_name = "Bc00Bottleneck",
                .desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice0__bc00_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Clipper0 Bottleneck",
                .symbol_name = "Cl0Bottleneck",
                .desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice0__cl0_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "CL0 Stall",
                .symbol_name = "Cl0Stall",
                .desc = "The percentage of time in which clipper pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice0__cl0_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS0 Bottleneck",
                .symbol_name = "Ds0Bottleneck",
                .desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice0__ds0_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS0 Stall",
                .symbol_name = "Ds0Stall",
                .desc = "The percentage of time in which domain shader pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice0__ds0_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice0__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__render_pipe_profile__slice0__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__render_pipe_profile__slice0__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS0 Bottleneck",
                .symbol_name = "Gs0Bottleneck",
                .desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice0__gs0_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Hi-Depth00 Bottleneck",
                .symbol_name = "HiDepth00Bottleneck",
                .desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice0__hi_depth00_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "HS0 Bottleneck",
                .symbol_name = "Hs0Bottleneck",
                .desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice0__hs0_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "HS0 Stall",
                .symbol_name = "Hs0Stall",
                .desc = "The percentage of time in which hull stall pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice0__hs0_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF0 Bottleneck",
                .symbol_name = "Sf0Bottleneck",
                .desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice0__sf0_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF0 Stall",
                .symbol_name = "Sf0Stall",
                .desc = "The percentage of time in which strip-fans pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice0__sf0_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO0 Bottleneck",
                .symbol_name = "So0Bottleneck",
                .desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice0__so0_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO0 Stall",
                .symbol_name = "So0Stall",
                .desc = "The percentage of time in which stream-output pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice0__so0_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VF0 Bottleneck",
                .symbol_name = "Vf0Bottleneck",
                .desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice0__vf0_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VS0 Bottleneck",
                .symbol_name = "Vs0Bottleneck",
                .desc = "The percentage of time in which VS0 pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice0__vs0_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}


static void
acmgt3_add_render_pipe_profile__slice1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Render Metrics for 3D Pipeline Profile";
    metric_set->symbol_name = "RenderPipeProfile_Slice1";
    metric_set->hw_config_guid = "53434b4e-ae6b-457a-b337-c9ebefa86aeb";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_render_pipe_profile__slice1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__render_pipe_profile__slice1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__render_pipe_profile__slice1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "BC10 Bottleneck",
                .symbol_name = "Bc10Bottleneck",
                .desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice1__bc10_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Clipper1 Bottleneck",
                .symbol_name = "Cl1Bottleneck",
                .desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice1__cl1_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "CL1 Stall",
                .symbol_name = "Cl1Stall",
                .desc = "The percentage of time in which clipper pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice1__cl1_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS1 Bottleneck",
                .symbol_name = "Ds1Bottleneck",
                .desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice1__ds1_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS1 Stall",
                .symbol_name = "Ds1Stall",
                .desc = "The percentage of time in which domain shader pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice1__ds1_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice1__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__render_pipe_profile__slice1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__render_pipe_profile__slice1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS1 Bottleneck",
                .symbol_name = "Gs1Bottleneck",
                .desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice1__gs1_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Hi-Depth10 Bottleneck",
                .symbol_name = "HiDepth10Bottleneck",
                .desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice1__hi_depth10_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "HS1 Bottleneck",
                .symbol_name = "Hs1Bottleneck",
                .desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice1__hs1_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "HS1 Stall",
                .symbol_name = "Hs1Stall",
                .desc = "The percentage of time in which hull stall pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice1__hs1_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF1 Bottleneck",
                .symbol_name = "Sf1Bottleneck",
                .desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice1__sf1_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF1 Stall",
                .symbol_name = "Sf1Stall",
                .desc = "The percentage of time in which strip-fans pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice1__sf1_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO1 Bottleneck",
                .symbol_name = "So1Bottleneck",
                .desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice1__so1_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO1 Stall",
                .symbol_name = "So1Stall",
                .desc = "The percentage of time in which stream-output pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice1__so1_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VF1 Bottleneck",
                .symbol_name = "Vf1Bottleneck",
                .desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice1__vf1_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VS1 Bottleneck",
                .symbol_name = "Vs1Bottleneck",
                .desc = "The percentage of time in which VS1 pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice1__vs1_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}


static void
acmgt3_add_render_pipe_profile__slice2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Render Metrics for 3D Pipeline Profile";
    metric_set->symbol_name = "RenderPipeProfile_Slice2";
    metric_set->hw_config_guid = "3921cb4b-32f1-4595-b51b-531651d6d89d";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_render_pipe_profile__slice2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__render_pipe_profile__slice2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__render_pipe_profile__slice2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "BC20 Bottleneck",
                .symbol_name = "Bc20Bottleneck",
                .desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice2__bc20_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Clipper2 Bottleneck",
                .symbol_name = "Cl2Bottleneck",
                .desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice2__cl2_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "CL2 Stall",
                .symbol_name = "Cl2Stall",
                .desc = "The percentage of time in which clipper pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice2__cl2_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS2 Bottleneck",
                .symbol_name = "Ds2Bottleneck",
                .desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice2__ds2_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS2 Stall",
                .symbol_name = "Ds2Stall",
                .desc = "The percentage of time in which domain shader pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice2__ds2_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice2__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__render_pipe_profile__slice2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__render_pipe_profile__slice2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS2 Bottleneck",
                .symbol_name = "Gs2Bottleneck",
                .desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice2__gs2_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Hi-Depth20 Bottleneck",
                .symbol_name = "HiDepth20Bottleneck",
                .desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice2__hi_depth20_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "HS2 Bottleneck",
                .symbol_name = "Hs2Bottleneck",
                .desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice2__hs2_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "HS2 Stall",
                .symbol_name = "Hs2Stall",
                .desc = "The percentage of time in which hull stall pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice2__hs2_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF2 Bottleneck",
                .symbol_name = "Sf2Bottleneck",
                .desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice2__sf2_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF2 Stall",
                .symbol_name = "Sf2Stall",
                .desc = "The percentage of time in which strip-fans pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice2__sf2_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO2 Bottleneck",
                .symbol_name = "So2Bottleneck",
                .desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice2__so2_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO2 Stall",
                .symbol_name = "So2Stall",
                .desc = "The percentage of time in which stream-output pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice2__so2_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VF2 Bottleneck",
                .symbol_name = "Vf2Bottleneck",
                .desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice2__vf2_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VS2 Bottleneck",
                .symbol_name = "Vs2Bottleneck",
                .desc = "The percentage of time in which VS2 pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice2__vs2_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}


static void
acmgt3_add_render_pipe_profile__slice3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Render Metrics for 3D Pipeline Profile";
    metric_set->symbol_name = "RenderPipeProfile_Slice3";
    metric_set->hw_config_guid = "47924a4a-4cbb-4c9a-a186-efd3af8acf6a";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_render_pipe_profile__slice3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__render_pipe_profile__slice3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__render_pipe_profile__slice3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "BC30 Bottleneck",
                .symbol_name = "Bc30Bottleneck",
                .desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice3__bc30_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Clipper3 Bottleneck",
                .symbol_name = "Cl3Bottleneck",
                .desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice3__cl3_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "CL3 Stall",
                .symbol_name = "Cl3Stall",
                .desc = "The percentage of time in which clipper pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice3__cl3_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS3 Bottleneck",
                .symbol_name = "Ds3Bottleneck",
                .desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice3__ds3_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS3 Stall",
                .symbol_name = "Ds3Stall",
                .desc = "The percentage of time in which domain shader pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice3__ds3_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice3__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__render_pipe_profile__slice3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__render_pipe_profile__slice3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS3 Bottleneck",
                .symbol_name = "Gs3Bottleneck",
                .desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice3__gs3_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Hi-Depth30 Bottleneck",
                .symbol_name = "HiDepth30Bottleneck",
                .desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice3__hi_depth30_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "HS3 Bottleneck",
                .symbol_name = "Hs3Bottleneck",
                .desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice3__hs3_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "HS3 Stall",
                .symbol_name = "Hs3Stall",
                .desc = "The percentage of time in which hull stall pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice3__hs3_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF3 Bottleneck",
                .symbol_name = "Sf3Bottleneck",
                .desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice3__sf3_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF3 Stall",
                .symbol_name = "Sf3Stall",
                .desc = "The percentage of time in which strip-fans pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice3__sf3_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO3 Bottleneck",
                .symbol_name = "So3Bottleneck",
                .desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice3__so3_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO3 Stall",
                .symbol_name = "So3Stall",
                .desc = "The percentage of time in which stream-output pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice3__so3_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VF3 Bottleneck",
                .symbol_name = "Vf3Bottleneck",
                .desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice3__vf3_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VS3 Bottleneck",
                .symbol_name = "Vs3Bottleneck",
                .desc = "The percentage of time in which VS3 pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice3__vs3_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}


static void
acmgt3_add_render_pipe_profile__slice4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Render Metrics for 3D Pipeline Profile";
    metric_set->symbol_name = "RenderPipeProfile_Slice4";
    metric_set->hw_config_guid = "ee1b4183-c89c-4bad-a11d-b91b60769895";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_render_pipe_profile__slice4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__render_pipe_profile__slice4__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__render_pipe_profile__slice4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "BC40 Bottleneck",
                .symbol_name = "Bc40Bottleneck",
                .desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice4__bc40_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Clipper4 Bottleneck",
                .symbol_name = "Cl4Bottleneck",
                .desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice4__cl4_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "CL4 Stall",
                .symbol_name = "Cl4Stall",
                .desc = "The percentage of time in which clipper pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice4__cl4_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS4 Bottleneck",
                .symbol_name = "Ds4Bottleneck",
                .desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice4__ds4_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS4 Stall",
                .symbol_name = "Ds4Stall",
                .desc = "The percentage of time in which domain shader pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice4__ds4_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice4__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__render_pipe_profile__slice4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__render_pipe_profile__slice4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS4 Bottleneck",
                .symbol_name = "Gs4Bottleneck",
                .desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice4__gs4_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Hi-Depth40 Bottleneck",
                .symbol_name = "HiDepth40Bottleneck",
                .desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice4__hi_depth40_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "HS4 Bottleneck",
                .symbol_name = "Hs4Bottleneck",
                .desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice4__hs4_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "HS4 Stall",
                .symbol_name = "Hs4Stall",
                .desc = "The percentage of time in which hull stall pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice4__hs4_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF4 Bottleneck",
                .symbol_name = "Sf4Bottleneck",
                .desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice4__sf4_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF4 Stall",
                .symbol_name = "Sf4Stall",
                .desc = "The percentage of time in which strip-fans pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice4__sf4_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO4 Bottleneck",
                .symbol_name = "So4Bottleneck",
                .desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice4__so4_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO4 Stall",
                .symbol_name = "So4Stall",
                .desc = "The percentage of time in which stream-output pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice4__so4_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VF4 Bottleneck",
                .symbol_name = "Vf4Bottleneck",
                .desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice4__vf4_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VS4 Bottleneck",
                .symbol_name = "Vs4Bottleneck",
                .desc = "The percentage of time in which VS4 pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice4__vs4_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}


static void
acmgt3_add_render_pipe_profile__slice5_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Render Metrics for 3D Pipeline Profile";
    metric_set->symbol_name = "RenderPipeProfile_Slice5";
    metric_set->hw_config_guid = "a1534029-affd-453e-b8d9-2931505c5288";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_render_pipe_profile__slice5_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__render_pipe_profile__slice5__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__render_pipe_profile__slice5__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "BC50 Bottleneck",
                .symbol_name = "Bc50Bottleneck",
                .desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice5__bc50_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Clipper5 Bottleneck",
                .symbol_name = "Cl5Bottleneck",
                .desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice5__cl5_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "CL5 Stall",
                .symbol_name = "Cl5Stall",
                .desc = "The percentage of time in which clipper pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice5__cl5_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS5 Bottleneck",
                .symbol_name = "Ds5Bottleneck",
                .desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice5__ds5_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS5 Stall",
                .symbol_name = "Ds5Stall",
                .desc = "The percentage of time in which domain shader pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice5__ds5_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice5__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__render_pipe_profile__slice5__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__render_pipe_profile__slice5__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS5 Bottleneck",
                .symbol_name = "Gs5Bottleneck",
                .desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice5__gs5_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Hi-Depth50 Bottleneck",
                .symbol_name = "HiDepth50Bottleneck",
                .desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice5__hi_depth50_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "HS5 Bottleneck",
                .symbol_name = "Hs5Bottleneck",
                .desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice5__hs5_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "HS5 Stall",
                .symbol_name = "Hs5Stall",
                .desc = "The percentage of time in which hull stall pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice5__hs5_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF5 Bottleneck",
                .symbol_name = "Sf5Bottleneck",
                .desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice5__sf5_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF5 Stall",
                .symbol_name = "Sf5Stall",
                .desc = "The percentage of time in which strip-fans pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice5__sf5_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO5 Bottleneck",
                .symbol_name = "So5Bottleneck",
                .desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice5__so5_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO5 Stall",
                .symbol_name = "So5Stall",
                .desc = "The percentage of time in which stream-output pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice5__so5_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VF5 Bottleneck",
                .symbol_name = "Vf5Bottleneck",
                .desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice5__vf5_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VS5 Bottleneck",
                .symbol_name = "Vs5Bottleneck",
                .desc = "The percentage of time in which VS5 pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice5__vs5_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}


static void
acmgt3_add_render_pipe_profile__slice6_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Render Metrics for 3D Pipeline Profile";
    metric_set->symbol_name = "RenderPipeProfile_Slice6";
    metric_set->hw_config_guid = "26a82035-dadd-4227-a1b4-f7808081f10c";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_render_pipe_profile__slice6_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__render_pipe_profile__slice6__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__render_pipe_profile__slice6__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "BC60 Bottleneck",
                .symbol_name = "Bc60Bottleneck",
                .desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice6__bc60_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Clipper6 Bottleneck",
                .symbol_name = "Cl6Bottleneck",
                .desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice6__cl6_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "CL6 Stall",
                .symbol_name = "Cl6Stall",
                .desc = "The percentage of time in which clipper pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice6__cl6_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS6 Bottleneck",
                .symbol_name = "Ds6Bottleneck",
                .desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice6__ds6_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS6 Stall",
                .symbol_name = "Ds6Stall",
                .desc = "The percentage of time in which domain shader pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice6__ds6_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice6__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__render_pipe_profile__slice6__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__render_pipe_profile__slice6__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS6 Bottleneck",
                .symbol_name = "Gs6Bottleneck",
                .desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice6__gs6_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Hi-Depth60 Bottleneck",
                .symbol_name = "HiDepth60Bottleneck",
                .desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice6__hi_depth60_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "HS6 Bottleneck",
                .symbol_name = "Hs6Bottleneck",
                .desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice6__hs6_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "HS6 Stall",
                .symbol_name = "Hs6Stall",
                .desc = "The percentage of time in which hull stall pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice6__hs6_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF6 Bottleneck",
                .symbol_name = "Sf6Bottleneck",
                .desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice6__sf6_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF6 Stall",
                .symbol_name = "Sf6Stall",
                .desc = "The percentage of time in which strip-fans pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice6__sf6_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO6 Bottleneck",
                .symbol_name = "So6Bottleneck",
                .desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice6__so6_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO6 Stall",
                .symbol_name = "So6Stall",
                .desc = "The percentage of time in which stream-output pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice6__so6_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VF6 Bottleneck",
                .symbol_name = "Vf6Bottleneck",
                .desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice6__vf6_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VS6 Bottleneck",
                .symbol_name = "Vs6Bottleneck",
                .desc = "The percentage of time in which VS6 pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice6__vs6_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}


static void
acmgt3_add_render_pipe_profile__slice7_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Render Metrics for 3D Pipeline Profile";
    metric_set->symbol_name = "RenderPipeProfile_Slice7";
    metric_set->hw_config_guid = "71b5ebc0-874f-4ecd-b409-c387a5bb0543";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_render_pipe_profile__slice7_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__render_pipe_profile__slice7__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__render_pipe_profile__slice7__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "BC70 Bottleneck",
                .symbol_name = "Bc70Bottleneck",
                .desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice7__bc70_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Clipper7 Bottleneck",
                .symbol_name = "Cl7Bottleneck",
                .desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice7__cl7_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "CL7 Stall",
                .symbol_name = "Cl7Stall",
                .desc = "The percentage of time in which clipper pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice7__cl7_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS7 Bottleneck",
                .symbol_name = "Ds7Bottleneck",
                .desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice7__ds7_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS7 Stall",
                .symbol_name = "Ds7Stall",
                .desc = "The percentage of time in which domain shader pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice7__ds7_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice7__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__render_pipe_profile__slice7__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__render_pipe_profile__slice7__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS7 Bottleneck",
                .symbol_name = "Gs7Bottleneck",
                .desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice7__gs7_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Hi-Depth70 Bottleneck",
                .symbol_name = "HiDepth70Bottleneck",
                .desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice7__hi_depth70_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "HS7 Bottleneck",
                .symbol_name = "Hs7Bottleneck",
                .desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice7__hs7_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "HS7 Stall",
                .symbol_name = "Hs7Stall",
                .desc = "The percentage of time in which hull stall pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice7__hs7_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF7 Bottleneck",
                .symbol_name = "Sf7Bottleneck",
                .desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice7__sf7_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF7 Stall",
                .symbol_name = "Sf7Stall",
                .desc = "The percentage of time in which strip-fans pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice7__sf7_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO7 Bottleneck",
                .symbol_name = "So7Bottleneck",
                .desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice7__so7_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO7 Stall",
                .symbol_name = "So7Stall",
                .desc = "The percentage of time in which stream-output pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice7__so7_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VF7 Bottleneck",
                .symbol_name = "Vf7Bottleneck",
                .desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice7__vf7_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VS7 Bottleneck",
                .symbol_name = "Vs7Bottleneck",
                .desc = "The percentage of time in which VS7 pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__render_pipe_profile__slice7__vs7_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_sampler__slice01_Sampler00InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice01_Sampler00OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice01_Sampler01InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice01_Sampler01OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice01_Sampler02InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice01_Sampler02OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice01_Sampler03InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice01_Sampler03OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice01_Sampler10InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice01_Sampler10OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice01_Sampler11InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice01_Sampler11OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice01_Sampler12InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice01_Sampler12OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice01_Sampler13InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice01_Sampler13OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_sampler__slice01_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Sampler_Slice01";
    metric_set->symbol_name = "Sampler_Slice01";
    metric_set->hw_config_guid = "1fa63cc6-c791-42ae-9db4-4170daefe666";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_sampler__slice01_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__sampler__slice01__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__sampler__slice01__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice01__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__sampler__slice01__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__sampler__slice01__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice0 Xe Core0 Input Available",
                .symbol_name = "Sampler00InputAvailable",
                .desc = "The percentage of time in which slice0 Xe core0 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice01__sampler00_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice01_Sampler00InputAvailable_availability,
            },

            {
                .name = "Slice0 Xe Core0 Sampler Output Ready",
                .symbol_name = "Sampler00OutputReady",
                .desc = "The percentage of time in which slice0 Xe core0 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice01__sampler00_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice01_Sampler00OutputReady_availability,
            },

            {
                .name = "Slice0 Xe Core1 Input Available",
                .symbol_name = "Sampler01InputAvailable",
                .desc = "The percentage of time in which slice0 Xe core1 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice01__sampler01_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice01_Sampler01InputAvailable_availability,
            },

            {
                .name = "Slice0 Xe Core1 Sampler Output Ready",
                .symbol_name = "Sampler01OutputReady",
                .desc = "The percentage of time in which slice0 Xe core1 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice01__sampler01_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice01_Sampler01OutputReady_availability,
            },

            {
                .name = "Slice0 Xe Core2 Input Available",
                .symbol_name = "Sampler02InputAvailable",
                .desc = "The percentage of time in which slice0 Xe core2 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice01__sampler02_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice01_Sampler02InputAvailable_availability,
            },

            {
                .name = "Slice0 Xe Core2 Sampler Output Ready",
                .symbol_name = "Sampler02OutputReady",
                .desc = "The percentage of time in which slice0 Xe core2 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice01__sampler02_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice01_Sampler02OutputReady_availability,
            },

            {
                .name = "Slice0 Xe Core3 Input Available",
                .symbol_name = "Sampler03InputAvailable",
                .desc = "The percentage of time in which slice0 Xe core3 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice01__sampler03_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice01_Sampler03InputAvailable_availability,
            },

            {
                .name = "Slice0 Xe Core3 Sampler Output Ready",
                .symbol_name = "Sampler03OutputReady",
                .desc = "The percentage of time in which slice0 Xe core3 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice01__sampler03_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice01_Sampler03OutputReady_availability,
            },

            {
                .name = "Slice1 Xe Core0 Input Available",
                .symbol_name = "Sampler10InputAvailable",
                .desc = "The percentage of time in which slice1 Xe core0 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice01__sampler10_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice01_Sampler10InputAvailable_availability,
            },

            {
                .name = "Slice1 Xe Core0 Sampler Output Ready",
                .symbol_name = "Sampler10OutputReady",
                .desc = "The percentage of time in which slice1 Xe core0 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice01__sampler10_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice01_Sampler10OutputReady_availability,
            },

            {
                .name = "Slice1 Xe Core1 Input Available",
                .symbol_name = "Sampler11InputAvailable",
                .desc = "The percentage of time in which slice1 Xe core1 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice01__sampler11_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice01_Sampler11InputAvailable_availability,
            },

            {
                .name = "Slice1 Xe Core1 Sampler Output Ready",
                .symbol_name = "Sampler11OutputReady",
                .desc = "The percentage of time in which slice1 Xe core1 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice01__sampler11_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice01_Sampler11OutputReady_availability,
            },

            {
                .name = "Slice1 Xe Core2 Input Available",
                .symbol_name = "Sampler12InputAvailable",
                .desc = "The percentage of time in which slice1 Xe core2 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice01__sampler12_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice01_Sampler12InputAvailable_availability,
            },

            {
                .name = "Slice1 Xe Core2 Sampler Output Ready",
                .symbol_name = "Sampler12OutputReady",
                .desc = "The percentage of time in which slice1 Xe core2 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice01__sampler12_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice01_Sampler12OutputReady_availability,
            },

            {
                .name = "Slice1 Xe Core3 Input Available",
                .symbol_name = "Sampler13InputAvailable",
                .desc = "The percentage of time in which slice1 Xe core3 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice01__sampler13_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice01_Sampler13InputAvailable_availability,
            },

            {
                .name = "Slice1 Xe Core3 Sampler Output Ready",
                .symbol_name = "Sampler13OutputReady",
                .desc = "The percentage of time in which slice1 Xe core3 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice01__sampler13_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice01_Sampler13OutputReady_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt3_sampler__slice23_Sampler20InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice23_Sampler20OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice23_Sampler21InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice23_Sampler21OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice23_Sampler22InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice23_Sampler22OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice23_Sampler23InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice23_Sampler23OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice23_Sampler30InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice23_Sampler30OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice23_Sampler31InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice23_Sampler31OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice23_Sampler32InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice23_Sampler32OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice23_Sampler33InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice23_Sampler33OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_sampler__slice23_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Sampler_Slice23";
    metric_set->symbol_name = "Sampler_Slice23";
    metric_set->hw_config_guid = "c22bbd17-c8bd-4f7e-bb2f-4b045e41f1cb";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_sampler__slice23_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__sampler__slice23__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__sampler__slice23__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice23__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__sampler__slice23__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__sampler__slice23__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice2 Xe Core0 Input Available",
                .symbol_name = "Sampler20InputAvailable",
                .desc = "The percentage of time in which slice2 Xe core0 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice23__sampler20_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice23_Sampler20InputAvailable_availability,
            },

            {
                .name = "Slice2 Xe Core0 Sampler Output Ready",
                .symbol_name = "Sampler20OutputReady",
                .desc = "The percentage of time in which slice2 Xe core0 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice23__sampler20_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice23_Sampler20OutputReady_availability,
            },

            {
                .name = "Slice2 Xe Core1 Input Available",
                .symbol_name = "Sampler21InputAvailable",
                .desc = "The percentage of time in which slice2 Xe core1 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice23__sampler21_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice23_Sampler21InputAvailable_availability,
            },

            {
                .name = "Slice2 Xe Core1 Sampler Output Ready",
                .symbol_name = "Sampler21OutputReady",
                .desc = "The percentage of time in which slice2 Xe core1 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice23__sampler21_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice23_Sampler21OutputReady_availability,
            },

            {
                .name = "Slice2 Xe Core2 Input Available",
                .symbol_name = "Sampler22InputAvailable",
                .desc = "The percentage of time in which slice2 Xe core2 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice23__sampler22_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice23_Sampler22InputAvailable_availability,
            },

            {
                .name = "Slice2 Xe Core2 Sampler Output Ready",
                .symbol_name = "Sampler22OutputReady",
                .desc = "The percentage of time in which slice2 Xe core2 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice23__sampler22_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice23_Sampler22OutputReady_availability,
            },

            {
                .name = "Slice2 Xe Core3 Input Available",
                .symbol_name = "Sampler23InputAvailable",
                .desc = "The percentage of time in which slice2 Xe core3 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice23__sampler23_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice23_Sampler23InputAvailable_availability,
            },

            {
                .name = "Slice2 Xe Core3 Sampler Output Ready",
                .symbol_name = "Sampler23OutputReady",
                .desc = "The percentage of time in which slice2 Xe core3 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice23__sampler23_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice23_Sampler23OutputReady_availability,
            },

            {
                .name = "Slice3 Xe Core0 Input Available",
                .symbol_name = "Sampler30InputAvailable",
                .desc = "The percentage of time in which slice3 Xe core0 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice23__sampler30_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice23_Sampler30InputAvailable_availability,
            },

            {
                .name = "Slice3 Xe Core0 Sampler Output Ready",
                .symbol_name = "Sampler30OutputReady",
                .desc = "The percentage of time in which slice3 Xe core0 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice23__sampler30_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice23_Sampler30OutputReady_availability,
            },

            {
                .name = "Slice3 Xe Core1 Input Available",
                .symbol_name = "Sampler31InputAvailable",
                .desc = "The percentage of time in which slice3 Xe core1 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice23__sampler31_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice23_Sampler31InputAvailable_availability,
            },

            {
                .name = "Slice3 Xe Core1 Sampler Output Ready",
                .symbol_name = "Sampler31OutputReady",
                .desc = "The percentage of time in which slice3 Xe core1 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice23__sampler31_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice23_Sampler31OutputReady_availability,
            },

            {
                .name = "Slice3 Xe Core2 Input Available",
                .symbol_name = "Sampler32InputAvailable",
                .desc = "The percentage of time in which slice3 Xe core2 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice23__sampler32_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice23_Sampler32InputAvailable_availability,
            },

            {
                .name = "Slice3 Xe Core2 Sampler Output Ready",
                .symbol_name = "Sampler32OutputReady",
                .desc = "The percentage of time in which slice3 Xe core2 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice23__sampler32_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice23_Sampler32OutputReady_availability,
            },

            {
                .name = "Slice3 Xe Core3 Input Available",
                .symbol_name = "Sampler33InputAvailable",
                .desc = "The percentage of time in which slice3 Xe core3 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice23__sampler33_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice23_Sampler33InputAvailable_availability,
            },

            {
                .name = "Slice3 Xe Core3 Sampler Output Ready",
                .symbol_name = "Sampler33OutputReady",
                .desc = "The percentage of time in which slice3 Xe core3 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice23__sampler33_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice23_Sampler33OutputReady_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt3_sampler__slice45_Sampler40InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice45_Sampler40OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice45_Sampler41InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice45_Sampler41OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice45_Sampler42InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice45_Sampler42OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice45_Sampler43InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice45_Sampler43OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice45_Sampler50InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice45_Sampler50OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice45_Sampler51InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice45_Sampler51OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice45_Sampler52InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice45_Sampler52OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice45_Sampler53InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice45_Sampler53OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_sampler__slice45_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Sampler_Slice45";
    metric_set->symbol_name = "Sampler_Slice45";
    metric_set->hw_config_guid = "3946ded6-dff6-461a-a9cd-5291d9dcce51";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_sampler__slice45_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__sampler__slice45__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__sampler__slice45__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice45__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__sampler__slice45__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__sampler__slice45__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice4 Xe Core0 Input Available",
                .symbol_name = "Sampler40InputAvailable",
                .desc = "The percentage of time in which slice4 Xe core0 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice45__sampler40_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice45_Sampler40InputAvailable_availability,
            },

            {
                .name = "Slice4 Xe Core0 Sampler Output Ready",
                .symbol_name = "Sampler40OutputReady",
                .desc = "The percentage of time in which slice4 Xe core0 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice45__sampler40_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice45_Sampler40OutputReady_availability,
            },

            {
                .name = "Slice4 Xe Core1 Input Available",
                .symbol_name = "Sampler41InputAvailable",
                .desc = "The percentage of time in which slice4 Xe core1 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice45__sampler41_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice45_Sampler41InputAvailable_availability,
            },

            {
                .name = "Slice4 Xe Core1 Sampler Output Ready",
                .symbol_name = "Sampler41OutputReady",
                .desc = "The percentage of time in which slice4 Xe core1 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice45__sampler41_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice45_Sampler41OutputReady_availability,
            },

            {
                .name = "Slice4 Xe Core2 Input Available",
                .symbol_name = "Sampler42InputAvailable",
                .desc = "The percentage of time in which slice4 Xe core2 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice45__sampler42_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice45_Sampler42InputAvailable_availability,
            },

            {
                .name = "Slice4 Xe Core2 Sampler Output Ready",
                .symbol_name = "Sampler42OutputReady",
                .desc = "The percentage of time in which slice4 Xe core2 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice45__sampler42_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice45_Sampler42OutputReady_availability,
            },

            {
                .name = "Slice4 Xe Core3 Input Available",
                .symbol_name = "Sampler43InputAvailable",
                .desc = "The percentage of time in which slice4 Xe core3 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice45__sampler43_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice45_Sampler43InputAvailable_availability,
            },

            {
                .name = "Slice4 Xe Core3 Sampler Output Ready",
                .symbol_name = "Sampler43OutputReady",
                .desc = "The percentage of time in which slice4 Xe core3 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice45__sampler43_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice45_Sampler43OutputReady_availability,
            },

            {
                .name = "Slice5 Xe Core0 Input Available",
                .symbol_name = "Sampler50InputAvailable",
                .desc = "The percentage of time in which slice5 Xe core0 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice45__sampler50_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice45_Sampler50InputAvailable_availability,
            },

            {
                .name = "Slice5 Xe Core0 Sampler Output Ready",
                .symbol_name = "Sampler50OutputReady",
                .desc = "The percentage of time in which slice5 Xe core0 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice45__sampler50_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice45_Sampler50OutputReady_availability,
            },

            {
                .name = "Slice5 Xe Core1 Input Available",
                .symbol_name = "Sampler51InputAvailable",
                .desc = "The percentage of time in which slice5 Xe core1 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice45__sampler51_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice45_Sampler51InputAvailable_availability,
            },

            {
                .name = "Slice5 Xe Core1 Sampler Output Ready",
                .symbol_name = "Sampler51OutputReady",
                .desc = "The percentage of time in which slice5 Xe core1 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice45__sampler51_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice45_Sampler51OutputReady_availability,
            },

            {
                .name = "Slice5 Xe Core2 Input Available",
                .symbol_name = "Sampler52InputAvailable",
                .desc = "The percentage of time in which slice5 Xe core2 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice45__sampler52_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice45_Sampler52InputAvailable_availability,
            },

            {
                .name = "Slice5 Xe Core2 Sampler Output Ready",
                .symbol_name = "Sampler52OutputReady",
                .desc = "The percentage of time in which slice5 Xe core2 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice45__sampler52_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice45_Sampler52OutputReady_availability,
            },

            {
                .name = "Slice5 Xe Core3 Input Available",
                .symbol_name = "Sampler53InputAvailable",
                .desc = "The percentage of time in which slice5 Xe core3 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice45__sampler53_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice45_Sampler53InputAvailable_availability,
            },

            {
                .name = "Slice5 Xe Core3 Sampler Output Ready",
                .symbol_name = "Sampler53OutputReady",
                .desc = "The percentage of time in which slice5 Xe core3 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice45__sampler53_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice45_Sampler53OutputReady_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt3_sampler__slice67_Sampler60InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice67_Sampler60OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice67_Sampler61InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice67_Sampler61OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice67_Sampler62InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice67_Sampler62OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice67_Sampler63InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice67_Sampler63OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice67_Sampler70InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice67_Sampler70OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice67_Sampler71InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice67_Sampler71OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice67_Sampler72InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice67_Sampler72OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice67_Sampler73InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_sampler__slice67_Sampler73OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_sampler__slice67_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Sampler_Slice67";
    metric_set->symbol_name = "Sampler_Slice67";
    metric_set->hw_config_guid = "6ab037fb-065e-4f01-b24e-5f425077189c";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_sampler__slice67_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__sampler__slice67__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__sampler__slice67__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice67__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__sampler__slice67__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__sampler__slice67__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice6 Xe Core0 Input Available",
                .symbol_name = "Sampler60InputAvailable",
                .desc = "The percentage of time in which slice6 Xe core0 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice67__sampler60_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice67_Sampler60InputAvailable_availability,
            },

            {
                .name = "Slice6 Xe Core0 Sampler Output Ready",
                .symbol_name = "Sampler60OutputReady",
                .desc = "The percentage of time in which slice6 Xe core0 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice67__sampler60_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice67_Sampler60OutputReady_availability,
            },

            {
                .name = "Slice6 Xe Core1 Input Available",
                .symbol_name = "Sampler61InputAvailable",
                .desc = "The percentage of time in which slice6 Xe core1 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice67__sampler61_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice67_Sampler61InputAvailable_availability,
            },

            {
                .name = "Slice6 Xe Core1 Sampler Output Ready",
                .symbol_name = "Sampler61OutputReady",
                .desc = "The percentage of time in which slice6 Xe core1 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice67__sampler61_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice67_Sampler61OutputReady_availability,
            },

            {
                .name = "Slice6 Xe Core2 Input Available",
                .symbol_name = "Sampler62InputAvailable",
                .desc = "The percentage of time in which slice6 Xe core2 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice67__sampler62_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice67_Sampler62InputAvailable_availability,
            },

            {
                .name = "Slice6 Xe Core2 Sampler Output Ready",
                .symbol_name = "Sampler62OutputReady",
                .desc = "The percentage of time in which slice6 Xe core2 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice67__sampler62_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice67_Sampler62OutputReady_availability,
            },

            {
                .name = "Slice6 Xe Core3 Input Available",
                .symbol_name = "Sampler63InputAvailable",
                .desc = "The percentage of time in which slice6 Xe core3 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice67__sampler63_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice67_Sampler63InputAvailable_availability,
            },

            {
                .name = "Slice6 Xe Core3 Sampler Output Ready",
                .symbol_name = "Sampler63OutputReady",
                .desc = "The percentage of time in which slice6 Xe core3 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice67__sampler63_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice67_Sampler63OutputReady_availability,
            },

            {
                .name = "Slice7 Xe Core0 Input Available",
                .symbol_name = "Sampler70InputAvailable",
                .desc = "The percentage of time in which slice7 Xe core0 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice67__sampler70_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice67_Sampler70InputAvailable_availability,
            },

            {
                .name = "Slice7 Xe Core0 Sampler Output Ready",
                .symbol_name = "Sampler70OutputReady",
                .desc = "The percentage of time in which slice7 Xe core0 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice67__sampler70_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice67_Sampler70OutputReady_availability,
            },

            {
                .name = "Slice7 Xe Core1 Input Available",
                .symbol_name = "Sampler71InputAvailable",
                .desc = "The percentage of time in which slice7 Xe core1 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice67__sampler71_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice67_Sampler71InputAvailable_availability,
            },

            {
                .name = "Slice7 Xe Core1 Sampler Output Ready",
                .symbol_name = "Sampler71OutputReady",
                .desc = "The percentage of time in which slice7 Xe core1 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice67__sampler71_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice67_Sampler71OutputReady_availability,
            },

            {
                .name = "Slice7 Xe Core2 Input Available",
                .symbol_name = "Sampler72InputAvailable",
                .desc = "The percentage of time in which slice7 Xe core2 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice67__sampler72_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice67_Sampler72InputAvailable_availability,
            },

            {
                .name = "Slice7 Xe Core2 Sampler Output Ready",
                .symbol_name = "Sampler72OutputReady",
                .desc = "The percentage of time in which slice7 Xe core2 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice67__sampler72_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice67_Sampler72OutputReady_availability,
            },

            {
                .name = "Slice7 Xe Core3 Input Available",
                .symbol_name = "Sampler73InputAvailable",
                .desc = "The percentage of time in which slice7 Xe core3 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice67__sampler73_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice67_Sampler73InputAvailable_availability,
            },

            {
                .name = "Slice7 Xe Core3 Sampler Output Ready",
                .symbol_name = "Sampler73OutputReady",
                .desc = "The percentage of time in which slice7 Xe core3 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__sampler__slice67__sampler73_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_sampler__slice67_Sampler73OutputReady_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt3_tdl__slice01_1_NonPSThread00ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_1_NonPSThread01ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_1_NonPSThread02ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_1_NonPSThread03ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_1_NonPSThread10ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_1_NonPSThread11ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_1_NonPSThread12ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_1_NonPSThread13ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_1_ThreadHeader03ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_1_ThreadHeader03ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_1_ThreadHeader03ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_1_ThreadHeader03ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_1_ThreadHeader13ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_1_ThreadHeader13ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_1_ThreadHeader13ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_1_ThreadHeader13ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_tdl__slice01_1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL_Slice01_1";
    metric_set->symbol_name = "TDL_Slice01_1";
    metric_set->hw_config_guid = "f0294ed6-827a-44e0-9f79-1ddc22182899";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_tdl__slice01_1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__tdl__slice01_1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__tdl__slice01_1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_1__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__tdl__slice01_1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__tdl__slice01_1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice0 Xe Core0 Thread Dispatcher",
                .symbol_name = "NonPSThread00ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_1__non_ps_thread00_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_1_NonPSThread00ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice0 Xe Core1 Thread Dispatcher",
                .symbol_name = "NonPSThread01ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_1__non_ps_thread01_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_1_NonPSThread01ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice0 Xe Core2 Thread Dispatcher",
                .symbol_name = "NonPSThread02ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_1__non_ps_thread02_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_1_NonPSThread02ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice0 Xe Core3 Thread Dispatcher",
                .symbol_name = "NonPSThread03ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_1__non_ps_thread03_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_1_NonPSThread03ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice1 Xe Core0 Thread Dispatcher",
                .symbol_name = "NonPSThread10ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice1 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_1__non_ps_thread10_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_1_NonPSThread10ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice1 Xe Core1 Thread Dispatcher",
                .symbol_name = "NonPSThread11ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice1 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_1__non_ps_thread11_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_1_NonPSThread11ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice1 Xe Core2 Thread Dispatcher",
                .symbol_name = "NonPSThread12ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice1 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_1__non_ps_thread12_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_1_NonPSThread12ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice1 Xe Core3 Thread Dispatcher",
                .symbol_name = "NonPSThread13ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice1 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_1__non_ps_thread13_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_1_NonPSThread13ReadyForDispatch_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader03ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core3 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_1__thread_header03_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_1_ThreadHeader03ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader03ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core3 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_1__thread_header03_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_1_ThreadHeader03ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader03ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core3 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_1__thread_header03_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_1_ThreadHeader03ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader03ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core3 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_1__thread_header03_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_1_ThreadHeader03ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core3 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader13ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core3 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_1__thread_header13_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_1_ThreadHeader13ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core3 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader13ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core3 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_1__thread_header13_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_1_ThreadHeader13ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core3 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader13ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core3 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_1__thread_header13_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_1_ThreadHeader13ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core3 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader13ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core3 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_1__thread_header13_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_1_ThreadHeader13ReadyPort3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt3_tdl__slice01_2_PSThread00ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_2_PSThread01ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_2_PSThread02ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_2_PSThread03ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_2_PSThread10ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_2_PSThread11ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_2_PSThread12ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_2_PSThread13ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_tdl__slice01_2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL_Slice01_2";
    metric_set->symbol_name = "TDL_Slice01_2";
    metric_set->hw_config_guid = "14477b8c-ad25-4351-8c67-e6411cb77bab";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_tdl__slice01_2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__tdl__slice01_2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__tdl__slice01_2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_2__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__tdl__slice01_2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__tdl__slice01_2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice0 Xe Core0 Thread Dispatcher",
                .symbol_name = "PSThread00ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice0 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_2__ps_thread00_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_2_PSThread00ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice0 Xe Core1 Thread Dispatcher",
                .symbol_name = "PSThread01ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice0 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_2__ps_thread01_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_2_PSThread01ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice0 Xe Core2 Thread Dispatcher",
                .symbol_name = "PSThread02ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice0 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_2__ps_thread02_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_2_PSThread02ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice0 Xe Core3 Thread Dispatcher",
                .symbol_name = "PSThread03ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice0 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_2__ps_thread03_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_2_PSThread03ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice1 Xe Core0 Thread Dispatcher",
                .symbol_name = "PSThread10ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice1 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_2__ps_thread10_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_2_PSThread10ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice1 Xe Core1 Thread Dispatcher",
                .symbol_name = "PSThread11ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice1 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_2__ps_thread11_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_2_PSThread11ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice1 Xe Core2 Thread Dispatcher",
                .symbol_name = "PSThread12ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice1 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_2__ps_thread12_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_2_PSThread12ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice1 Xe Core3 Thread Dispatcher",
                .symbol_name = "PSThread13ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice1 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_2__ps_thread13_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_2_PSThread13ReadyForDispatch_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt3_tdl__slice01_3_ThreadHeader00Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_3_ThreadHeader00ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_3_ThreadHeader00ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_3_ThreadHeader00ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_3_ThreadHeader00ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_3_ThreadHeader01Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_3_ThreadHeader01ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_3_ThreadHeader01ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_3_ThreadHeader01ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_3_ThreadHeader01ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_3_ThreadHeader02Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_3_ThreadHeader02ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_3_ThreadHeader02ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_3_ThreadHeader02ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_3_ThreadHeader02ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_3_ThreadHeader03Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_tdl__slice01_3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL_Slice01_3";
    metric_set->symbol_name = "TDL_Slice01_3";
    metric_set->hw_config_guid = "6b48996e-1179-4955-bd28-d5aefeea1196";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_tdl__slice01_3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__tdl__slice01_3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__tdl__slice01_3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_3__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__tdl__slice01_3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__tdl__slice01_3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher",
                .symbol_name = "ThreadHeader00Ready",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_3__thread_header00_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_3_ThreadHeader00Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader00ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core0 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_3__thread_header00_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_3_ThreadHeader00ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader00ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core0 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_3__thread_header00_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_3_ThreadHeader00ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader00ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core0 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_3__thread_header00_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_3_ThreadHeader00ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader00ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core0 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_3__thread_header00_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_3_ThreadHeader00ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher",
                .symbol_name = "ThreadHeader01Ready",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_3__thread_header01_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_3_ThreadHeader01Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader01ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core1 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_3__thread_header01_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_3_ThreadHeader01ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader01ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core1 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_3__thread_header01_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_3_ThreadHeader01ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader01ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core1 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_3__thread_header01_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_3_ThreadHeader01ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader01ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core1 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_3__thread_header01_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_3_ThreadHeader01ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher",
                .symbol_name = "ThreadHeader02Ready",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_3__thread_header02_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_3_ThreadHeader02Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader02ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core2 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_3__thread_header02_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_3_ThreadHeader02ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader02ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core2 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_3__thread_header02_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_3_ThreadHeader02ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader02ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core2 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_3__thread_header02_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_3_ThreadHeader02ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader02ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core2 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_3__thread_header02_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_3_ThreadHeader02ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher",
                .symbol_name = "ThreadHeader03Ready",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_3__thread_header03_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_3_ThreadHeader03Ready_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt3_tdl__slice01_4_ThreadHeader10Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_4_ThreadHeader10ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_4_ThreadHeader10ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_4_ThreadHeader10ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_4_ThreadHeader10ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_4_ThreadHeader11Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_4_ThreadHeader11ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_4_ThreadHeader11ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_4_ThreadHeader11ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_4_ThreadHeader11ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_4_ThreadHeader12Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_4_ThreadHeader12ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_4_ThreadHeader12ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_4_ThreadHeader12ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_4_ThreadHeader12ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice01_4_ThreadHeader13Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_tdl__slice01_4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL_Slice01_4";
    metric_set->symbol_name = "TDL_Slice01_4";
    metric_set->hw_config_guid = "6403c3b2-e302-4c1a-a604-7817e846ab2c";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_tdl__slice01_4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__tdl__slice01_4__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__tdl__slice01_4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_4__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__tdl__slice01_4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__tdl__slice01_4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core0 Thread Dispatcher",
                .symbol_name = "ThreadHeader10Ready",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_4__thread_header10_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_4_ThreadHeader10Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core0 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader10ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core0 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_4__thread_header10_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_4_ThreadHeader10ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core0 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader10ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core0 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_4__thread_header10_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_4_ThreadHeader10ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core0 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader10ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core0 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_4__thread_header10_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_4_ThreadHeader10ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core0 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader10ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core0 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_4__thread_header10_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_4_ThreadHeader10ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core1 Thread Dispatcher",
                .symbol_name = "ThreadHeader11Ready",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_4__thread_header11_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_4_ThreadHeader11Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core1 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader11ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core1 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_4__thread_header11_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_4_ThreadHeader11ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core1 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader11ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core1 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_4__thread_header11_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_4_ThreadHeader11ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core1 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader11ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core1 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_4__thread_header11_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_4_ThreadHeader11ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core1 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader11ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core1 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_4__thread_header11_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_4_ThreadHeader11ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core2 Thread Dispatcher",
                .symbol_name = "ThreadHeader12Ready",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_4__thread_header12_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_4_ThreadHeader12Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core2 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader12ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core2 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_4__thread_header12_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_4_ThreadHeader12ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core2 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader12ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core2 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_4__thread_header12_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_4_ThreadHeader12ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core2 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader12ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core2 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_4__thread_header12_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_4_ThreadHeader12ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core2 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader12ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core2 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_4__thread_header12_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_4_ThreadHeader12ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core3 Thread Dispatcher",
                .symbol_name = "ThreadHeader13Ready",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice01_4__thread_header13_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice01_4_ThreadHeader13Ready_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt3_tdl__slice23_1_NonPSThread20ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_1_NonPSThread21ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_1_NonPSThread22ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_1_NonPSThread23ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_1_NonPSThread30ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_1_NonPSThread31ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_1_NonPSThread32ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_1_NonPSThread33ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_1_ThreadHeader23ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_1_ThreadHeader23ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_1_ThreadHeader23ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_1_ThreadHeader23ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_1_ThreadHeader33ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_1_ThreadHeader33ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_1_ThreadHeader33ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_1_ThreadHeader33ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_tdl__slice23_1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL_Slice23_1";
    metric_set->symbol_name = "TDL_Slice23_1";
    metric_set->hw_config_guid = "51d2c1bd-7432-411f-9095-ac97d55dc285";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_tdl__slice23_1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__tdl__slice23_1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__tdl__slice23_1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_1__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__tdl__slice23_1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__tdl__slice23_1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice2 Xe Core0 Thread Dispatcher",
                .symbol_name = "NonPSThread20ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice2 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_1__non_ps_thread20_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_1_NonPSThread20ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice2 Xe Core1 Thread Dispatcher",
                .symbol_name = "NonPSThread21ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice2 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_1__non_ps_thread21_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_1_NonPSThread21ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice2 Xe Core2 Thread Dispatcher",
                .symbol_name = "NonPSThread22ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice2 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_1__non_ps_thread22_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_1_NonPSThread22ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice2 Xe Core3 Thread Dispatcher",
                .symbol_name = "NonPSThread23ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice2 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_1__non_ps_thread23_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_1_NonPSThread23ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice3 Xe Core0 Thread Dispatcher",
                .symbol_name = "NonPSThread30ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice3 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_1__non_ps_thread30_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_1_NonPSThread30ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice3 Xe Core1 Thread Dispatcher",
                .symbol_name = "NonPSThread31ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice3 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_1__non_ps_thread31_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_1_NonPSThread31ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice3 Xe Core2 Thread Dispatcher",
                .symbol_name = "NonPSThread32ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice3 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_1__non_ps_thread32_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_1_NonPSThread32ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice3 Xe Core3 Thread Dispatcher",
                .symbol_name = "NonPSThread33ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice3 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_1__non_ps_thread33_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_1_NonPSThread33ReadyForDispatch_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader23ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_1__thread_header23_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_1_ThreadHeader23ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader23ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_1__thread_header23_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_1_ThreadHeader23ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader23ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_1__thread_header23_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_1_ThreadHeader23ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader23ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_1__thread_header23_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_1_ThreadHeader23ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader33ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_1__thread_header33_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_1_ThreadHeader33ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader33ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_1__thread_header33_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_1_ThreadHeader33ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader33ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_1__thread_header33_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_1_ThreadHeader33ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader33ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_1__thread_header33_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_1_ThreadHeader33ReadyPort3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt3_tdl__slice23_2_PSThread20ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_2_PSThread21ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_2_PSThread22ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_2_PSThread23ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_2_PSThread30ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_2_PSThread31ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_2_PSThread32ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_2_PSThread33ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_tdl__slice23_2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL_Slice23_2";
    metric_set->symbol_name = "TDL_Slice23_2";
    metric_set->hw_config_guid = "32e32945-471f-4f17-bae1-9d96f9c54f8d";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_tdl__slice23_2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__tdl__slice23_2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__tdl__slice23_2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_2__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__tdl__slice23_2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__tdl__slice23_2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice2 Xe Core0 Thread Dispatcher",
                .symbol_name = "PSThread20ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice2 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_2__ps_thread20_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_2_PSThread20ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice2 Xe Core1 Thread Dispatcher",
                .symbol_name = "PSThread21ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice2 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_2__ps_thread21_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_2_PSThread21ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice2 Xe Core2 Thread Dispatcher",
                .symbol_name = "PSThread22ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice2 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_2__ps_thread22_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_2_PSThread22ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice2 Xe Core3 Thread Dispatcher",
                .symbol_name = "PSThread23ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice2 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_2__ps_thread23_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_2_PSThread23ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice3 Xe Core0 Thread Dispatcher",
                .symbol_name = "PSThread30ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice3 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_2__ps_thread30_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_2_PSThread30ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice3 Xe Core1 Thread Dispatcher",
                .symbol_name = "PSThread31ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice3 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_2__ps_thread31_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_2_PSThread31ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice3 Xe Core2 Thread Dispatcher",
                .symbol_name = "PSThread32ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice3 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_2__ps_thread32_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_2_PSThread32ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice3 Xe Core3 Thread Dispatcher",
                .symbol_name = "PSThread33ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice3 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_2__ps_thread33_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_2_PSThread33ReadyForDispatch_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt3_tdl__slice23_3_ThreadHeader20Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_3_ThreadHeader20ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_3_ThreadHeader20ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_3_ThreadHeader20ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_3_ThreadHeader20ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_3_ThreadHeader21Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_3_ThreadHeader21ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_3_ThreadHeader21ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_3_ThreadHeader21ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_3_ThreadHeader21ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_3_ThreadHeader22Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_3_ThreadHeader22ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_3_ThreadHeader22ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_3_ThreadHeader22ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_3_ThreadHeader22ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_3_ThreadHeader23Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_tdl__slice23_3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL_Slice23_3";
    metric_set->symbol_name = "TDL_Slice23_3";
    metric_set->hw_config_guid = "34804b9e-0d2b-4e97-ba78-5c2069bc9df9";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_tdl__slice23_3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__tdl__slice23_3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__tdl__slice23_3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_3__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__tdl__slice23_3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__tdl__slice23_3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher",
                .symbol_name = "ThreadHeader20Ready",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_3__thread_header20_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_3_ThreadHeader20Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader20ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_3__thread_header20_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_3_ThreadHeader20ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader20ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_3__thread_header20_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_3_ThreadHeader20ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader20ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_3__thread_header20_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_3_ThreadHeader20ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader20ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_3__thread_header20_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_3_ThreadHeader20ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher",
                .symbol_name = "ThreadHeader21Ready",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_3__thread_header21_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_3_ThreadHeader21Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader21ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_3__thread_header21_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_3_ThreadHeader21ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader21ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_3__thread_header21_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_3_ThreadHeader21ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader21ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_3__thread_header21_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_3_ThreadHeader21ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader21ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_3__thread_header21_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_3_ThreadHeader21ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher",
                .symbol_name = "ThreadHeader22Ready",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_3__thread_header22_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_3_ThreadHeader22Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader22ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_3__thread_header22_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_3_ThreadHeader22ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader22ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_3__thread_header22_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_3_ThreadHeader22ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader22ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_3__thread_header22_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_3_ThreadHeader22ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader22ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_3__thread_header22_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_3_ThreadHeader22ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher",
                .symbol_name = "ThreadHeader23Ready",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_3__thread_header23_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_3_ThreadHeader23Ready_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt3_tdl__slice23_4_ThreadHeader30Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_4_ThreadHeader30ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_4_ThreadHeader30ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_4_ThreadHeader30ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_4_ThreadHeader30ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_4_ThreadHeader31Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_4_ThreadHeader31ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_4_ThreadHeader31ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_4_ThreadHeader31ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_4_ThreadHeader31ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_4_ThreadHeader32Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_4_ThreadHeader32ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_4_ThreadHeader32ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_4_ThreadHeader32ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_4_ThreadHeader32ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice23_4_ThreadHeader33Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_tdl__slice23_4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL_Slice23_4";
    metric_set->symbol_name = "TDL_Slice23_4";
    metric_set->hw_config_guid = "97ca0de0-9d3b-4bdd-94f7-662113dfc905";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_tdl__slice23_4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__tdl__slice23_4__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__tdl__slice23_4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_4__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__tdl__slice23_4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__tdl__slice23_4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher",
                .symbol_name = "ThreadHeader30Ready",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_4__thread_header30_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_4_ThreadHeader30Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader30ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_4__thread_header30_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_4_ThreadHeader30ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader30ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_4__thread_header30_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_4_ThreadHeader30ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader30ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_4__thread_header30_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_4_ThreadHeader30ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader30ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_4__thread_header30_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_4_ThreadHeader30ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher",
                .symbol_name = "ThreadHeader31Ready",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_4__thread_header31_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_4_ThreadHeader31Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader31ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_4__thread_header31_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_4_ThreadHeader31ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader31ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_4__thread_header31_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_4_ThreadHeader31ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader31ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_4__thread_header31_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_4_ThreadHeader31ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader31ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_4__thread_header31_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_4_ThreadHeader31ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher",
                .symbol_name = "ThreadHeader32Ready",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_4__thread_header32_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_4_ThreadHeader32Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader32ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_4__thread_header32_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_4_ThreadHeader32ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader32ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_4__thread_header32_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_4_ThreadHeader32ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader32ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_4__thread_header32_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_4_ThreadHeader32ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader32ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_4__thread_header32_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_4_ThreadHeader32ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher",
                .symbol_name = "ThreadHeader33Ready",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice23_4__thread_header33_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice23_4_ThreadHeader33Ready_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt3_tdl__slice45_1_NonPSThread40ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_1_NonPSThread41ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_1_NonPSThread42ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_1_NonPSThread43ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_1_NonPSThread50ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_1_NonPSThread51ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_1_NonPSThread52ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_1_NonPSThread53ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_1_ThreadHeader43ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_1_ThreadHeader43ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_1_ThreadHeader43ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_1_ThreadHeader43ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_1_ThreadHeader53ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_1_ThreadHeader53ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_1_ThreadHeader53ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_1_ThreadHeader53ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_tdl__slice45_1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL_Slice45_1";
    metric_set->symbol_name = "TDL_Slice45_1";
    metric_set->hw_config_guid = "f4ba49b6-37a1-4848-88d6-3c63cb8e1c12";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_tdl__slice45_1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__tdl__slice45_1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__tdl__slice45_1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_1__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__tdl__slice45_1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__tdl__slice45_1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice4 Xe Core0 Thread Dispatcher",
                .symbol_name = "NonPSThread40ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice4 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_1__non_ps_thread40_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_1_NonPSThread40ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice4 Xe Core1 Thread Dispatcher",
                .symbol_name = "NonPSThread41ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice4 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_1__non_ps_thread41_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_1_NonPSThread41ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice4 Xe Core2 Thread Dispatcher",
                .symbol_name = "NonPSThread42ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice4 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_1__non_ps_thread42_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_1_NonPSThread42ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice4 Xe Core3 Thread Dispatcher",
                .symbol_name = "NonPSThread43ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice4 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_1__non_ps_thread43_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_1_NonPSThread43ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice5 Xe Core0 Thread Dispatcher",
                .symbol_name = "NonPSThread50ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice5 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_1__non_ps_thread50_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_1_NonPSThread50ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice5 Xe Core1 Thread Dispatcher",
                .symbol_name = "NonPSThread51ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice5 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_1__non_ps_thread51_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_1_NonPSThread51ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice5 Xe Core2 Thread Dispatcher",
                .symbol_name = "NonPSThread52ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice5 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_1__non_ps_thread52_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_1_NonPSThread52ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice5 Xe Core3 Thread Dispatcher",
                .symbol_name = "NonPSThread53ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice5 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_1__non_ps_thread53_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_1_NonPSThread53ReadyForDispatch_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core3 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader43ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core3 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_1__thread_header43_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_1_ThreadHeader43ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core3 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader43ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core3 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_1__thread_header43_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_1_ThreadHeader43ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core3 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader43ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core3 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_1__thread_header43_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_1_ThreadHeader43ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core3 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader43ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core3 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_1__thread_header43_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_1_ThreadHeader43ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core3 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader53ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core3 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_1__thread_header53_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_1_ThreadHeader53ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core3 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader53ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core3 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_1__thread_header53_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_1_ThreadHeader53ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core3 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader53ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core3 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_1__thread_header53_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_1_ThreadHeader53ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core3 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader53ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core3 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_1__thread_header53_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_1_ThreadHeader53ReadyPort3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt3_tdl__slice45_2_PSThread40ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_2_PSThread41ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_2_PSThread42ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_2_PSThread43ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_2_PSThread50ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_2_PSThread51ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_2_PSThread52ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_2_PSThread53ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_tdl__slice45_2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL_Slice45_2";
    metric_set->symbol_name = "TDL_Slice45_2";
    metric_set->hw_config_guid = "a6969313-fe82-4f0b-9499-b90c98e9ede7";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_tdl__slice45_2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__tdl__slice45_2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__tdl__slice45_2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_2__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__tdl__slice45_2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__tdl__slice45_2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice4 Xe Core0 Thread Dispatcher",
                .symbol_name = "PSThread40ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice4 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_2__ps_thread40_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_2_PSThread40ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice4 Xe Core1 Thread Dispatcher",
                .symbol_name = "PSThread41ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice4 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_2__ps_thread41_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_2_PSThread41ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice4 Xe Core2 Thread Dispatcher",
                .symbol_name = "PSThread42ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice4 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_2__ps_thread42_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_2_PSThread42ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice4 Xe Core3 Thread Dispatcher",
                .symbol_name = "PSThread43ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice4 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_2__ps_thread43_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_2_PSThread43ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice5 Xe Core0 Thread Dispatcher",
                .symbol_name = "PSThread50ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice5 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_2__ps_thread50_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_2_PSThread50ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice5 Xe Core1 Thread Dispatcher",
                .symbol_name = "PSThread51ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice5 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_2__ps_thread51_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_2_PSThread51ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice5 Xe Core2 Thread Dispatcher",
                .symbol_name = "PSThread52ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice5 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_2__ps_thread52_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_2_PSThread52ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice5 Xe Core3 Thread Dispatcher",
                .symbol_name = "PSThread53ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice5 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_2__ps_thread53_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_2_PSThread53ReadyForDispatch_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt3_tdl__slice45_3_ThreadHeader40Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_3_ThreadHeader40ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_3_ThreadHeader40ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_3_ThreadHeader40ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_3_ThreadHeader40ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_3_ThreadHeader41Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_3_ThreadHeader41ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_3_ThreadHeader41ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_3_ThreadHeader41ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_3_ThreadHeader41ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_3_ThreadHeader42Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_3_ThreadHeader42ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_3_ThreadHeader42ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_3_ThreadHeader42ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_3_ThreadHeader42ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_3_ThreadHeader43Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_tdl__slice45_3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL_Slice45_3";
    metric_set->symbol_name = "TDL_Slice45_3";
    metric_set->hw_config_guid = "8dd20826-657e-43b7-9bba-a48ef4db2d14";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_tdl__slice45_3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__tdl__slice45_3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__tdl__slice45_3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_3__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__tdl__slice45_3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__tdl__slice45_3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core0 Thread Dispatcher",
                .symbol_name = "ThreadHeader40Ready",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_3__thread_header40_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_3_ThreadHeader40Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core0 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader40ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core0 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_3__thread_header40_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_3_ThreadHeader40ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core0 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader40ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core0 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_3__thread_header40_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_3_ThreadHeader40ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core0 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader40ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core0 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_3__thread_header40_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_3_ThreadHeader40ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core0 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader40ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core0 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_3__thread_header40_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_3_ThreadHeader40ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core1 Thread Dispatcher",
                .symbol_name = "ThreadHeader41Ready",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_3__thread_header41_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_3_ThreadHeader41Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core1 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader41ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core1 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_3__thread_header41_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_3_ThreadHeader41ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core1 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader41ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core1 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_3__thread_header41_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_3_ThreadHeader41ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core1 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader41ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core1 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_3__thread_header41_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_3_ThreadHeader41ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core1 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader41ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core1 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_3__thread_header41_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_3_ThreadHeader41ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core2 Thread Dispatcher",
                .symbol_name = "ThreadHeader42Ready",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_3__thread_header42_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_3_ThreadHeader42Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core2 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader42ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core2 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_3__thread_header42_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_3_ThreadHeader42ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core2 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader42ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core2 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_3__thread_header42_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_3_ThreadHeader42ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core2 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader42ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core2 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_3__thread_header42_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_3_ThreadHeader42ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core2 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader42ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core2 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_3__thread_header42_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_3_ThreadHeader42ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice4 Xe Core3 Thread Dispatcher",
                .symbol_name = "ThreadHeader43Ready",
                .desc = "The percentage of time in which thread header is ready on slice4 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_3__thread_header43_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_3_ThreadHeader43Ready_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt3_tdl__slice45_4_ThreadHeader50Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_4_ThreadHeader50ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_4_ThreadHeader50ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_4_ThreadHeader50ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_4_ThreadHeader50ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_4_ThreadHeader51Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_4_ThreadHeader51ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_4_ThreadHeader51ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_4_ThreadHeader51ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_4_ThreadHeader51ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_4_ThreadHeader52Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_4_ThreadHeader52ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_4_ThreadHeader52ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_4_ThreadHeader52ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_4_ThreadHeader52ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice45_4_ThreadHeader53Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_tdl__slice45_4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL_Slice45_4";
    metric_set->symbol_name = "TDL_Slice45_4";
    metric_set->hw_config_guid = "e479a02f-fc83-438f-818d-3e11e769fbae";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_tdl__slice45_4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__tdl__slice45_4__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__tdl__slice45_4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_4__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__tdl__slice45_4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__tdl__slice45_4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core0 Thread Dispatcher",
                .symbol_name = "ThreadHeader50Ready",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_4__thread_header50_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_4_ThreadHeader50Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core0 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader50ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core0 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_4__thread_header50_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_4_ThreadHeader50ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core0 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader50ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core0 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_4__thread_header50_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_4_ThreadHeader50ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core0 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader50ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core0 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_4__thread_header50_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_4_ThreadHeader50ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core0 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader50ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core0 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_4__thread_header50_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_4_ThreadHeader50ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core1 Thread Dispatcher",
                .symbol_name = "ThreadHeader51Ready",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_4__thread_header51_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_4_ThreadHeader51Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core1 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader51ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core1 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_4__thread_header51_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_4_ThreadHeader51ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core1 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader51ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core1 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_4__thread_header51_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_4_ThreadHeader51ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core1 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader51ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core1 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_4__thread_header51_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_4_ThreadHeader51ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core1 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader51ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core1 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_4__thread_header51_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_4_ThreadHeader51ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core2 Thread Dispatcher",
                .symbol_name = "ThreadHeader52Ready",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_4__thread_header52_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_4_ThreadHeader52Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core2 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader52ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core2 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_4__thread_header52_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_4_ThreadHeader52ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core2 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader52ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core2 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_4__thread_header52_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_4_ThreadHeader52ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core2 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader52ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core2 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_4__thread_header52_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_4_ThreadHeader52ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core2 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader52ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core2 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_4__thread_header52_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_4_ThreadHeader52ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice5 Xe Core3 Thread Dispatcher",
                .symbol_name = "ThreadHeader53Ready",
                .desc = "The percentage of time in which thread header is ready on slice5 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice45_4__thread_header53_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice45_4_ThreadHeader53Ready_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt3_tdl__slice67_1_NonPSThread60ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_1_NonPSThread61ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_1_NonPSThread62ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_1_NonPSThread63ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_1_NonPSThread70ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_1_NonPSThread71ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_1_NonPSThread72ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_1_NonPSThread73ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_1_ThreadHeader63ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_1_ThreadHeader63ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_1_ThreadHeader63ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_1_ThreadHeader63ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_1_ThreadHeader73ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_1_ThreadHeader73ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_1_ThreadHeader73ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_1_ThreadHeader73ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_tdl__slice67_1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL_Slice67_1";
    metric_set->symbol_name = "TDL_Slice67_1";
    metric_set->hw_config_guid = "deb1e6dd-bddd-42a4-87f5-c4bd8438a884";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_tdl__slice67_1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__tdl__slice67_1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__tdl__slice67_1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_1__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__tdl__slice67_1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__tdl__slice67_1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice6 Xe Core0 Thread Dispatcher",
                .symbol_name = "NonPSThread60ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice6 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_1__non_ps_thread60_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_1_NonPSThread60ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice6 Xe Core1 Thread Dispatcher",
                .symbol_name = "NonPSThread61ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice6 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_1__non_ps_thread61_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_1_NonPSThread61ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice6 Xe Core2 Thread Dispatcher",
                .symbol_name = "NonPSThread62ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice6 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_1__non_ps_thread62_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_1_NonPSThread62ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice6 Xe Core3 Thread Dispatcher",
                .symbol_name = "NonPSThread63ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice6 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_1__non_ps_thread63_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_1_NonPSThread63ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice7 Xe Core0 Thread Dispatcher",
                .symbol_name = "NonPSThread70ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice7 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_1__non_ps_thread70_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_1_NonPSThread70ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice7 Xe Core1 Thread Dispatcher",
                .symbol_name = "NonPSThread71ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice7 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_1__non_ps_thread71_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_1_NonPSThread71ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice7 Xe Core2 Thread Dispatcher",
                .symbol_name = "NonPSThread72ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice7 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_1__non_ps_thread72_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_1_NonPSThread72ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice7 Xe Core3 Thread Dispatcher",
                .symbol_name = "NonPSThread73ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice7 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_1__non_ps_thread73_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_1_NonPSThread73ReadyForDispatch_availability,
            },

            {
                .name = "Thread Header Ready on Slice6 Xe Core3 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader63ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice6 Xe core3 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_1__thread_header63_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_1_ThreadHeader63ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice6 Xe Core3 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader63ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice6 Xe core3 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_1__thread_header63_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_1_ThreadHeader63ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice6 Xe Core3 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader63ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice6 Xe core3 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_1__thread_header63_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_1_ThreadHeader63ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice6 Xe Core3 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader63ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice6 Xe core3 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_1__thread_header63_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_1_ThreadHeader63ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice7 Xe Core3 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader73ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice7 Xe core3 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_1__thread_header73_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_1_ThreadHeader73ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice7 Xe Core3 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader73ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice7 Xe core3 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_1__thread_header73_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_1_ThreadHeader73ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice7 Xe Core3 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader73ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice7 Xe core3 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_1__thread_header73_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_1_ThreadHeader73ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice7 Xe Core3 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader73ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice7 Xe core3 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_1__thread_header73_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_1_ThreadHeader73ReadyPort3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt3_tdl__slice67_2_PSThread60ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_2_PSThread61ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_2_PSThread62ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_2_PSThread63ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_2_PSThread70ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_2_PSThread71ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_2_PSThread72ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_2_PSThread73ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_tdl__slice67_2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL_Slice67_2";
    metric_set->symbol_name = "TDL_Slice67_2";
    metric_set->hw_config_guid = "0a6abc27-343e-4118-b17e-5c5121611b08";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_tdl__slice67_2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__tdl__slice67_2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__tdl__slice67_2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_2__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__tdl__slice67_2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__tdl__slice67_2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice6 Xe Core0 Thread Dispatcher",
                .symbol_name = "PSThread60ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice6 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_2__ps_thread60_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_2_PSThread60ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice6 Xe Core1 Thread Dispatcher",
                .symbol_name = "PSThread61ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice6 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_2__ps_thread61_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_2_PSThread61ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice6 Xe Core2 Thread Dispatcher",
                .symbol_name = "PSThread62ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice6 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_2__ps_thread62_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_2_PSThread62ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice6 Xe Core3 Thread Dispatcher",
                .symbol_name = "PSThread63ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice6 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_2__ps_thread63_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_2_PSThread63ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice7 Xe Core0 Thread Dispatcher",
                .symbol_name = "PSThread70ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice7 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_2__ps_thread70_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_2_PSThread70ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice7 Xe Core1 Thread Dispatcher",
                .symbol_name = "PSThread71ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice7 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_2__ps_thread71_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_2_PSThread71ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice7 Xe Core2 Thread Dispatcher",
                .symbol_name = "PSThread72ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice7 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_2__ps_thread72_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_2_PSThread72ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice7 Xe Core3 Thread Dispatcher",
                .symbol_name = "PSThread73ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice7 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_2__ps_thread73_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_2_PSThread73ReadyForDispatch_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt3_tdl__slice67_3_ThreadHeader60Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_3_ThreadHeader60ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_3_ThreadHeader60ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_3_ThreadHeader60ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_3_ThreadHeader60ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_3_ThreadHeader61Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_3_ThreadHeader61ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_3_ThreadHeader61ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_3_ThreadHeader61ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_3_ThreadHeader61ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_3_ThreadHeader62Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_3_ThreadHeader62ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_3_ThreadHeader62ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_3_ThreadHeader62ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_3_ThreadHeader62ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_3_ThreadHeader63Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_tdl__slice67_3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL_Slice67_3";
    metric_set->symbol_name = "TDL_Slice67_3";
    metric_set->hw_config_guid = "67abb260-55fb-4c66-8469-db2f8700884a";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_tdl__slice67_3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__tdl__slice67_3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__tdl__slice67_3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_3__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__tdl__slice67_3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__tdl__slice67_3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Thread Header Ready on Slice6 Xe Core0 Thread Dispatcher",
                .symbol_name = "ThreadHeader60Ready",
                .desc = "The percentage of time in which thread header is ready on slice6 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_3__thread_header60_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_3_ThreadHeader60Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice6 Xe Core0 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader60ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice6 Xe core0 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_3__thread_header60_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_3_ThreadHeader60ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice6 Xe Core0 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader60ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice6 Xe core0 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_3__thread_header60_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_3_ThreadHeader60ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice6 Xe Core0 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader60ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice6 Xe core0 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_3__thread_header60_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_3_ThreadHeader60ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice6 Xe Core0 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader60ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice6 Xe core0 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_3__thread_header60_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_3_ThreadHeader60ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice6 Xe Core1 Thread Dispatcher",
                .symbol_name = "ThreadHeader61Ready",
                .desc = "The percentage of time in which thread header is ready on slice6 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_3__thread_header61_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_3_ThreadHeader61Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice6 Xe Core1 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader61ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice6 Xe core1 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_3__thread_header61_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_3_ThreadHeader61ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice6 Xe Core1 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader61ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice6 Xe core1 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_3__thread_header61_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_3_ThreadHeader61ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice6 Xe Core1 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader61ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice6 Xe core1 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_3__thread_header61_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_3_ThreadHeader61ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice6 Xe Core1 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader61ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice6 Xe core1 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_3__thread_header61_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_3_ThreadHeader61ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice6 Xe Core2 Thread Dispatcher",
                .symbol_name = "ThreadHeader62Ready",
                .desc = "The percentage of time in which thread header is ready on slice6 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_3__thread_header62_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_3_ThreadHeader62Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice6 Xe Core2 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader62ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice6 Xe core2 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_3__thread_header62_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_3_ThreadHeader62ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice6 Xe Core2 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader62ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice6 Xe core2 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_3__thread_header62_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_3_ThreadHeader62ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice6 Xe Core2 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader62ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice6 Xe core2 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_3__thread_header62_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_3_ThreadHeader62ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice6 Xe Core2 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader62ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice6 Xe core2 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_3__thread_header62_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_3_ThreadHeader62ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice6 Xe Core3 Thread Dispatcher",
                .symbol_name = "ThreadHeader63Ready",
                .desc = "The percentage of time in which thread header is ready on slice6 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_3__thread_header63_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_3_ThreadHeader63Ready_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt3_tdl__slice67_4_ThreadHeader70Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_4_ThreadHeader70ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_4_ThreadHeader70ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_4_ThreadHeader70ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_4_ThreadHeader70ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_4_ThreadHeader71Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_4_ThreadHeader71ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_4_ThreadHeader71ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_4_ThreadHeader71ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_4_ThreadHeader71ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_4_ThreadHeader72Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_4_ThreadHeader72ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_4_ThreadHeader72ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_4_ThreadHeader72ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_4_ThreadHeader72ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_tdl__slice67_4_ThreadHeader73Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_tdl__slice67_4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL_Slice67_4";
    metric_set->symbol_name = "TDL_Slice67_4";
    metric_set->hw_config_guid = "7c064e0d-b3ee-4159-9361-8d1da3158d39";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_tdl__slice67_4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__tdl__slice67_4__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__tdl__slice67_4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_4__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__tdl__slice67_4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__tdl__slice67_4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Thread Header Ready on Slice7 Xe Core0 Thread Dispatcher",
                .symbol_name = "ThreadHeader70Ready",
                .desc = "The percentage of time in which thread header is ready on slice7 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_4__thread_header70_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_4_ThreadHeader70Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice7 Xe Core0 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader70ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice7 Xe core0 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_4__thread_header70_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_4_ThreadHeader70ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice7 Xe Core0 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader70ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice7 Xe core0 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_4__thread_header70_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_4_ThreadHeader70ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice7 Xe Core0 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader70ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice7 Xe core0 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_4__thread_header70_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_4_ThreadHeader70ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice7 Xe Core0 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader70ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice7 Xe core0 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_4__thread_header70_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_4_ThreadHeader70ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice7 Xe Core1 Thread Dispatcher",
                .symbol_name = "ThreadHeader71Ready",
                .desc = "The percentage of time in which thread header is ready on slice7 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_4__thread_header71_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_4_ThreadHeader71Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice7 Xe Core1 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader71ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice7 Xe core1 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_4__thread_header71_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_4_ThreadHeader71ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice7 Xe Core1 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader71ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice7 Xe core1 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_4__thread_header71_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_4_ThreadHeader71ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice7 Xe Core1 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader71ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice7 Xe core1 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_4__thread_header71_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_4_ThreadHeader71ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice7 Xe Core1 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader71ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice7 Xe core1 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_4__thread_header71_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_4_ThreadHeader71ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice7 Xe Core2 Thread Dispatcher",
                .symbol_name = "ThreadHeader72Ready",
                .desc = "The percentage of time in which thread header is ready on slice7 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_4__thread_header72_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_4_ThreadHeader72Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice7 Xe Core2 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader72ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice7 Xe core2 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_4__thread_header72_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_4_ThreadHeader72ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice7 Xe Core2 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader72ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice7 Xe core2 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_4__thread_header72_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_4_ThreadHeader72ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice7 Xe Core2 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader72ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice7 Xe core2 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_4__thread_header72_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_4_ThreadHeader72ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice7 Xe Core2 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader72ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice7 Xe core2 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_4__thread_header72_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_4_ThreadHeader72ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice7 Xe Core3 Thread Dispatcher",
                .symbol_name = "ThreadHeader73Ready",
                .desc = "The percentage of time in which thread header is ready on slice7 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__tdl__slice67_4__thread_header73_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_tdl__slice67_4_ThreadHeader73Ready_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}


static void
acmgt3_add_compute_overview_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ComputeOverview";
    metric_set->symbol_name = "ComputeOverview";
    metric_set->hw_config_guid = "5ae9db29-303b-4e74-8dc8-b9f2eb31aaa1";
    metric_set->counters = calloc(26, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_compute_overview_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__compute_overview__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__compute_overview__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY BYTE READ",
                .symbol_name = "GPU_MEMORY_BYTE_READ",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__compute_overview__gpu_memory_byte_read__read,
                .max_uint64 = acmgt3__compute_overview__gpu_memory_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__compute_overview__gpu_memory_byte_write__read,
                .max_uint64 = acmgt3__compute_overview__gpu_memory_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__compute_overview__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__compute_overview__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BYTE READ",
                .symbol_name = "L3_BYTE_READ",
                .desc = "Number of bytes read from L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__compute_overview__l3_byte_read__read,
                .max_uint64 = acmgt3__compute_overview__l3_byte_read__max,
                .group = "L3Cache",
            },

            {
                .name = "L3 BYTE WRITE",
                .symbol_name = "L3_BYTE_WRITE",
                .desc = "Number of bytes written to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__compute_overview__l3_byte_write__read,
                .max_uint64 = acmgt3__compute_overview__l3_byte_write__max,
                .group = "L3Cache",
            },

            {
                .name = "XVE ACTIVE",
                .symbol_name = "XVE_ACTIVE",
                .desc = "Percentage of time in which at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__compute_overview__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE ATOMIC ACCESS COUNT",
                .symbol_name = "XVE_ATOMIC_ACCESS_COUNT",
                .desc = "Number of shader atomic memory accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt3__compute_overview__xve_atomic_access_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "XVE BARRIER MESSAGE COUNT",
                .symbol_name = "XVE_BARRIER_MESSAGE_COUNT",
                .desc = "Number of shader barrier messages",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt3__compute_overview__xve_barrier_message_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "XVE BUSY",
                .symbol_name = "XVE_BUSY",
                .desc = "Any XVE thread loaded.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__compute_overview__xve_busy__read,
                .max_uint64 = acmgt3__compute_overview__xve_busy__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE COMPUTE THREAD COUNT",
                .symbol_name = "XVE_COMPUTE_THREAD_COUNT",
                .desc = "Number of compute shader hardware threads dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__compute_overview__xve_compute_thread_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ALL",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ALL",
                .desc = "Number of execution slots taken by instructions executed on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__compute_overview__xve_inst_executed_alu0_all__read,
                .max_uint64 = acmgt3__compute_overview__xve_inst_executed_alu0_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__compute_overview__xve_inst_executed_alu0_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ALL",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ALL",
                .desc = "Number of execution slots taken by instructions executed on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__compute_overview__xve_inst_executed_alu1_all__read,
                .max_uint64 = acmgt3__compute_overview__xve_inst_executed_alu1_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__compute_overview__xve_inst_executed_alu1_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED CONTROL ALL",
                .symbol_name = "XVE_INST_EXECUTED_CONTROL_ALL",
                .desc = "Number of instructions executed on Jump Pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__compute_overview__xve_inst_executed_control_all__read,
                .max_uint64 = acmgt3__compute_overview__xve_inst_executed_control_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED CONTROL ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_CONTROL_ALL_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed on Jump Pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__compute_overview__xve_inst_executed_control_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND ALL",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ALL",
                .desc = "Number of instructions executed on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__compute_overview__xve_inst_executed_send_all__read,
                .max_uint64 = acmgt3__compute_overview__xve_inst_executed_send_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ALL_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__compute_overview__xve_inst_executed_send_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX ALL",
                .symbol_name = "XVE_INST_EXECUTED_XMX_ALL",
                .desc = "Number of execution slots taken by instructions executed in XMX pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__compute_overview__xve_inst_executed_xmx_all__read,
                .max_uint64 = acmgt3__compute_overview__xve_inst_executed_xmx_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_XMX_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed in XMX pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__compute_overview__xve_inst_executed_xmx_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE PIPE ALU0 AND ALU1 ACTIVE",
                .symbol_name = "XVE_PIPE_ALU0_AND_ALU1_ACTIVE",
                .desc = "Percentage of time in which ALU0 and ALU1 pipes are both actively executing a Gen ISA instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__compute_overview__xve_pipe_alu0_and_alu1_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE PIPE ALU0 AND XMX ACTIVE",
                .symbol_name = "XVE_PIPE_ALU0_AND_XMX_ACTIVE",
                .desc = "Percentage of time in which ALU0 and XMX pipes are both actively executing a Gen ISA instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__compute_overview__xve_pipe_alu0_and_xmx_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__compute_overview__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE THREADS OCCUPANCY ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_ALL",
                .desc = "Percentage of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__compute_overview__xve_threads_occupancy_all__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 26);
}


static void
acmgt3_add_l1_profile_reads__xe_core0_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1ProfileReads";
    metric_set->symbol_name = "L1ProfileReads_XeCore0";
    metric_set->hw_config_guid = "16047ddf-5ee1-4948-81dc-edbe26576ac1";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_l1_profile_reads__xe_core0_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__l1_profile_reads__xe_core0__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__l1_profile_reads__xe_core0__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY BYTE READ",
                .symbol_name = "GPU_MEMORY_BYTE_READ",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__l1_profile_reads__xe_core0__gpu_memory_byte_read__read,
                .max_uint64 = acmgt3__l1_profile_reads__xe_core0__gpu_memory_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__l1_profile_reads__xe_core0__gpu_memory_byte_write__read,
                .max_uint64 = acmgt3__l1_profile_reads__xe_core0__gpu_memory_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__l1_profile_reads__xe_core0__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__l1_profile_reads__xe_core0__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__l1_profile_reads__xe_core0__load_store_cache_byte_read__read,
                .max_uint64 = acmgt3__l1_profile_reads__xe_core0__load_store_cache_byte_read__max,
                .group = "L1Cache",
            },

            {
                .name = "SLM BYTE READ",
                .symbol_name = "SLM_BYTE_READ",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__l1_profile_reads__xe_core0__slm_byte_read__read,
                .max_uint64 = acmgt3__l1_profile_reads__xe_core0__slm_byte_read__max,
                .group = "L1Cache",
            },

            {
                .name = "XVE ACTIVE",
                .symbol_name = "XVE_ACTIVE",
                .desc = "Percentage of time in which at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l1_profile_reads__xe_core0__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE BUSY",
                .symbol_name = "XVE_BUSY",
                .desc = "Any XVE thread loaded.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__l1_profile_reads__xe_core0__xve_busy__read,
                .max_uint64 = acmgt3__l1_profile_reads__xe_core0__xve_busy__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l1_profile_reads__xe_core0__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE THREADS OCCUPANCY ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_ALL",
                .desc = "Percentage of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l1_profile_reads__xe_core0__xve_threads_occupancy_all__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}


static void
acmgt3_add_l1_profile_reads__xe_core3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1ProfileReads";
    metric_set->symbol_name = "L1ProfileReads_XeCore3";
    metric_set->hw_config_guid = "224881aa-faa7-4d2d-8161-50dbb10026e8";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_l1_profile_reads__xe_core3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__l1_profile_reads__xe_core3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__l1_profile_reads__xe_core3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY BYTE READ",
                .symbol_name = "GPU_MEMORY_BYTE_READ",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__l1_profile_reads__xe_core3__gpu_memory_byte_read__read,
                .max_uint64 = acmgt3__l1_profile_reads__xe_core3__gpu_memory_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__l1_profile_reads__xe_core3__gpu_memory_byte_write__read,
                .max_uint64 = acmgt3__l1_profile_reads__xe_core3__gpu_memory_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__l1_profile_reads__xe_core3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__l1_profile_reads__xe_core3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__l1_profile_reads__xe_core3__load_store_cache_byte_read__read,
                .max_uint64 = acmgt3__l1_profile_reads__xe_core3__load_store_cache_byte_read__max,
                .group = "L1Cache",
            },

            {
                .name = "SLM BYTE READ",
                .symbol_name = "SLM_BYTE_READ",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__l1_profile_reads__xe_core3__slm_byte_read__read,
                .max_uint64 = acmgt3__l1_profile_reads__xe_core3__slm_byte_read__max,
                .group = "L1Cache",
            },

            {
                .name = "XVE ACTIVE",
                .symbol_name = "XVE_ACTIVE",
                .desc = "Percentage of time in which at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l1_profile_reads__xe_core3__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE BUSY",
                .symbol_name = "XVE_BUSY",
                .desc = "Any XVE thread loaded.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__l1_profile_reads__xe_core3__xve_busy__read,
                .max_uint64 = acmgt3__l1_profile_reads__xe_core3__xve_busy__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l1_profile_reads__xe_core3__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE THREADS OCCUPANCY ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_ALL",
                .desc = "Percentage of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l1_profile_reads__xe_core3__xve_threads_occupancy_all__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}


static void
acmgt3_add_l1_profile_slm_bank_conflicts__xe_core0_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1ProfileSlmBankConflicts";
    metric_set->symbol_name = "L1ProfileSlmBankConflicts_XeCore0";
    metric_set->hw_config_guid = "dc5ee653-2006-48de-8be2-e8b760a4369c";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_l1_profile_slm_bank_conflicts__xe_core0_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__l1_profile_slm_bank_conflicts__xe_core0__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__l1_profile_slm_bank_conflicts__xe_core0__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY BYTE READ",
                .symbol_name = "GPU_MEMORY_BYTE_READ",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__l1_profile_slm_bank_conflicts__xe_core0__gpu_memory_byte_read__read,
                .max_uint64 = acmgt3__l1_profile_slm_bank_conflicts__xe_core0__gpu_memory_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__l1_profile_slm_bank_conflicts__xe_core0__gpu_memory_byte_write__read,
                .max_uint64 = acmgt3__l1_profile_slm_bank_conflicts__xe_core0__gpu_memory_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__l1_profile_slm_bank_conflicts__xe_core0__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__l1_profile_slm_bank_conflicts__xe_core0__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__l1_profile_slm_bank_conflicts__xe_core0__slm_bank_conflict_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
            },

            {
                .name = "XVE ACTIVE",
                .symbol_name = "XVE_ACTIVE",
                .desc = "Percentage of time in which at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l1_profile_slm_bank_conflicts__xe_core0__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE BUSY",
                .symbol_name = "XVE_BUSY",
                .desc = "Any XVE thread loaded.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__l1_profile_slm_bank_conflicts__xe_core0__xve_busy__read,
                .max_uint64 = acmgt3__l1_profile_slm_bank_conflicts__xe_core0__xve_busy__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l1_profile_slm_bank_conflicts__xe_core0__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE THREADS OCCUPANCY ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_ALL",
                .desc = "Percentage of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l1_profile_slm_bank_conflicts__xe_core0__xve_threads_occupancy_all__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}


static void
acmgt3_add_l1_profile_slm_bank_conflicts__xe_core3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1ProfileSlmBankConflicts";
    metric_set->symbol_name = "L1ProfileSlmBankConflicts_XeCore3";
    metric_set->hw_config_guid = "41302bd4-41dd-4c52-b250-569324d62f1a";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_l1_profile_slm_bank_conflicts__xe_core3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__l1_profile_slm_bank_conflicts__xe_core3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__l1_profile_slm_bank_conflicts__xe_core3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY BYTE READ",
                .symbol_name = "GPU_MEMORY_BYTE_READ",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__l1_profile_slm_bank_conflicts__xe_core3__gpu_memory_byte_read__read,
                .max_uint64 = acmgt3__l1_profile_slm_bank_conflicts__xe_core3__gpu_memory_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__l1_profile_slm_bank_conflicts__xe_core3__gpu_memory_byte_write__read,
                .max_uint64 = acmgt3__l1_profile_slm_bank_conflicts__xe_core3__gpu_memory_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__l1_profile_slm_bank_conflicts__xe_core3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__l1_profile_slm_bank_conflicts__xe_core3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__l1_profile_slm_bank_conflicts__xe_core3__slm_bank_conflict_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
            },

            {
                .name = "XVE ACTIVE",
                .symbol_name = "XVE_ACTIVE",
                .desc = "Percentage of time in which at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l1_profile_slm_bank_conflicts__xe_core3__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE BUSY",
                .symbol_name = "XVE_BUSY",
                .desc = "Any XVE thread loaded.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__l1_profile_slm_bank_conflicts__xe_core3__xve_busy__read,
                .max_uint64 = acmgt3__l1_profile_slm_bank_conflicts__xe_core3__xve_busy__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l1_profile_slm_bank_conflicts__xe_core3__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE THREADS OCCUPANCY ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_ALL",
                .desc = "Percentage of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l1_profile_slm_bank_conflicts__xe_core3__xve_threads_occupancy_all__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}


static void
acmgt3_add_l1_profile_writes__xe_core0_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1ProfileWrites";
    metric_set->symbol_name = "L1ProfileWrites_XeCore0";
    metric_set->hw_config_guid = "a0369d50-1c37-4bf4-97a9-169c92b63483";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_l1_profile_writes__xe_core0_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__l1_profile_writes__xe_core0__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__l1_profile_writes__xe_core0__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY BYTE READ",
                .symbol_name = "GPU_MEMORY_BYTE_READ",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__l1_profile_writes__xe_core0__gpu_memory_byte_read__read,
                .max_uint64 = acmgt3__l1_profile_writes__xe_core0__gpu_memory_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__l1_profile_writes__xe_core0__gpu_memory_byte_write__read,
                .max_uint64 = acmgt3__l1_profile_writes__xe_core0__gpu_memory_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__l1_profile_writes__xe_core0__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__l1_profile_writes__xe_core0__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__l1_profile_writes__xe_core0__load_store_cache_byte_write__read,
                .max_uint64 = acmgt3__l1_profile_writes__xe_core0__load_store_cache_byte_write__max,
                .group = "L1Cache",
            },

            {
                .name = "SLM BYTE WRITE",
                .symbol_name = "SLM_BYTE_WRITE",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__l1_profile_writes__xe_core0__slm_byte_write__read,
                .max_uint64 = acmgt3__l1_profile_writes__xe_core0__slm_byte_write__max,
                .group = "L1Cache",
            },

            {
                .name = "XVE ACTIVE",
                .symbol_name = "XVE_ACTIVE",
                .desc = "Percentage of time in which at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l1_profile_writes__xe_core0__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE BUSY",
                .symbol_name = "XVE_BUSY",
                .desc = "Any XVE thread loaded.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__l1_profile_writes__xe_core0__xve_busy__read,
                .max_uint64 = acmgt3__l1_profile_writes__xe_core0__xve_busy__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l1_profile_writes__xe_core0__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE THREADS OCCUPANCY ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_ALL",
                .desc = "Percentage of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l1_profile_writes__xe_core0__xve_threads_occupancy_all__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}


static void
acmgt3_add_l1_profile_writes__xe_core3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1ProfileWrites";
    metric_set->symbol_name = "L1ProfileWrites_XeCore3";
    metric_set->hw_config_guid = "ff386ef9-604c-48a5-9fc9-e2281bbd7463";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_l1_profile_writes__xe_core3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__l1_profile_writes__xe_core3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__l1_profile_writes__xe_core3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY BYTE READ",
                .symbol_name = "GPU_MEMORY_BYTE_READ",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__l1_profile_writes__xe_core3__gpu_memory_byte_read__read,
                .max_uint64 = acmgt3__l1_profile_writes__xe_core3__gpu_memory_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__l1_profile_writes__xe_core3__gpu_memory_byte_write__read,
                .max_uint64 = acmgt3__l1_profile_writes__xe_core3__gpu_memory_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__l1_profile_writes__xe_core3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__l1_profile_writes__xe_core3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__l1_profile_writes__xe_core3__load_store_cache_byte_write__read,
                .max_uint64 = acmgt3__l1_profile_writes__xe_core3__load_store_cache_byte_write__max,
                .group = "L1Cache",
            },

            {
                .name = "SLM BYTE WRITE",
                .symbol_name = "SLM_BYTE_WRITE",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__l1_profile_writes__xe_core3__slm_byte_write__read,
                .max_uint64 = acmgt3__l1_profile_writes__xe_core3__slm_byte_write__max,
                .group = "L1Cache",
            },

            {
                .name = "XVE ACTIVE",
                .symbol_name = "XVE_ACTIVE",
                .desc = "Percentage of time in which at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l1_profile_writes__xe_core3__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE BUSY",
                .symbol_name = "XVE_BUSY",
                .desc = "Any XVE thread loaded.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__l1_profile_writes__xe_core3__xve_busy__read,
                .max_uint64 = acmgt3__l1_profile_writes__xe_core3__xve_busy__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l1_profile_writes__xe_core3__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE THREADS OCCUPANCY ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_ALL",
                .desc = "Percentage of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__l1_profile_writes__xe_core3__xve_threads_occupancy_all__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}


static void
acmgt3_add_dataport_reads_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DataportReads";
    metric_set->symbol_name = "DataportReads";
    metric_set->hw_config_guid = "c027d083-6448-4ec1-9415-8a1ff807562c";
    metric_set->counters = calloc(13, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_dataport_reads_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__dataport_reads__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__dataport_reads__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ",
                .symbol_name = "DATAPORT_BYTE_READ",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__dataport_reads__dataport_byte_read__read,
                .max_uint64 = acmgt3__dataport_reads__dataport_byte_read__max,
                .group = "Dataport",
            },

            {
                .name = "GPU MEMORY BYTE READ",
                .symbol_name = "GPU_MEMORY_BYTE_READ",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__dataport_reads__gpu_memory_byte_read__read,
                .max_uint64 = acmgt3__dataport_reads__gpu_memory_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__dataport_reads__gpu_memory_byte_write__read,
                .max_uint64 = acmgt3__dataport_reads__gpu_memory_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__dataport_reads__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__dataport_reads__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HOST TO GPUMEM BYTE READ",
                .symbol_name = "HOST_TO_GPUMEM_BYTE_READ",
                .desc = "Number of bytes read by host from GPU local (HBM) memory (downstream)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__dataport_reads__host_to_gpumem_byte_read__read,
                .max_uint64 = acmgt3__dataport_reads__host_to_gpumem_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "HOST TO GPUMEM BYTE WRITE",
                .symbol_name = "HOST_TO_GPUMEM_BYTE_WRITE",
                .desc = "Number of bytes written by host to GPU local (HBM) memory (downstream)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__dataport_reads__host_to_gpumem_byte_write__read,
                .max_uint64 = acmgt3__dataport_reads__host_to_gpumem_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "XVE ACTIVE",
                .symbol_name = "XVE_ACTIVE",
                .desc = "Percentage of time in which at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__dataport_reads__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE BUSY",
                .symbol_name = "XVE_BUSY",
                .desc = "Any XVE thread loaded.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__dataport_reads__xve_busy__read,
                .max_uint64 = acmgt3__dataport_reads__xve_busy__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE COMPUTE THREAD COUNT",
                .symbol_name = "XVE_COMPUTE_THREAD_COUNT",
                .desc = "Number of compute shader hardware threads dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__dataport_reads__xve_compute_thread_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__dataport_reads__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE THREADS OCCUPANCY ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_ALL",
                .desc = "Percentage of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__dataport_reads__xve_threads_occupancy_all__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 13);
}


static void
acmgt3_add_dataport_writes_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DataportWrites";
    metric_set->symbol_name = "DataportWrites";
    metric_set->hw_config_guid = "57e2e261-2715-4b63-baec-527eba9e06cb";
    metric_set->counters = calloc(14, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_dataport_writes_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__dataport_writes__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__dataport_writes__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE WRITE",
                .symbol_name = "DATAPORT_BYTE_WRITE",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__dataport_writes__dataport_byte_write__read,
                .max_uint64 = acmgt3__dataport_writes__dataport_byte_write__max,
                .group = "Dataport",
            },

            {
                .name = "GPU MEMORY BYTE READ",
                .symbol_name = "GPU_MEMORY_BYTE_READ",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__dataport_writes__gpu_memory_byte_read__read,
                .max_uint64 = acmgt3__dataport_writes__gpu_memory_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__dataport_writes__gpu_memory_byte_write__read,
                .max_uint64 = acmgt3__dataport_writes__gpu_memory_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__dataport_writes__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__dataport_writes__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER L3 READ",
                .symbol_name = "SAMPLER_L3_READ",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__dataport_writes__sampler_l3_read__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "SYSMEM BYTE READ",
                .symbol_name = "SYSMEM_BYTE_READ",
                .desc = "Number of system memory bytes read (upstream)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__dataport_writes__sysmem_byte_read__read,
                .max_uint64 = acmgt3__dataport_writes__sysmem_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "SYSMEM BYTE WRITE",
                .symbol_name = "SYSMEM_BYTE_WRITE",
                .desc = "Number of system memory bytes written (upstream)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__dataport_writes__sysmem_byte_write__read,
                .max_uint64 = acmgt3__dataport_writes__sysmem_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "XVE ACTIVE",
                .symbol_name = "XVE_ACTIVE",
                .desc = "Percentage of time in which at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__dataport_writes__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE BUSY",
                .symbol_name = "XVE_BUSY",
                .desc = "Any XVE thread loaded.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__dataport_writes__xve_busy__read,
                .max_uint64 = acmgt3__dataport_writes__xve_busy__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE COMPUTE THREAD COUNT",
                .symbol_name = "XVE_COMPUTE_THREAD_COUNT",
                .desc = "Number of compute shader hardware threads dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt3__dataport_writes__xve_compute_thread_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__dataport_writes__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE THREADS OCCUPANCY ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_ALL",
                .desc = "Percentage of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__dataport_writes__xve_threads_occupancy_all__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 14);
}


static void
acmgt3_add_ext1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1";
    metric_set->symbol_name = "Ext1";
    metric_set->hw_config_guid = "9e92a393-69c4-46fd-b038-e6183364d8c5";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY READ",
                .symbol_name = "GPU_MEMORY_READ",
                .desc = "Number of GTI memory reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1__gpu_memory_read__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY READ SQIDI0",
                .symbol_name = "GPU_MEMORY_READ_SQIDI0",
                .desc = "Number of GTI memory reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1__gpu_memory_read_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY READ SQIDI1",
                .symbol_name = "GPU_MEMORY_READ_SQIDI1",
                .desc = "Number of GTI memory reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1__gpu_memory_read_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY READ SQIDI2",
                .symbol_name = "GPU_MEMORY_READ_SQIDI2",
                .desc = "Number of GTI memory reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1__gpu_memory_read_sqidi2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY READ SQIDI3",
                .symbol_name = "GPU_MEMORY_READ_SQIDI3",
                .desc = "Number of GTI memory reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1__gpu_memory_read_sqidi3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY READ SQIDI4",
                .symbol_name = "GPU_MEMORY_READ_SQIDI4",
                .desc = "Number of GTI memory reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1__gpu_memory_read_sqidi4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY READ SQIDI5",
                .symbol_name = "GPU_MEMORY_READ_SQIDI5",
                .desc = "Number of GTI memory reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1__gpu_memory_read_sqidi5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY READ SQIDI6",
                .symbol_name = "GPU_MEMORY_READ_SQIDI6",
                .desc = "Number of GTI memory reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1__gpu_memory_read_sqidi6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY READ SQIDI7",
                .symbol_name = "GPU_MEMORY_READ_SQIDI7",
                .desc = "Number of GTI memory reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1__gpu_memory_read_sqidi7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}


static void
acmgt3_add_ext2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext2";
    metric_set->symbol_name = "Ext2";
    metric_set->hw_config_guid = "e8621f59-b8d2-4e00-86a9-472e3848973d";
    metric_set->counters = calloc(39, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY BYTE READ",
                .symbol_name = "GPU_MEMORY_BYTE_READ",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext2__gpu_memory_byte_read__read,
                .max_uint64 = acmgt3__ext2__gpu_memory_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ BW",
                .symbol_name = "GPU_MEMORY_BYTE_READ_BW",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) read bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt3__ext2__gpu_memory_byte_read_bw__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ BW SQIDI0",
                .symbol_name = "GPU_MEMORY_BYTE_READ_BW_SQIDI0",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) read bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt3__ext2__gpu_memory_byte_read_bw_sqidi0__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ BW SQIDI1",
                .symbol_name = "GPU_MEMORY_BYTE_READ_BW_SQIDI1",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) read bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt3__ext2__gpu_memory_byte_read_bw_sqidi1__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ BW SQIDI2",
                .symbol_name = "GPU_MEMORY_BYTE_READ_BW_SQIDI2",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) read bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt3__ext2__gpu_memory_byte_read_bw_sqidi2__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ BW SQIDI3",
                .symbol_name = "GPU_MEMORY_BYTE_READ_BW_SQIDI3",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) read bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt3__ext2__gpu_memory_byte_read_bw_sqidi3__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ BW SQIDI4",
                .symbol_name = "GPU_MEMORY_BYTE_READ_BW_SQIDI4",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) read bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt3__ext2__gpu_memory_byte_read_bw_sqidi4__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ BW SQIDI5",
                .symbol_name = "GPU_MEMORY_BYTE_READ_BW_SQIDI5",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) read bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt3__ext2__gpu_memory_byte_read_bw_sqidi5__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ BW SQIDI6",
                .symbol_name = "GPU_MEMORY_BYTE_READ_BW_SQIDI6",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) read bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt3__ext2__gpu_memory_byte_read_bw_sqidi6__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ BW SQIDI7",
                .symbol_name = "GPU_MEMORY_BYTE_READ_BW_SQIDI7",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) read bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt3__ext2__gpu_memory_byte_read_bw_sqidi7__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ SQIDI0",
                .symbol_name = "GPU_MEMORY_BYTE_READ_SQIDI0",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext2__gpu_memory_byte_read_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ SQIDI1",
                .symbol_name = "GPU_MEMORY_BYTE_READ_SQIDI1",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext2__gpu_memory_byte_read_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ SQIDI2",
                .symbol_name = "GPU_MEMORY_BYTE_READ_SQIDI2",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext2__gpu_memory_byte_read_sqidi2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ SQIDI3",
                .symbol_name = "GPU_MEMORY_BYTE_READ_SQIDI3",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext2__gpu_memory_byte_read_sqidi3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ SQIDI4",
                .symbol_name = "GPU_MEMORY_BYTE_READ_SQIDI4",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext2__gpu_memory_byte_read_sqidi4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ SQIDI5",
                .symbol_name = "GPU_MEMORY_BYTE_READ_SQIDI5",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext2__gpu_memory_byte_read_sqidi5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ SQIDI6",
                .symbol_name = "GPU_MEMORY_BYTE_READ_SQIDI6",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext2__gpu_memory_byte_read_sqidi6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ SQIDI7",
                .symbol_name = "GPU_MEMORY_BYTE_READ_SQIDI7",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext2__gpu_memory_byte_read_sqidi7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext2__gpu_memory_byte_write__read,
                .max_uint64 = acmgt3__ext2__gpu_memory_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE BW",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_BW",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) write bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt3__ext2__gpu_memory_byte_write_bw__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE BW SQIDI0",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_BW_SQIDI0",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) write bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt3__ext2__gpu_memory_byte_write_bw_sqidi0__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE BW SQIDI1",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_BW_SQIDI1",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) write bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt3__ext2__gpu_memory_byte_write_bw_sqidi1__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE BW SQIDI2",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_BW_SQIDI2",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) write bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt3__ext2__gpu_memory_byte_write_bw_sqidi2__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE BW SQIDI3",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_BW_SQIDI3",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) write bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt3__ext2__gpu_memory_byte_write_bw_sqidi3__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE BW SQIDI4",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_BW_SQIDI4",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) write bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt3__ext2__gpu_memory_byte_write_bw_sqidi4__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE BW SQIDI5",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_BW_SQIDI5",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) write bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt3__ext2__gpu_memory_byte_write_bw_sqidi5__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE BW SQIDI6",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_BW_SQIDI6",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) write bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt3__ext2__gpu_memory_byte_write_bw_sqidi6__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE BW SQIDI7",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_BW_SQIDI7",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) write bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt3__ext2__gpu_memory_byte_write_bw_sqidi7__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE SQIDI0",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_SQIDI0",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext2__gpu_memory_byte_write_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE SQIDI1",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_SQIDI1",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext2__gpu_memory_byte_write_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE SQIDI2",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_SQIDI2",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext2__gpu_memory_byte_write_sqidi2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE SQIDI3",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_SQIDI3",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext2__gpu_memory_byte_write_sqidi3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE SQIDI4",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_SQIDI4",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext2__gpu_memory_byte_write_sqidi4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE SQIDI5",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_SQIDI5",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext2__gpu_memory_byte_write_sqidi5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE SQIDI6",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_SQIDI6",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext2__gpu_memory_byte_write_sqidi6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE SQIDI7",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_SQIDI7",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext2__gpu_memory_byte_write_sqidi7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 39);
}


static void
acmgt3_add_ext3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext3";
    metric_set->symbol_name = "Ext3";
    metric_set->hw_config_guid = "12eee9d0-7d4a-495c-a3b5-7d8ab1b0fe02";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION READ SQIDI0",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_READ_SQIDI0",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext3__gpu_memory_32_b_transaction_read_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION READ SQIDI1",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_READ_SQIDI1",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext3__gpu_memory_32_b_transaction_read_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION READ SQIDI2",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_READ_SQIDI2",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext3__gpu_memory_32_b_transaction_read_sqidi2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION READ SQIDI3",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_READ_SQIDI3",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext3__gpu_memory_32_b_transaction_read_sqidi3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION READ SQIDI4",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_READ_SQIDI4",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext3__gpu_memory_32_b_transaction_read_sqidi4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION READ SQIDI5",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_READ_SQIDI5",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext3__gpu_memory_32_b_transaction_read_sqidi5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION READ SQIDI6",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_READ_SQIDI6",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext3__gpu_memory_32_b_transaction_read_sqidi6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION READ SQIDI7",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_READ_SQIDI7",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext3__gpu_memory_32_b_transaction_read_sqidi7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}


static void
acmgt3_add_ext4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext4";
    metric_set->symbol_name = "Ext4";
    metric_set->hw_config_guid = "59c0b126-b2dc-4a97-818e-741e6355059c";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext4__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION READ SQIDI0",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_READ_SQIDI0",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext4__gpu_memory_64_b_transaction_read_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION READ SQIDI1",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_READ_SQIDI1",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext4__gpu_memory_64_b_transaction_read_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION READ SQIDI2",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_READ_SQIDI2",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext4__gpu_memory_64_b_transaction_read_sqidi2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION READ SQIDI3",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_READ_SQIDI3",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext4__gpu_memory_64_b_transaction_read_sqidi3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION READ SQIDI4",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_READ_SQIDI4",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext4__gpu_memory_64_b_transaction_read_sqidi4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION READ SQIDI5",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_READ_SQIDI5",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext4__gpu_memory_64_b_transaction_read_sqidi5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION READ SQIDI6",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_READ_SQIDI6",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext4__gpu_memory_64_b_transaction_read_sqidi6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION READ SQIDI7",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_READ_SQIDI7",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext4__gpu_memory_64_b_transaction_read_sqidi7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}


static void
acmgt3_add_ext5_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext5";
    metric_set->symbol_name = "Ext5";
    metric_set->hw_config_guid = "9da5cb85-6e23-4896-8d99-1b8a87dd8930";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext5_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext5__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext5__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION WRITE SQIDI0",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_WRITE_SQIDI0",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext5__gpu_memory_32_b_transaction_write_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION WRITE SQIDI1",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_WRITE_SQIDI1",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext5__gpu_memory_32_b_transaction_write_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION WRITE SQIDI2",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_WRITE_SQIDI2",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext5__gpu_memory_32_b_transaction_write_sqidi2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION WRITE SQIDI3",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_WRITE_SQIDI3",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext5__gpu_memory_32_b_transaction_write_sqidi3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION WRITE SQIDI4",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_WRITE_SQIDI4",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext5__gpu_memory_32_b_transaction_write_sqidi4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION WRITE SQIDI5",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_WRITE_SQIDI5",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext5__gpu_memory_32_b_transaction_write_sqidi5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION WRITE SQIDI6",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_WRITE_SQIDI6",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext5__gpu_memory_32_b_transaction_write_sqidi6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION WRITE SQIDI7",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_WRITE_SQIDI7",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext5__gpu_memory_32_b_transaction_write_sqidi7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION WRITE SQIDI0",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_WRITE_SQIDI0",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext5__gpu_memory_64_b_transaction_write_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION WRITE SQIDI1",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_WRITE_SQIDI1",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext5__gpu_memory_64_b_transaction_write_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION WRITE SQIDI2",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_WRITE_SQIDI2",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext5__gpu_memory_64_b_transaction_write_sqidi2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION WRITE SQIDI3",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_WRITE_SQIDI3",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext5__gpu_memory_64_b_transaction_write_sqidi3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION WRITE SQIDI4",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_WRITE_SQIDI4",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext5__gpu_memory_64_b_transaction_write_sqidi4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION WRITE SQIDI5",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_WRITE_SQIDI5",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext5__gpu_memory_64_b_transaction_write_sqidi5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION WRITE SQIDI6",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_WRITE_SQIDI6",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext5__gpu_memory_64_b_transaction_write_sqidi6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION WRITE SQIDI7",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_WRITE_SQIDI7",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext5__gpu_memory_64_b_transaction_write_sqidi7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext5__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext5__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}


static void
acmgt3_add_ext6_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext6";
    metric_set->symbol_name = "Ext6";
    metric_set->hw_config_guid = "4cd5fd6b-e82a-44fc-a068-4debac13114f";
    metric_set->counters = calloc(21, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext6_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext6__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext6__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY ACTIVE",
                .symbol_name = "GPU_MEMORY_ACTIVE",
                .desc = "Percentage of time in which device local memory (HBM, GDDR, LPDDR, etc.) is active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext6__gpu_memory_active__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY ACTIVE SQIDI0",
                .symbol_name = "GPU_MEMORY_ACTIVE_SQIDI0",
                .desc = "Percentage of time in which device local memory (HBM, GDDR, LPDDR, etc.) is active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext6__gpu_memory_active_sqidi0__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY ACTIVE SQIDI1",
                .symbol_name = "GPU_MEMORY_ACTIVE_SQIDI1",
                .desc = "Percentage of time in which device local memory (HBM, GDDR, LPDDR, etc.) is active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext6__gpu_memory_active_sqidi1__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY ACTIVE SQIDI2",
                .symbol_name = "GPU_MEMORY_ACTIVE_SQIDI2",
                .desc = "Percentage of time in which device local memory (HBM, GDDR, LPDDR, etc.) is active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext6__gpu_memory_active_sqidi2__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY ACTIVE SQIDI3",
                .symbol_name = "GPU_MEMORY_ACTIVE_SQIDI3",
                .desc = "Percentage of time in which device local memory (HBM, GDDR, LPDDR, etc.) is active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext6__gpu_memory_active_sqidi3__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY ACTIVE SQIDI4",
                .symbol_name = "GPU_MEMORY_ACTIVE_SQIDI4",
                .desc = "Percentage of time in which device local memory (HBM, GDDR, LPDDR, etc.) is active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext6__gpu_memory_active_sqidi4__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY ACTIVE SQIDI5",
                .symbol_name = "GPU_MEMORY_ACTIVE_SQIDI5",
                .desc = "Percentage of time in which device local memory (HBM, GDDR, LPDDR, etc.) is active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext6__gpu_memory_active_sqidi5__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY ACTIVE SQIDI6",
                .symbol_name = "GPU_MEMORY_ACTIVE_SQIDI6",
                .desc = "Percentage of time in which device local memory (HBM, GDDR, LPDDR, etc.) is active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext6__gpu_memory_active_sqidi6__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY ACTIVE SQIDI7",
                .symbol_name = "GPU_MEMORY_ACTIVE_SQIDI7",
                .desc = "Percentage of time in which device local memory (HBM, GDDR, LPDDR, etc.) is active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext6__gpu_memory_active_sqidi7__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY REQUEST QUEUE FULL",
                .symbol_name = "GPU_MEMORY_REQUEST_QUEUE_FULL",
                .desc = "Percentage of time in which SQ is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext6__gpu_memory_request_queue_full__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY REQUEST QUEUE FULL SQIDI0",
                .symbol_name = "GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI0",
                .desc = "Percentage of time in which SQ is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext6__gpu_memory_request_queue_full_sqidi0__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY REQUEST QUEUE FULL SQIDI1",
                .symbol_name = "GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI1",
                .desc = "Percentage of time in which SQ is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext6__gpu_memory_request_queue_full_sqidi1__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY REQUEST QUEUE FULL SQIDI2",
                .symbol_name = "GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI2",
                .desc = "Percentage of time in which SQ is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext6__gpu_memory_request_queue_full_sqidi2__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY REQUEST QUEUE FULL SQIDI3",
                .symbol_name = "GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI3",
                .desc = "Percentage of time in which SQ is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext6__gpu_memory_request_queue_full_sqidi3__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY REQUEST QUEUE FULL SQIDI4",
                .symbol_name = "GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI4",
                .desc = "Percentage of time in which SQ is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext6__gpu_memory_request_queue_full_sqidi4__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY REQUEST QUEUE FULL SQIDI5",
                .symbol_name = "GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI5",
                .desc = "Percentage of time in which SQ is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext6__gpu_memory_request_queue_full_sqidi5__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY REQUEST QUEUE FULL SQIDI6",
                .symbol_name = "GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI6",
                .desc = "Percentage of time in which SQ is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext6__gpu_memory_request_queue_full_sqidi6__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY REQUEST QUEUE FULL SQIDI7",
                .symbol_name = "GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI7",
                .desc = "Percentage of time in which SQ is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext6__gpu_memory_request_queue_full_sqidi7__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext6__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext6__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 21);
}


static void
acmgt3_add_ext7_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext7";
    metric_set->symbol_name = "Ext7";
    metric_set->hw_config_guid = "29eade65-5f7c-4b51-8006-66852e9f2181";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext7_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext7__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext7__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext7__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext7__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 HIT L3BANK0",
                .symbol_name = "L3_HIT_L3BANK0",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext7__l3_hit_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK1",
                .symbol_name = "L3_HIT_L3BANK1",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext7__l3_hit_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK10",
                .symbol_name = "L3_HIT_L3BANK10",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext7__l3_hit_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK11",
                .symbol_name = "L3_HIT_L3BANK11",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext7__l3_hit_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK12",
                .symbol_name = "L3_HIT_L3BANK12",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext7__l3_hit_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK13",
                .symbol_name = "L3_HIT_L3BANK13",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext7__l3_hit_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK14",
                .symbol_name = "L3_HIT_L3BANK14",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext7__l3_hit_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK15",
                .symbol_name = "L3_HIT_L3BANK15",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext7__l3_hit_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK2",
                .symbol_name = "L3_HIT_L3BANK2",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext7__l3_hit_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK3",
                .symbol_name = "L3_HIT_L3BANK3",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext7__l3_hit_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK4",
                .symbol_name = "L3_HIT_L3BANK4",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext7__l3_hit_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK5",
                .symbol_name = "L3_HIT_L3BANK5",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext7__l3_hit_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK6",
                .symbol_name = "L3_HIT_L3BANK6",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext7__l3_hit_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK7",
                .symbol_name = "L3_HIT_L3BANK7",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext7__l3_hit_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK8",
                .symbol_name = "L3_HIT_L3BANK8",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext7__l3_hit_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK9",
                .symbol_name = "L3_HIT_L3BANK9",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext7__l3_hit_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}


static void
acmgt3_add_ext8_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext8";
    metric_set->symbol_name = "Ext8";
    metric_set->hw_config_guid = "859c2807-55de-47e0-aa30-320c23c9373d";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext8_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext8__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext8__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext8__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext8__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 HIT L3BANK16",
                .symbol_name = "L3_HIT_L3BANK16",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext8__l3_hit_l3_bank16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK17",
                .symbol_name = "L3_HIT_L3BANK17",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext8__l3_hit_l3_bank17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK18",
                .symbol_name = "L3_HIT_L3BANK18",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext8__l3_hit_l3_bank18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK19",
                .symbol_name = "L3_HIT_L3BANK19",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext8__l3_hit_l3_bank19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK20",
                .symbol_name = "L3_HIT_L3BANK20",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext8__l3_hit_l3_bank20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK21",
                .symbol_name = "L3_HIT_L3BANK21",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext8__l3_hit_l3_bank21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK22",
                .symbol_name = "L3_HIT_L3BANK22",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext8__l3_hit_l3_bank22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK23",
                .symbol_name = "L3_HIT_L3BANK23",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext8__l3_hit_l3_bank23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK24",
                .symbol_name = "L3_HIT_L3BANK24",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext8__l3_hit_l3_bank24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK25",
                .symbol_name = "L3_HIT_L3BANK25",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext8__l3_hit_l3_bank25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK26",
                .symbol_name = "L3_HIT_L3BANK26",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext8__l3_hit_l3_bank26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK27",
                .symbol_name = "L3_HIT_L3BANK27",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext8__l3_hit_l3_bank27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK28",
                .symbol_name = "L3_HIT_L3BANK28",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext8__l3_hit_l3_bank28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK29",
                .symbol_name = "L3_HIT_L3BANK29",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext8__l3_hit_l3_bank29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK30",
                .symbol_name = "L3_HIT_L3BANK30",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext8__l3_hit_l3_bank30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK31",
                .symbol_name = "L3_HIT_L3BANK31",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext8__l3_hit_l3_bank31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext9_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext9";
    metric_set->symbol_name = "Ext9";
    metric_set->hw_config_guid = "c9c488d0-950c-4a0a-a079-b299cd33aa6b";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext9_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext9__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext9__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext9__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext9__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK0",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK0",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext9__l3_input_available_l3_bank0__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK0_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK1",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK1",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext9__l3_input_available_l3_bank1__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK1_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK10",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK10",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext9__l3_input_available_l3_bank10__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK10_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK11",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK11",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext9__l3_input_available_l3_bank11__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK11_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK12",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK12",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext9__l3_input_available_l3_bank12__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK12_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK13",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK13",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext9__l3_input_available_l3_bank13__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK13_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK14",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK14",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext9__l3_input_available_l3_bank14__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK14_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK15",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK15",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext9__l3_input_available_l3_bank15__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK15_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK2",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK2",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext9__l3_input_available_l3_bank2__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK2_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK3",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK3",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext9__l3_input_available_l3_bank3__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK3_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK4",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK4",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext9__l3_input_available_l3_bank4__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK4_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK5",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK5",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext9__l3_input_available_l3_bank5__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK5_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK6",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK6",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext9__l3_input_available_l3_bank6__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK6_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK7",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK7",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext9__l3_input_available_l3_bank7__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK7_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK8",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK8",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext9__l3_input_available_l3_bank8__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK8_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK9",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK9",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext9__l3_input_available_l3_bank9__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext9_L3_INPUT_AVAILABLE_L3BANK9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK16_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK17_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK18_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK19_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK20_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK21_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK22_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK23_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK24_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK25_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK26_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK27_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK28_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK29_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK30_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK31_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext10_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext10";
    metric_set->symbol_name = "Ext10";
    metric_set->hw_config_guid = "4599426b-4cfa-442a-8a59-9eda3dd742db";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext10_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext10__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext10__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext10__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext10__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK16",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK16",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext10__l3_input_available_l3_bank16__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK16_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK17",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK17",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext10__l3_input_available_l3_bank17__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK17_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK18",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK18",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext10__l3_input_available_l3_bank18__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK18_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK19",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK19",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext10__l3_input_available_l3_bank19__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK19_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK20",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK20",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext10__l3_input_available_l3_bank20__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK20_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK21",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK21",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext10__l3_input_available_l3_bank21__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK21_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK22",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK22",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext10__l3_input_available_l3_bank22__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK22_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK23",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK23",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext10__l3_input_available_l3_bank23__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK23_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK24",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK24",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext10__l3_input_available_l3_bank24__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK24_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK25",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK25",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext10__l3_input_available_l3_bank25__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK25_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK26",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK26",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext10__l3_input_available_l3_bank26__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK26_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK27",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK27",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext10__l3_input_available_l3_bank27__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK27_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK28",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK28",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext10__l3_input_available_l3_bank28__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK28_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK29",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK29",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext10__l3_input_available_l3_bank29__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK29_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK30",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK30",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext10__l3_input_available_l3_bank30__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK30_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK31",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK31",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext10__l3_input_available_l3_bank31__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext10_L3_INPUT_AVAILABLE_L3BANK31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext11_L3_OUTPUT_READY_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext11_L3_OUTPUT_READY_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext11_L3_OUTPUT_READY_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext11_L3_OUTPUT_READY_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext11_L3_OUTPUT_READY_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext11_L3_OUTPUT_READY_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext11_L3_OUTPUT_READY_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext11_L3_OUTPUT_READY_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext11_L3_OUTPUT_READY_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext11_L3_OUTPUT_READY_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext11_L3_OUTPUT_READY_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext11_L3_OUTPUT_READY_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext11_L3_OUTPUT_READY_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext11_L3_OUTPUT_READY_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext11_L3_OUTPUT_READY_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext11_L3_OUTPUT_READY_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext11_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext11";
    metric_set->symbol_name = "Ext11";
    metric_set->hw_config_guid = "42107330-c266-42b4-aef5-5c2ab410edc4";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext11_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext11__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext11__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext11__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext11__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 OUTPUT READY L3BANK0",
                .symbol_name = "L3_OUTPUT_READY_L3BANK0",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext11__l3_output_ready_l3_bank0__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext11_L3_OUTPUT_READY_L3BANK0_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK1",
                .symbol_name = "L3_OUTPUT_READY_L3BANK1",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext11__l3_output_ready_l3_bank1__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext11_L3_OUTPUT_READY_L3BANK1_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK10",
                .symbol_name = "L3_OUTPUT_READY_L3BANK10",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext11__l3_output_ready_l3_bank10__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext11_L3_OUTPUT_READY_L3BANK10_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK11",
                .symbol_name = "L3_OUTPUT_READY_L3BANK11",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext11__l3_output_ready_l3_bank11__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext11_L3_OUTPUT_READY_L3BANK11_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK12",
                .symbol_name = "L3_OUTPUT_READY_L3BANK12",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext11__l3_output_ready_l3_bank12__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext11_L3_OUTPUT_READY_L3BANK12_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK13",
                .symbol_name = "L3_OUTPUT_READY_L3BANK13",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext11__l3_output_ready_l3_bank13__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext11_L3_OUTPUT_READY_L3BANK13_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK14",
                .symbol_name = "L3_OUTPUT_READY_L3BANK14",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext11__l3_output_ready_l3_bank14__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext11_L3_OUTPUT_READY_L3BANK14_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK15",
                .symbol_name = "L3_OUTPUT_READY_L3BANK15",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext11__l3_output_ready_l3_bank15__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext11_L3_OUTPUT_READY_L3BANK15_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK2",
                .symbol_name = "L3_OUTPUT_READY_L3BANK2",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext11__l3_output_ready_l3_bank2__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext11_L3_OUTPUT_READY_L3BANK2_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK3",
                .symbol_name = "L3_OUTPUT_READY_L3BANK3",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext11__l3_output_ready_l3_bank3__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext11_L3_OUTPUT_READY_L3BANK3_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK4",
                .symbol_name = "L3_OUTPUT_READY_L3BANK4",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext11__l3_output_ready_l3_bank4__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext11_L3_OUTPUT_READY_L3BANK4_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK5",
                .symbol_name = "L3_OUTPUT_READY_L3BANK5",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext11__l3_output_ready_l3_bank5__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext11_L3_OUTPUT_READY_L3BANK5_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK6",
                .symbol_name = "L3_OUTPUT_READY_L3BANK6",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext11__l3_output_ready_l3_bank6__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext11_L3_OUTPUT_READY_L3BANK6_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK7",
                .symbol_name = "L3_OUTPUT_READY_L3BANK7",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext11__l3_output_ready_l3_bank7__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext11_L3_OUTPUT_READY_L3BANK7_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK8",
                .symbol_name = "L3_OUTPUT_READY_L3BANK8",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext11__l3_output_ready_l3_bank8__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext11_L3_OUTPUT_READY_L3BANK8_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK9",
                .symbol_name = "L3_OUTPUT_READY_L3BANK9",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext11__l3_output_ready_l3_bank9__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext11_L3_OUTPUT_READY_L3BANK9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext12_L3_OUTPUT_READY_L3BANK16_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext12_L3_OUTPUT_READY_L3BANK17_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext12_L3_OUTPUT_READY_L3BANK18_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext12_L3_OUTPUT_READY_L3BANK19_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext12_L3_OUTPUT_READY_L3BANK20_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext12_L3_OUTPUT_READY_L3BANK21_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext12_L3_OUTPUT_READY_L3BANK22_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext12_L3_OUTPUT_READY_L3BANK23_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext12_L3_OUTPUT_READY_L3BANK24_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext12_L3_OUTPUT_READY_L3BANK25_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext12_L3_OUTPUT_READY_L3BANK26_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext12_L3_OUTPUT_READY_L3BANK27_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext12_L3_OUTPUT_READY_L3BANK28_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext12_L3_OUTPUT_READY_L3BANK29_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext12_L3_OUTPUT_READY_L3BANK30_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext12_L3_OUTPUT_READY_L3BANK31_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext12_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext12";
    metric_set->symbol_name = "Ext12";
    metric_set->hw_config_guid = "a0add3fe-f028-4e6c-b104-c369fabe2b09";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext12_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext12__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext12__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext12__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext12__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 OUTPUT READY L3BANK16",
                .symbol_name = "L3_OUTPUT_READY_L3BANK16",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext12__l3_output_ready_l3_bank16__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext12_L3_OUTPUT_READY_L3BANK16_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK17",
                .symbol_name = "L3_OUTPUT_READY_L3BANK17",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext12__l3_output_ready_l3_bank17__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext12_L3_OUTPUT_READY_L3BANK17_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK18",
                .symbol_name = "L3_OUTPUT_READY_L3BANK18",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext12__l3_output_ready_l3_bank18__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext12_L3_OUTPUT_READY_L3BANK18_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK19",
                .symbol_name = "L3_OUTPUT_READY_L3BANK19",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext12__l3_output_ready_l3_bank19__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext12_L3_OUTPUT_READY_L3BANK19_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK20",
                .symbol_name = "L3_OUTPUT_READY_L3BANK20",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext12__l3_output_ready_l3_bank20__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext12_L3_OUTPUT_READY_L3BANK20_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK21",
                .symbol_name = "L3_OUTPUT_READY_L3BANK21",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext12__l3_output_ready_l3_bank21__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext12_L3_OUTPUT_READY_L3BANK21_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK22",
                .symbol_name = "L3_OUTPUT_READY_L3BANK22",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext12__l3_output_ready_l3_bank22__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext12_L3_OUTPUT_READY_L3BANK22_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK23",
                .symbol_name = "L3_OUTPUT_READY_L3BANK23",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext12__l3_output_ready_l3_bank23__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext12_L3_OUTPUT_READY_L3BANK23_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK24",
                .symbol_name = "L3_OUTPUT_READY_L3BANK24",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext12__l3_output_ready_l3_bank24__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext12_L3_OUTPUT_READY_L3BANK24_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK25",
                .symbol_name = "L3_OUTPUT_READY_L3BANK25",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext12__l3_output_ready_l3_bank25__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext12_L3_OUTPUT_READY_L3BANK25_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK26",
                .symbol_name = "L3_OUTPUT_READY_L3BANK26",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext12__l3_output_ready_l3_bank26__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext12_L3_OUTPUT_READY_L3BANK26_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK27",
                .symbol_name = "L3_OUTPUT_READY_L3BANK27",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext12__l3_output_ready_l3_bank27__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext12_L3_OUTPUT_READY_L3BANK27_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK28",
                .symbol_name = "L3_OUTPUT_READY_L3BANK28",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext12__l3_output_ready_l3_bank28__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext12_L3_OUTPUT_READY_L3BANK28_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK29",
                .symbol_name = "L3_OUTPUT_READY_L3BANK29",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext12__l3_output_ready_l3_bank29__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext12_L3_OUTPUT_READY_L3BANK29_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK30",
                .symbol_name = "L3_OUTPUT_READY_L3BANK30",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext12__l3_output_ready_l3_bank30__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext12_L3_OUTPUT_READY_L3BANK30_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK31",
                .symbol_name = "L3_OUTPUT_READY_L3BANK31",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext12__l3_output_ready_l3_bank31__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext12_L3_OUTPUT_READY_L3BANK31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext13_L3_BUSY_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext13_L3_BUSY_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext13_L3_BUSY_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext13_L3_BUSY_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext13_L3_BUSY_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext13_L3_BUSY_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext13_L3_BUSY_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext13_L3_BUSY_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext13_L3_BUSY_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext13_L3_BUSY_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext13_L3_BUSY_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext13_L3_BUSY_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext13_L3_BUSY_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext13_L3_BUSY_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext13_L3_BUSY_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext13_L3_BUSY_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext13_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext13";
    metric_set->symbol_name = "Ext13";
    metric_set->hw_config_guid = "4aeacf49-91c2-41bf-8d9f-49233689e36a";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext13_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext13__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext13__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext13__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext13__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BANK ACTIVE L3BANK0",
                .symbol_name = "L3_BUSY_L3BANK0",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext13__l3_busy_l3_bank0__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext13_L3_BUSY_L3BANK0_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK1",
                .symbol_name = "L3_BUSY_L3BANK1",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext13__l3_busy_l3_bank1__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext13_L3_BUSY_L3BANK1_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK10",
                .symbol_name = "L3_BUSY_L3BANK10",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext13__l3_busy_l3_bank10__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext13_L3_BUSY_L3BANK10_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK11",
                .symbol_name = "L3_BUSY_L3BANK11",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext13__l3_busy_l3_bank11__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext13_L3_BUSY_L3BANK11_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK12",
                .symbol_name = "L3_BUSY_L3BANK12",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext13__l3_busy_l3_bank12__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext13_L3_BUSY_L3BANK12_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK13",
                .symbol_name = "L3_BUSY_L3BANK13",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext13__l3_busy_l3_bank13__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext13_L3_BUSY_L3BANK13_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK14",
                .symbol_name = "L3_BUSY_L3BANK14",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext13__l3_busy_l3_bank14__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext13_L3_BUSY_L3BANK14_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK15",
                .symbol_name = "L3_BUSY_L3BANK15",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext13__l3_busy_l3_bank15__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext13_L3_BUSY_L3BANK15_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK2",
                .symbol_name = "L3_BUSY_L3BANK2",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext13__l3_busy_l3_bank2__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext13_L3_BUSY_L3BANK2_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK3",
                .symbol_name = "L3_BUSY_L3BANK3",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext13__l3_busy_l3_bank3__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext13_L3_BUSY_L3BANK3_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK4",
                .symbol_name = "L3_BUSY_L3BANK4",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext13__l3_busy_l3_bank4__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext13_L3_BUSY_L3BANK4_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK5",
                .symbol_name = "L3_BUSY_L3BANK5",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext13__l3_busy_l3_bank5__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext13_L3_BUSY_L3BANK5_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK6",
                .symbol_name = "L3_BUSY_L3BANK6",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext13__l3_busy_l3_bank6__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext13_L3_BUSY_L3BANK6_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK7",
                .symbol_name = "L3_BUSY_L3BANK7",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext13__l3_busy_l3_bank7__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext13_L3_BUSY_L3BANK7_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK8",
                .symbol_name = "L3_BUSY_L3BANK8",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext13__l3_busy_l3_bank8__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext13_L3_BUSY_L3BANK8_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK9",
                .symbol_name = "L3_BUSY_L3BANK9",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext13__l3_busy_l3_bank9__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext13_L3_BUSY_L3BANK9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext14_L3_BUSY_L3BANK16_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext14_L3_BUSY_L3BANK17_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext14_L3_BUSY_L3BANK18_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext14_L3_BUSY_L3BANK19_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext14_L3_BUSY_L3BANK20_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext14_L3_BUSY_L3BANK21_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext14_L3_BUSY_L3BANK22_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext14_L3_BUSY_L3BANK23_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext14_L3_BUSY_L3BANK24_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext14_L3_BUSY_L3BANK25_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext14_L3_BUSY_L3BANK26_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext14_L3_BUSY_L3BANK27_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext14_L3_BUSY_L3BANK28_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext14_L3_BUSY_L3BANK29_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext14_L3_BUSY_L3BANK30_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext14_L3_BUSY_L3BANK31_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext14_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext14";
    metric_set->symbol_name = "Ext14";
    metric_set->hw_config_guid = "60e3a9fa-b807-4a8d-8a83-88705d05e2c9";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext14_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext14__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext14__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext14__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext14__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BANK ACTIVE L3BANK16",
                .symbol_name = "L3_BUSY_L3BANK16",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext14__l3_busy_l3_bank16__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext14_L3_BUSY_L3BANK16_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK17",
                .symbol_name = "L3_BUSY_L3BANK17",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext14__l3_busy_l3_bank17__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext14_L3_BUSY_L3BANK17_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK18",
                .symbol_name = "L3_BUSY_L3BANK18",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext14__l3_busy_l3_bank18__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext14_L3_BUSY_L3BANK18_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK19",
                .symbol_name = "L3_BUSY_L3BANK19",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext14__l3_busy_l3_bank19__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext14_L3_BUSY_L3BANK19_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK20",
                .symbol_name = "L3_BUSY_L3BANK20",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext14__l3_busy_l3_bank20__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext14_L3_BUSY_L3BANK20_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK21",
                .symbol_name = "L3_BUSY_L3BANK21",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext14__l3_busy_l3_bank21__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext14_L3_BUSY_L3BANK21_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK22",
                .symbol_name = "L3_BUSY_L3BANK22",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext14__l3_busy_l3_bank22__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext14_L3_BUSY_L3BANK22_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK23",
                .symbol_name = "L3_BUSY_L3BANK23",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext14__l3_busy_l3_bank23__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext14_L3_BUSY_L3BANK23_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK24",
                .symbol_name = "L3_BUSY_L3BANK24",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext14__l3_busy_l3_bank24__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext14_L3_BUSY_L3BANK24_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK25",
                .symbol_name = "L3_BUSY_L3BANK25",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext14__l3_busy_l3_bank25__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext14_L3_BUSY_L3BANK25_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK26",
                .symbol_name = "L3_BUSY_L3BANK26",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext14__l3_busy_l3_bank26__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext14_L3_BUSY_L3BANK26_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK27",
                .symbol_name = "L3_BUSY_L3BANK27",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext14__l3_busy_l3_bank27__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext14_L3_BUSY_L3BANK27_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK28",
                .symbol_name = "L3_BUSY_L3BANK28",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext14__l3_busy_l3_bank28__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext14_L3_BUSY_L3BANK28_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK29",
                .symbol_name = "L3_BUSY_L3BANK29",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext14__l3_busy_l3_bank29__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext14_L3_BUSY_L3BANK29_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK30",
                .symbol_name = "L3_BUSY_L3BANK30",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext14__l3_busy_l3_bank30__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext14_L3_BUSY_L3BANK30_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK31",
                .symbol_name = "L3_BUSY_L3BANK31",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext14__l3_busy_l3_bank31__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext14_L3_BUSY_L3BANK31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext15_L3_STALL_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext15_L3_STALL_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext15_L3_STALL_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext15_L3_STALL_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext15_L3_STALL_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext15_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext15";
    metric_set->symbol_name = "Ext15";
    metric_set->hw_config_guid = "0aab7745-1e24-42af-9c96-c640e4f45aa9";
    metric_set->counters = calloc(8, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext15_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext15__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext15__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext15__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext15__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BANK STALL L3BANK0",
                .symbol_name = "L3_STALL_L3BANK0",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext15__l3_stall_l3_bank0__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext15_L3_STALL_L3BANK0_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK1",
                .symbol_name = "L3_STALL_L3BANK1",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext15__l3_stall_l3_bank1__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext15_L3_STALL_L3BANK1_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK2",
                .symbol_name = "L3_STALL_L3BANK2",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext15__l3_stall_l3_bank2__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext15_L3_STALL_L3BANK2_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK3",
                .symbol_name = "L3_STALL_L3BANK3",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext15__l3_stall_l3_bank3__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext15_L3_STALL_L3BANK3_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK4",
                .symbol_name = "L3_STALL_L3BANK4",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext15__l3_stall_l3_bank4__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext15_L3_STALL_L3BANK4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 8);
}

static bool acmgt3_ext16_L3_STALL_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext16_L3_STALL_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext16_L3_STALL_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext16_L3_STALL_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext16_L3_STALL_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext16_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext16";
    metric_set->symbol_name = "Ext16";
    metric_set->hw_config_guid = "97670487-9837-4cd2-9475-dea1d28d34fc";
    metric_set->counters = calloc(8, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext16_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext16__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext16__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext16__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext16__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BANK STALL L3BANK5",
                .symbol_name = "L3_STALL_L3BANK5",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext16__l3_stall_l3_bank5__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext16_L3_STALL_L3BANK5_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK6",
                .symbol_name = "L3_STALL_L3BANK6",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext16__l3_stall_l3_bank6__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext16_L3_STALL_L3BANK6_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK7",
                .symbol_name = "L3_STALL_L3BANK7",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext16__l3_stall_l3_bank7__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext16_L3_STALL_L3BANK7_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK8",
                .symbol_name = "L3_STALL_L3BANK8",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext16__l3_stall_l3_bank8__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext16_L3_STALL_L3BANK8_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK9",
                .symbol_name = "L3_STALL_L3BANK9",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext16__l3_stall_l3_bank9__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext16_L3_STALL_L3BANK9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 8);
}

static bool acmgt3_ext17_L3_STALL_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext17_L3_STALL_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext17_L3_STALL_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext17_L3_STALL_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext17_L3_STALL_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext17_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext17";
    metric_set->symbol_name = "Ext17";
    metric_set->hw_config_guid = "2908914a-a836-44ec-a053-36a7ed383462";
    metric_set->counters = calloc(8, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext17_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext17__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext17__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext17__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext17__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BANK STALL L3BANK10",
                .symbol_name = "L3_STALL_L3BANK10",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext17__l3_stall_l3_bank10__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext17_L3_STALL_L3BANK10_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK11",
                .symbol_name = "L3_STALL_L3BANK11",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext17__l3_stall_l3_bank11__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext17_L3_STALL_L3BANK11_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK12",
                .symbol_name = "L3_STALL_L3BANK12",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext17__l3_stall_l3_bank12__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext17_L3_STALL_L3BANK12_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK13",
                .symbol_name = "L3_STALL_L3BANK13",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext17__l3_stall_l3_bank13__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext17_L3_STALL_L3BANK13_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK14",
                .symbol_name = "L3_STALL_L3BANK14",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext17__l3_stall_l3_bank14__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext17_L3_STALL_L3BANK14_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 8);
}

static bool acmgt3_ext18_L3_STALL_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext18_L3_STALL_L3BANK16_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext18_L3_STALL_L3BANK17_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext18_L3_STALL_L3BANK18_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext18_L3_STALL_L3BANK19_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext18_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext18";
    metric_set->symbol_name = "Ext18";
    metric_set->hw_config_guid = "34f121ae-5907-4fe2-a237-a36940510708";
    metric_set->counters = calloc(8, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext18_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext18__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext18__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext18__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext18__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BANK STALL L3BANK15",
                .symbol_name = "L3_STALL_L3BANK15",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext18__l3_stall_l3_bank15__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext18_L3_STALL_L3BANK15_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK16",
                .symbol_name = "L3_STALL_L3BANK16",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext18__l3_stall_l3_bank16__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext18_L3_STALL_L3BANK16_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK17",
                .symbol_name = "L3_STALL_L3BANK17",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext18__l3_stall_l3_bank17__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext18_L3_STALL_L3BANK17_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK18",
                .symbol_name = "L3_STALL_L3BANK18",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext18__l3_stall_l3_bank18__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext18_L3_STALL_L3BANK18_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK19",
                .symbol_name = "L3_STALL_L3BANK19",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext18__l3_stall_l3_bank19__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext18_L3_STALL_L3BANK19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 8);
}

static bool acmgt3_ext19_L3_STALL_L3BANK20_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext19_L3_STALL_L3BANK21_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext19_L3_STALL_L3BANK22_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext19_L3_STALL_L3BANK23_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext19_L3_STALL_L3BANK24_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext19_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext19";
    metric_set->symbol_name = "Ext19";
    metric_set->hw_config_guid = "f3893d2b-10f8-48f6-8417-6ed748d3dccd";
    metric_set->counters = calloc(8, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext19_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext19__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext19__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext19__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext19__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BANK STALL L3BANK20",
                .symbol_name = "L3_STALL_L3BANK20",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext19__l3_stall_l3_bank20__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext19_L3_STALL_L3BANK20_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK21",
                .symbol_name = "L3_STALL_L3BANK21",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext19__l3_stall_l3_bank21__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext19_L3_STALL_L3BANK21_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK22",
                .symbol_name = "L3_STALL_L3BANK22",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext19__l3_stall_l3_bank22__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext19_L3_STALL_L3BANK22_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK23",
                .symbol_name = "L3_STALL_L3BANK23",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext19__l3_stall_l3_bank23__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext19_L3_STALL_L3BANK23_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK24",
                .symbol_name = "L3_STALL_L3BANK24",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext19__l3_stall_l3_bank24__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext19_L3_STALL_L3BANK24_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 8);
}

static bool acmgt3_ext20_L3_STALL_L3BANK25_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext20_L3_STALL_L3BANK26_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext20_L3_STALL_L3BANK27_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext20_L3_STALL_L3BANK28_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext20_L3_STALL_L3BANK29_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext20_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext20";
    metric_set->symbol_name = "Ext20";
    metric_set->hw_config_guid = "6b5ae61c-ceab-4202-b550-8430b037566c";
    metric_set->counters = calloc(8, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext20_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext20__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext20__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext20__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext20__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BANK STALL L3BANK25",
                .symbol_name = "L3_STALL_L3BANK25",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext20__l3_stall_l3_bank25__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext20_L3_STALL_L3BANK25_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK26",
                .symbol_name = "L3_STALL_L3BANK26",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext20__l3_stall_l3_bank26__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext20_L3_STALL_L3BANK26_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK27",
                .symbol_name = "L3_STALL_L3BANK27",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext20__l3_stall_l3_bank27__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext20_L3_STALL_L3BANK27_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK28",
                .symbol_name = "L3_STALL_L3BANK28",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext20__l3_stall_l3_bank28__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext20_L3_STALL_L3BANK28_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK29",
                .symbol_name = "L3_STALL_L3BANK29",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext20__l3_stall_l3_bank29__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext20_L3_STALL_L3BANK29_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 8);
}

static bool acmgt3_ext21_L3_READ_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext21_L3_READ_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext21_L3_READ_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext21_L3_READ_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext21_L3_READ_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext21_L3_READ_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext21_L3_READ_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext21_L3_READ_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext21_L3_READ_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext21_L3_READ_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext21_L3_READ_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext21_L3_READ_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext21_L3_READ_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext21_L3_READ_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext21_L3_READ_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext21_L3_READ_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext21_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext21";
    metric_set->symbol_name = "Ext21";
    metric_set->hw_config_guid = "66bbd7d1-f6a2-4189-99f7-8e360e28be45";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext21_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext21__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext21__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext21__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext21__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 READ L3BANK0",
                .symbol_name = "L3_READ_L3BANK0",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext21__l3_read_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext21_L3_READ_L3BANK0_availability,
            },

            {
                .name = "L3 READ L3BANK1",
                .symbol_name = "L3_READ_L3BANK1",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext21__l3_read_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext21_L3_READ_L3BANK1_availability,
            },

            {
                .name = "L3 READ L3BANK10",
                .symbol_name = "L3_READ_L3BANK10",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext21__l3_read_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext21_L3_READ_L3BANK10_availability,
            },

            {
                .name = "L3 READ L3BANK11",
                .symbol_name = "L3_READ_L3BANK11",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext21__l3_read_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext21_L3_READ_L3BANK11_availability,
            },

            {
                .name = "L3 READ L3BANK12",
                .symbol_name = "L3_READ_L3BANK12",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext21__l3_read_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext21_L3_READ_L3BANK12_availability,
            },

            {
                .name = "L3 READ L3BANK13",
                .symbol_name = "L3_READ_L3BANK13",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext21__l3_read_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext21_L3_READ_L3BANK13_availability,
            },

            {
                .name = "L3 READ L3BANK14",
                .symbol_name = "L3_READ_L3BANK14",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext21__l3_read_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext21_L3_READ_L3BANK14_availability,
            },

            {
                .name = "L3 READ L3BANK15",
                .symbol_name = "L3_READ_L3BANK15",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext21__l3_read_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext21_L3_READ_L3BANK15_availability,
            },

            {
                .name = "L3 READ L3BANK2",
                .symbol_name = "L3_READ_L3BANK2",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext21__l3_read_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext21_L3_READ_L3BANK2_availability,
            },

            {
                .name = "L3 READ L3BANK3",
                .symbol_name = "L3_READ_L3BANK3",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext21__l3_read_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext21_L3_READ_L3BANK3_availability,
            },

            {
                .name = "L3 READ L3BANK4",
                .symbol_name = "L3_READ_L3BANK4",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext21__l3_read_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext21_L3_READ_L3BANK4_availability,
            },

            {
                .name = "L3 READ L3BANK5",
                .symbol_name = "L3_READ_L3BANK5",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext21__l3_read_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext21_L3_READ_L3BANK5_availability,
            },

            {
                .name = "L3 READ L3BANK6",
                .symbol_name = "L3_READ_L3BANK6",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext21__l3_read_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext21_L3_READ_L3BANK6_availability,
            },

            {
                .name = "L3 READ L3BANK7",
                .symbol_name = "L3_READ_L3BANK7",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext21__l3_read_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext21_L3_READ_L3BANK7_availability,
            },

            {
                .name = "L3 READ L3BANK8",
                .symbol_name = "L3_READ_L3BANK8",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext21__l3_read_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext21_L3_READ_L3BANK8_availability,
            },

            {
                .name = "L3 READ L3BANK9",
                .symbol_name = "L3_READ_L3BANK9",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext21__l3_read_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext21_L3_READ_L3BANK9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext22_L3_READ_L3BANK16_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext22_L3_READ_L3BANK17_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext22_L3_READ_L3BANK18_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext22_L3_READ_L3BANK19_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext22_L3_READ_L3BANK20_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext22_L3_READ_L3BANK21_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext22_L3_READ_L3BANK22_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext22_L3_READ_L3BANK23_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext22_L3_READ_L3BANK24_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext22_L3_READ_L3BANK25_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext22_L3_READ_L3BANK26_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext22_L3_READ_L3BANK27_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext22_L3_READ_L3BANK28_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext22_L3_READ_L3BANK29_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext22_L3_READ_L3BANK30_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext22_L3_READ_L3BANK31_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext22_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext22";
    metric_set->symbol_name = "Ext22";
    metric_set->hw_config_guid = "b8a9f40b-5906-46b2-ad95-8d36eb9cf998";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext22_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext22__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext22__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext22__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext22__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 READ L3BANK16",
                .symbol_name = "L3_READ_L3BANK16",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext22__l3_read_l3_bank16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext22_L3_READ_L3BANK16_availability,
            },

            {
                .name = "L3 READ L3BANK17",
                .symbol_name = "L3_READ_L3BANK17",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext22__l3_read_l3_bank17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext22_L3_READ_L3BANK17_availability,
            },

            {
                .name = "L3 READ L3BANK18",
                .symbol_name = "L3_READ_L3BANK18",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext22__l3_read_l3_bank18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext22_L3_READ_L3BANK18_availability,
            },

            {
                .name = "L3 READ L3BANK19",
                .symbol_name = "L3_READ_L3BANK19",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext22__l3_read_l3_bank19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext22_L3_READ_L3BANK19_availability,
            },

            {
                .name = "L3 READ L3BANK20",
                .symbol_name = "L3_READ_L3BANK20",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext22__l3_read_l3_bank20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext22_L3_READ_L3BANK20_availability,
            },

            {
                .name = "L3 READ L3BANK21",
                .symbol_name = "L3_READ_L3BANK21",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext22__l3_read_l3_bank21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext22_L3_READ_L3BANK21_availability,
            },

            {
                .name = "L3 READ L3BANK22",
                .symbol_name = "L3_READ_L3BANK22",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext22__l3_read_l3_bank22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext22_L3_READ_L3BANK22_availability,
            },

            {
                .name = "L3 READ L3BANK23",
                .symbol_name = "L3_READ_L3BANK23",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext22__l3_read_l3_bank23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext22_L3_READ_L3BANK23_availability,
            },

            {
                .name = "L3 READ L3BANK24",
                .symbol_name = "L3_READ_L3BANK24",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext22__l3_read_l3_bank24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext22_L3_READ_L3BANK24_availability,
            },

            {
                .name = "L3 READ L3BANK25",
                .symbol_name = "L3_READ_L3BANK25",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext22__l3_read_l3_bank25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext22_L3_READ_L3BANK25_availability,
            },

            {
                .name = "L3 READ L3BANK26",
                .symbol_name = "L3_READ_L3BANK26",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext22__l3_read_l3_bank26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext22_L3_READ_L3BANK26_availability,
            },

            {
                .name = "L3 READ L3BANK27",
                .symbol_name = "L3_READ_L3BANK27",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext22__l3_read_l3_bank27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext22_L3_READ_L3BANK27_availability,
            },

            {
                .name = "L3 READ L3BANK28",
                .symbol_name = "L3_READ_L3BANK28",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext22__l3_read_l3_bank28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext22_L3_READ_L3BANK28_availability,
            },

            {
                .name = "L3 READ L3BANK29",
                .symbol_name = "L3_READ_L3BANK29",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext22__l3_read_l3_bank29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext22_L3_READ_L3BANK29_availability,
            },

            {
                .name = "L3 READ L3BANK30",
                .symbol_name = "L3_READ_L3BANK30",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext22__l3_read_l3_bank30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext22_L3_READ_L3BANK30_availability,
            },

            {
                .name = "L3 READ L3BANK31",
                .symbol_name = "L3_READ_L3BANK31",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext22__l3_read_l3_bank31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext22_L3_READ_L3BANK31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext23_L3_WRITE_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext23_L3_WRITE_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext23_L3_WRITE_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext23_L3_WRITE_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext23_L3_WRITE_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext23_L3_WRITE_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext23_L3_WRITE_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext23_L3_WRITE_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext23_L3_WRITE_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext23_L3_WRITE_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext23_L3_WRITE_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext23_L3_WRITE_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext23_L3_WRITE_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext23_L3_WRITE_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext23_L3_WRITE_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext23_L3_WRITE_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext23_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext23";
    metric_set->symbol_name = "Ext23";
    metric_set->hw_config_guid = "e5d242d2-5bf6-4380-8f7c-cb0ff2372733";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext23_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext23__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext23__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext23__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext23__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 WRITE L3BANK0",
                .symbol_name = "L3_WRITE_L3BANK0",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext23__l3_write_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext23_L3_WRITE_L3BANK0_availability,
            },

            {
                .name = "L3 WRITE L3BANK1",
                .symbol_name = "L3_WRITE_L3BANK1",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext23__l3_write_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext23_L3_WRITE_L3BANK1_availability,
            },

            {
                .name = "L3 WRITE L3BANK10",
                .symbol_name = "L3_WRITE_L3BANK10",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext23__l3_write_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext23_L3_WRITE_L3BANK10_availability,
            },

            {
                .name = "L3 WRITE L3BANK11",
                .symbol_name = "L3_WRITE_L3BANK11",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext23__l3_write_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext23_L3_WRITE_L3BANK11_availability,
            },

            {
                .name = "L3 WRITE L3BANK12",
                .symbol_name = "L3_WRITE_L3BANK12",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext23__l3_write_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext23_L3_WRITE_L3BANK12_availability,
            },

            {
                .name = "L3 WRITE L3BANK13",
                .symbol_name = "L3_WRITE_L3BANK13",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext23__l3_write_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext23_L3_WRITE_L3BANK13_availability,
            },

            {
                .name = "L3 WRITE L3BANK14",
                .symbol_name = "L3_WRITE_L3BANK14",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext23__l3_write_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext23_L3_WRITE_L3BANK14_availability,
            },

            {
                .name = "L3 WRITE L3BANK15",
                .symbol_name = "L3_WRITE_L3BANK15",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext23__l3_write_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext23_L3_WRITE_L3BANK15_availability,
            },

            {
                .name = "L3 WRITE L3BANK2",
                .symbol_name = "L3_WRITE_L3BANK2",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext23__l3_write_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext23_L3_WRITE_L3BANK2_availability,
            },

            {
                .name = "L3 WRITE L3BANK3",
                .symbol_name = "L3_WRITE_L3BANK3",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext23__l3_write_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext23_L3_WRITE_L3BANK3_availability,
            },

            {
                .name = "L3 WRITE L3BANK4",
                .symbol_name = "L3_WRITE_L3BANK4",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext23__l3_write_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext23_L3_WRITE_L3BANK4_availability,
            },

            {
                .name = "L3 WRITE L3BANK5",
                .symbol_name = "L3_WRITE_L3BANK5",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext23__l3_write_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext23_L3_WRITE_L3BANK5_availability,
            },

            {
                .name = "L3 WRITE L3BANK6",
                .symbol_name = "L3_WRITE_L3BANK6",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext23__l3_write_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext23_L3_WRITE_L3BANK6_availability,
            },

            {
                .name = "L3 WRITE L3BANK7",
                .symbol_name = "L3_WRITE_L3BANK7",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext23__l3_write_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext23_L3_WRITE_L3BANK7_availability,
            },

            {
                .name = "L3 WRITE L3BANK8",
                .symbol_name = "L3_WRITE_L3BANK8",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext23__l3_write_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext23_L3_WRITE_L3BANK8_availability,
            },

            {
                .name = "L3 WRITE L3BANK9",
                .symbol_name = "L3_WRITE_L3BANK9",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext23__l3_write_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext23_L3_WRITE_L3BANK9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext24_L3_WRITE_L3BANK16_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext24_L3_WRITE_L3BANK17_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext24_L3_WRITE_L3BANK18_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext24_L3_WRITE_L3BANK19_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext24_L3_WRITE_L3BANK20_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext24_L3_WRITE_L3BANK21_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext24_L3_WRITE_L3BANK22_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext24_L3_WRITE_L3BANK23_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext24_L3_WRITE_L3BANK24_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext24_L3_WRITE_L3BANK25_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext24_L3_WRITE_L3BANK26_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext24_L3_WRITE_L3BANK27_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext24_L3_WRITE_L3BANK28_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext24_L3_WRITE_L3BANK29_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext24_L3_WRITE_L3BANK30_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext24_L3_WRITE_L3BANK31_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext24_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext24";
    metric_set->symbol_name = "Ext24";
    metric_set->hw_config_guid = "b6096e7e-a2c9-4622-9bd6-2169cdebc490";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext24_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext24__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext24__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext24__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext24__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 WRITE L3BANK16",
                .symbol_name = "L3_WRITE_L3BANK16",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext24__l3_write_l3_bank16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext24_L3_WRITE_L3BANK16_availability,
            },

            {
                .name = "L3 WRITE L3BANK17",
                .symbol_name = "L3_WRITE_L3BANK17",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext24__l3_write_l3_bank17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext24_L3_WRITE_L3BANK17_availability,
            },

            {
                .name = "L3 WRITE L3BANK18",
                .symbol_name = "L3_WRITE_L3BANK18",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext24__l3_write_l3_bank18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext24_L3_WRITE_L3BANK18_availability,
            },

            {
                .name = "L3 WRITE L3BANK19",
                .symbol_name = "L3_WRITE_L3BANK19",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext24__l3_write_l3_bank19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext24_L3_WRITE_L3BANK19_availability,
            },

            {
                .name = "L3 WRITE L3BANK20",
                .symbol_name = "L3_WRITE_L3BANK20",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext24__l3_write_l3_bank20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext24_L3_WRITE_L3BANK20_availability,
            },

            {
                .name = "L3 WRITE L3BANK21",
                .symbol_name = "L3_WRITE_L3BANK21",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext24__l3_write_l3_bank21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext24_L3_WRITE_L3BANK21_availability,
            },

            {
                .name = "L3 WRITE L3BANK22",
                .symbol_name = "L3_WRITE_L3BANK22",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext24__l3_write_l3_bank22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext24_L3_WRITE_L3BANK22_availability,
            },

            {
                .name = "L3 WRITE L3BANK23",
                .symbol_name = "L3_WRITE_L3BANK23",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext24__l3_write_l3_bank23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext24_L3_WRITE_L3BANK23_availability,
            },

            {
                .name = "L3 WRITE L3BANK24",
                .symbol_name = "L3_WRITE_L3BANK24",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext24__l3_write_l3_bank24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext24_L3_WRITE_L3BANK24_availability,
            },

            {
                .name = "L3 WRITE L3BANK25",
                .symbol_name = "L3_WRITE_L3BANK25",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext24__l3_write_l3_bank25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext24_L3_WRITE_L3BANK25_availability,
            },

            {
                .name = "L3 WRITE L3BANK26",
                .symbol_name = "L3_WRITE_L3BANK26",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext24__l3_write_l3_bank26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext24_L3_WRITE_L3BANK26_availability,
            },

            {
                .name = "L3 WRITE L3BANK27",
                .symbol_name = "L3_WRITE_L3BANK27",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext24__l3_write_l3_bank27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext24_L3_WRITE_L3BANK27_availability,
            },

            {
                .name = "L3 WRITE L3BANK28",
                .symbol_name = "L3_WRITE_L3BANK28",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext24__l3_write_l3_bank28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext24_L3_WRITE_L3BANK28_availability,
            },

            {
                .name = "L3 WRITE L3BANK29",
                .symbol_name = "L3_WRITE_L3BANK29",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext24__l3_write_l3_bank29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext24_L3_WRITE_L3BANK29_availability,
            },

            {
                .name = "L3 WRITE L3BANK30",
                .symbol_name = "L3_WRITE_L3BANK30",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext24__l3_write_l3_bank30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext24_L3_WRITE_L3BANK30_availability,
            },

            {
                .name = "L3 WRITE L3BANK31",
                .symbol_name = "L3_WRITE_L3BANK31",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext24__l3_write_l3_bank31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext24_L3_WRITE_L3BANK31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext27_L3_MISS_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext27_L3_MISS_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext27_L3_MISS_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext27_L3_MISS_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext27_L3_MISS_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext27_L3_MISS_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext27_L3_MISS_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext27_L3_MISS_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext27_L3_MISS_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext27_L3_MISS_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext27_L3_MISS_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext27_L3_MISS_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext27_L3_MISS_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext27_L3_MISS_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext27_L3_MISS_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext27_L3_MISS_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext27_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext27";
    metric_set->symbol_name = "Ext27";
    metric_set->hw_config_guid = "c7b9f883-12c5-470c-ab75-790961e66be6";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext27_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext27__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext27__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext27__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext27__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 MISS L3BANK0",
                .symbol_name = "L3_MISS_L3BANK0",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext27__l3_miss_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext27_L3_MISS_L3BANK0_availability,
            },

            {
                .name = "L3 MISS L3BANK1",
                .symbol_name = "L3_MISS_L3BANK1",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext27__l3_miss_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext27_L3_MISS_L3BANK1_availability,
            },

            {
                .name = "L3 MISS L3BANK10",
                .symbol_name = "L3_MISS_L3BANK10",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext27__l3_miss_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext27_L3_MISS_L3BANK10_availability,
            },

            {
                .name = "L3 MISS L3BANK11",
                .symbol_name = "L3_MISS_L3BANK11",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext27__l3_miss_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext27_L3_MISS_L3BANK11_availability,
            },

            {
                .name = "L3 MISS L3BANK12",
                .symbol_name = "L3_MISS_L3BANK12",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext27__l3_miss_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext27_L3_MISS_L3BANK12_availability,
            },

            {
                .name = "L3 MISS L3BANK13",
                .symbol_name = "L3_MISS_L3BANK13",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext27__l3_miss_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext27_L3_MISS_L3BANK13_availability,
            },

            {
                .name = "L3 MISS L3BANK14",
                .symbol_name = "L3_MISS_L3BANK14",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext27__l3_miss_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext27_L3_MISS_L3BANK14_availability,
            },

            {
                .name = "L3 MISS L3BANK15",
                .symbol_name = "L3_MISS_L3BANK15",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext27__l3_miss_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext27_L3_MISS_L3BANK15_availability,
            },

            {
                .name = "L3 MISS L3BANK2",
                .symbol_name = "L3_MISS_L3BANK2",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext27__l3_miss_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext27_L3_MISS_L3BANK2_availability,
            },

            {
                .name = "L3 MISS L3BANK3",
                .symbol_name = "L3_MISS_L3BANK3",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext27__l3_miss_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext27_L3_MISS_L3BANK3_availability,
            },

            {
                .name = "L3 MISS L3BANK4",
                .symbol_name = "L3_MISS_L3BANK4",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext27__l3_miss_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext27_L3_MISS_L3BANK4_availability,
            },

            {
                .name = "L3 MISS L3BANK5",
                .symbol_name = "L3_MISS_L3BANK5",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext27__l3_miss_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext27_L3_MISS_L3BANK5_availability,
            },

            {
                .name = "L3 MISS L3BANK6",
                .symbol_name = "L3_MISS_L3BANK6",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext27__l3_miss_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext27_L3_MISS_L3BANK6_availability,
            },

            {
                .name = "L3 MISS L3BANK7",
                .symbol_name = "L3_MISS_L3BANK7",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext27__l3_miss_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext27_L3_MISS_L3BANK7_availability,
            },

            {
                .name = "L3 MISS L3BANK8",
                .symbol_name = "L3_MISS_L3BANK8",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext27__l3_miss_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext27_L3_MISS_L3BANK8_availability,
            },

            {
                .name = "L3 MISS L3BANK9",
                .symbol_name = "L3_MISS_L3BANK9",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext27__l3_miss_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext27_L3_MISS_L3BANK9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext28_L3_MISS_L3BANK16_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext28_L3_MISS_L3BANK17_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext28_L3_MISS_L3BANK18_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext28_L3_MISS_L3BANK19_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext28_L3_MISS_L3BANK20_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext28_L3_MISS_L3BANK21_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext28_L3_MISS_L3BANK22_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext28_L3_MISS_L3BANK23_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext28_L3_MISS_L3BANK24_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext28_L3_MISS_L3BANK25_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext28_L3_MISS_L3BANK26_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext28_L3_MISS_L3BANK27_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext28_L3_MISS_L3BANK28_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext28_L3_MISS_L3BANK29_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext28_L3_MISS_L3BANK30_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext28_L3_MISS_L3BANK31_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext28_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext28";
    metric_set->symbol_name = "Ext28";
    metric_set->hw_config_guid = "78161cec-30c8-4b7f-aab8-6f13139f454e";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext28_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext28__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext28__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext28__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext28__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 MISS L3BANK16",
                .symbol_name = "L3_MISS_L3BANK16",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext28__l3_miss_l3_bank16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext28_L3_MISS_L3BANK16_availability,
            },

            {
                .name = "L3 MISS L3BANK17",
                .symbol_name = "L3_MISS_L3BANK17",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext28__l3_miss_l3_bank17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext28_L3_MISS_L3BANK17_availability,
            },

            {
                .name = "L3 MISS L3BANK18",
                .symbol_name = "L3_MISS_L3BANK18",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext28__l3_miss_l3_bank18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext28_L3_MISS_L3BANK18_availability,
            },

            {
                .name = "L3 MISS L3BANK19",
                .symbol_name = "L3_MISS_L3BANK19",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext28__l3_miss_l3_bank19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext28_L3_MISS_L3BANK19_availability,
            },

            {
                .name = "L3 MISS L3BANK20",
                .symbol_name = "L3_MISS_L3BANK20",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext28__l3_miss_l3_bank20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext28_L3_MISS_L3BANK20_availability,
            },

            {
                .name = "L3 MISS L3BANK21",
                .symbol_name = "L3_MISS_L3BANK21",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext28__l3_miss_l3_bank21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext28_L3_MISS_L3BANK21_availability,
            },

            {
                .name = "L3 MISS L3BANK22",
                .symbol_name = "L3_MISS_L3BANK22",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext28__l3_miss_l3_bank22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext28_L3_MISS_L3BANK22_availability,
            },

            {
                .name = "L3 MISS L3BANK23",
                .symbol_name = "L3_MISS_L3BANK23",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext28__l3_miss_l3_bank23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext28_L3_MISS_L3BANK23_availability,
            },

            {
                .name = "L3 MISS L3BANK24",
                .symbol_name = "L3_MISS_L3BANK24",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext28__l3_miss_l3_bank24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext28_L3_MISS_L3BANK24_availability,
            },

            {
                .name = "L3 MISS L3BANK25",
                .symbol_name = "L3_MISS_L3BANK25",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext28__l3_miss_l3_bank25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext28_L3_MISS_L3BANK25_availability,
            },

            {
                .name = "L3 MISS L3BANK26",
                .symbol_name = "L3_MISS_L3BANK26",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext28__l3_miss_l3_bank26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext28_L3_MISS_L3BANK26_availability,
            },

            {
                .name = "L3 MISS L3BANK27",
                .symbol_name = "L3_MISS_L3BANK27",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext28__l3_miss_l3_bank27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext28_L3_MISS_L3BANK27_availability,
            },

            {
                .name = "L3 MISS L3BANK28",
                .symbol_name = "L3_MISS_L3BANK28",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext28__l3_miss_l3_bank28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext28_L3_MISS_L3BANK28_availability,
            },

            {
                .name = "L3 MISS L3BANK29",
                .symbol_name = "L3_MISS_L3BANK29",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext28__l3_miss_l3_bank29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext28_L3_MISS_L3BANK29_availability,
            },

            {
                .name = "L3 MISS L3BANK30",
                .symbol_name = "L3_MISS_L3BANK30",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext28__l3_miss_l3_bank30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext28_L3_MISS_L3BANK30_availability,
            },

            {
                .name = "L3 MISS L3BANK31",
                .symbol_name = "L3_MISS_L3BANK31",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext28__l3_miss_l3_bank31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext28_L3_MISS_L3BANK31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext29_DATAPORT_L3_READ_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext29_DATAPORT_L3_READ_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext29_DATAPORT_L3_READ_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext29_DATAPORT_L3_READ_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext29_DATAPORT_L3_READ_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext29_DATAPORT_L3_READ_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext29_DATAPORT_L3_READ_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext29_DATAPORT_L3_READ_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext29_DATAPORT_L3_READ_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext29_DATAPORT_L3_READ_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext29_DATAPORT_L3_READ_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext29_DATAPORT_L3_READ_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext29_DATAPORT_L3_READ_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext29_DATAPORT_L3_READ_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext29_DATAPORT_L3_READ_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext29_DATAPORT_L3_READ_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext29_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext29";
    metric_set->symbol_name = "Ext29";
    metric_set->hw_config_guid = "e9ba5301-d2ca-4978-af6e-19096ad16dbb";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext29_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext29__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext29__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT L3 READ L3BANK0",
                .symbol_name = "DATAPORT_L3_READ_L3BANK0",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext29__dataport_l3_read_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext29_DATAPORT_L3_READ_L3BANK0_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK1",
                .symbol_name = "DATAPORT_L3_READ_L3BANK1",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext29__dataport_l3_read_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext29_DATAPORT_L3_READ_L3BANK1_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK10",
                .symbol_name = "DATAPORT_L3_READ_L3BANK10",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext29__dataport_l3_read_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext29_DATAPORT_L3_READ_L3BANK10_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK11",
                .symbol_name = "DATAPORT_L3_READ_L3BANK11",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext29__dataport_l3_read_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext29_DATAPORT_L3_READ_L3BANK11_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK12",
                .symbol_name = "DATAPORT_L3_READ_L3BANK12",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext29__dataport_l3_read_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext29_DATAPORT_L3_READ_L3BANK12_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK13",
                .symbol_name = "DATAPORT_L3_READ_L3BANK13",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext29__dataport_l3_read_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext29_DATAPORT_L3_READ_L3BANK13_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK14",
                .symbol_name = "DATAPORT_L3_READ_L3BANK14",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext29__dataport_l3_read_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext29_DATAPORT_L3_READ_L3BANK14_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK15",
                .symbol_name = "DATAPORT_L3_READ_L3BANK15",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext29__dataport_l3_read_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext29_DATAPORT_L3_READ_L3BANK15_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK2",
                .symbol_name = "DATAPORT_L3_READ_L3BANK2",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext29__dataport_l3_read_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext29_DATAPORT_L3_READ_L3BANK2_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK3",
                .symbol_name = "DATAPORT_L3_READ_L3BANK3",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext29__dataport_l3_read_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext29_DATAPORT_L3_READ_L3BANK3_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK4",
                .symbol_name = "DATAPORT_L3_READ_L3BANK4",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext29__dataport_l3_read_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext29_DATAPORT_L3_READ_L3BANK4_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK5",
                .symbol_name = "DATAPORT_L3_READ_L3BANK5",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext29__dataport_l3_read_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext29_DATAPORT_L3_READ_L3BANK5_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK6",
                .symbol_name = "DATAPORT_L3_READ_L3BANK6",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext29__dataport_l3_read_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext29_DATAPORT_L3_READ_L3BANK6_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK7",
                .symbol_name = "DATAPORT_L3_READ_L3BANK7",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext29__dataport_l3_read_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext29_DATAPORT_L3_READ_L3BANK7_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK8",
                .symbol_name = "DATAPORT_L3_READ_L3BANK8",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext29__dataport_l3_read_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext29_DATAPORT_L3_READ_L3BANK8_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK9",
                .symbol_name = "DATAPORT_L3_READ_L3BANK9",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext29__dataport_l3_read_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext29_DATAPORT_L3_READ_L3BANK9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext29__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext29__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext30_DATAPORT_L3_READ_L3BANK16_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext30_DATAPORT_L3_READ_L3BANK17_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext30_DATAPORT_L3_READ_L3BANK18_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext30_DATAPORT_L3_READ_L3BANK19_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext30_DATAPORT_L3_READ_L3BANK20_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext30_DATAPORT_L3_READ_L3BANK21_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext30_DATAPORT_L3_READ_L3BANK22_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext30_DATAPORT_L3_READ_L3BANK23_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext30_DATAPORT_L3_READ_L3BANK24_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext30_DATAPORT_L3_READ_L3BANK25_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext30_DATAPORT_L3_READ_L3BANK26_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext30_DATAPORT_L3_READ_L3BANK27_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext30_DATAPORT_L3_READ_L3BANK28_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext30_DATAPORT_L3_READ_L3BANK29_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext30_DATAPORT_L3_READ_L3BANK30_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext30_DATAPORT_L3_READ_L3BANK31_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext30_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext30";
    metric_set->symbol_name = "Ext30";
    metric_set->hw_config_guid = "cae0eb96-c3e6-4a3a-83e2-e939146602b5";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext30_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext30__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext30__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT L3 READ L3BANK16",
                .symbol_name = "DATAPORT_L3_READ_L3BANK16",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext30__dataport_l3_read_l3_bank16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext30_DATAPORT_L3_READ_L3BANK16_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK17",
                .symbol_name = "DATAPORT_L3_READ_L3BANK17",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext30__dataport_l3_read_l3_bank17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext30_DATAPORT_L3_READ_L3BANK17_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK18",
                .symbol_name = "DATAPORT_L3_READ_L3BANK18",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext30__dataport_l3_read_l3_bank18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext30_DATAPORT_L3_READ_L3BANK18_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK19",
                .symbol_name = "DATAPORT_L3_READ_L3BANK19",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext30__dataport_l3_read_l3_bank19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext30_DATAPORT_L3_READ_L3BANK19_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK20",
                .symbol_name = "DATAPORT_L3_READ_L3BANK20",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext30__dataport_l3_read_l3_bank20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext30_DATAPORT_L3_READ_L3BANK20_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK21",
                .symbol_name = "DATAPORT_L3_READ_L3BANK21",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext30__dataport_l3_read_l3_bank21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext30_DATAPORT_L3_READ_L3BANK21_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK22",
                .symbol_name = "DATAPORT_L3_READ_L3BANK22",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext30__dataport_l3_read_l3_bank22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext30_DATAPORT_L3_READ_L3BANK22_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK23",
                .symbol_name = "DATAPORT_L3_READ_L3BANK23",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext30__dataport_l3_read_l3_bank23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext30_DATAPORT_L3_READ_L3BANK23_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK24",
                .symbol_name = "DATAPORT_L3_READ_L3BANK24",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext30__dataport_l3_read_l3_bank24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext30_DATAPORT_L3_READ_L3BANK24_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK25",
                .symbol_name = "DATAPORT_L3_READ_L3BANK25",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext30__dataport_l3_read_l3_bank25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext30_DATAPORT_L3_READ_L3BANK25_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK26",
                .symbol_name = "DATAPORT_L3_READ_L3BANK26",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext30__dataport_l3_read_l3_bank26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext30_DATAPORT_L3_READ_L3BANK26_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK27",
                .symbol_name = "DATAPORT_L3_READ_L3BANK27",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext30__dataport_l3_read_l3_bank27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext30_DATAPORT_L3_READ_L3BANK27_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK28",
                .symbol_name = "DATAPORT_L3_READ_L3BANK28",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext30__dataport_l3_read_l3_bank28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext30_DATAPORT_L3_READ_L3BANK28_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK29",
                .symbol_name = "DATAPORT_L3_READ_L3BANK29",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext30__dataport_l3_read_l3_bank29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext30_DATAPORT_L3_READ_L3BANK29_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK30",
                .symbol_name = "DATAPORT_L3_READ_L3BANK30",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext30__dataport_l3_read_l3_bank30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext30_DATAPORT_L3_READ_L3BANK30_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK31",
                .symbol_name = "DATAPORT_L3_READ_L3BANK31",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext30__dataport_l3_read_l3_bank31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext30_DATAPORT_L3_READ_L3BANK31_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext30__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext30__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext31_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext31";
    metric_set->symbol_name = "Ext31";
    metric_set->hw_config_guid = "002950f1-a311-45f9-b88e-2276f42d8f92";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext31_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext31__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext31__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK0",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK0",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext31__dataport_l3_write_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK0_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK1",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK1",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext31__dataport_l3_write_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK1_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK10",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK10",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext31__dataport_l3_write_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK10_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK11",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK11",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext31__dataport_l3_write_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK11_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK12",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK12",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext31__dataport_l3_write_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK12_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK13",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK13",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext31__dataport_l3_write_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK13_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK14",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK14",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext31__dataport_l3_write_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK14_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK15",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK15",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext31__dataport_l3_write_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK15_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK2",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK2",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext31__dataport_l3_write_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK2_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK3",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK3",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext31__dataport_l3_write_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK3_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK4",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK4",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext31__dataport_l3_write_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK4_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK5",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK5",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext31__dataport_l3_write_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK5_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK6",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK6",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext31__dataport_l3_write_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK6_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK7",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK7",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext31__dataport_l3_write_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK7_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK8",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK8",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext31__dataport_l3_write_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK8_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK9",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK9",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext31__dataport_l3_write_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext31_DATAPORT_L3_WRITE_L3BANK9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext31__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext31__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK16_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK17_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK18_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK19_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK20_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK21_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK22_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK23_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK24_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK25_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK26_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK27_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK28_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK29_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK30_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK31_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext32_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext32";
    metric_set->symbol_name = "Ext32";
    metric_set->hw_config_guid = "98b27683-8d7c-4b3e-92d9-3c3683b2cc38";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext32_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext32__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext32__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK16",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK16",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext32__dataport_l3_write_l3_bank16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK16_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK17",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK17",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext32__dataport_l3_write_l3_bank17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK17_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK18",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK18",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext32__dataport_l3_write_l3_bank18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK18_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK19",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK19",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext32__dataport_l3_write_l3_bank19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK19_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK20",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK20",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext32__dataport_l3_write_l3_bank20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK20_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK21",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK21",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext32__dataport_l3_write_l3_bank21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK21_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK22",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK22",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext32__dataport_l3_write_l3_bank22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK22_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK23",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK23",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext32__dataport_l3_write_l3_bank23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK23_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK24",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK24",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext32__dataport_l3_write_l3_bank24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK24_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK25",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK25",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext32__dataport_l3_write_l3_bank25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK25_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK26",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK26",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext32__dataport_l3_write_l3_bank26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK26_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK27",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK27",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext32__dataport_l3_write_l3_bank27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK27_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK28",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK28",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext32__dataport_l3_write_l3_bank28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK28_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK29",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK29",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext32__dataport_l3_write_l3_bank29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK29_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK30",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK30",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext32__dataport_l3_write_l3_bank30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK30_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK31",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK31",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext32__dataport_l3_write_l3_bank31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext32_DATAPORT_L3_WRITE_L3BANK31_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext32__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext32__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext33_ICACHE_L3_READ_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext33_ICACHE_L3_READ_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext33_ICACHE_L3_READ_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext33_ICACHE_L3_READ_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext33_ICACHE_L3_READ_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext33_ICACHE_L3_READ_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext33_ICACHE_L3_READ_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext33_ICACHE_L3_READ_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext33_ICACHE_L3_READ_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext33_ICACHE_L3_READ_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext33_ICACHE_L3_READ_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext33_ICACHE_L3_READ_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext33_ICACHE_L3_READ_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext33_ICACHE_L3_READ_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext33_ICACHE_L3_READ_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext33_ICACHE_L3_READ_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext33_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext33";
    metric_set->symbol_name = "Ext33";
    metric_set->hw_config_guid = "57d03ea4-1959-4b4f-8a32-abaa96246b1d";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext33_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext33__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext33__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext33__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext33__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE L3 READ L3BANK0",
                .symbol_name = "ICACHE_L3_READ_L3BANK0",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext33__icache_l3_read_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext33_ICACHE_L3_READ_L3BANK0_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK1",
                .symbol_name = "ICACHE_L3_READ_L3BANK1",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext33__icache_l3_read_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext33_ICACHE_L3_READ_L3BANK1_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK10",
                .symbol_name = "ICACHE_L3_READ_L3BANK10",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext33__icache_l3_read_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext33_ICACHE_L3_READ_L3BANK10_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK11",
                .symbol_name = "ICACHE_L3_READ_L3BANK11",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext33__icache_l3_read_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext33_ICACHE_L3_READ_L3BANK11_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK12",
                .symbol_name = "ICACHE_L3_READ_L3BANK12",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext33__icache_l3_read_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext33_ICACHE_L3_READ_L3BANK12_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK13",
                .symbol_name = "ICACHE_L3_READ_L3BANK13",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext33__icache_l3_read_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext33_ICACHE_L3_READ_L3BANK13_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK14",
                .symbol_name = "ICACHE_L3_READ_L3BANK14",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext33__icache_l3_read_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext33_ICACHE_L3_READ_L3BANK14_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK15",
                .symbol_name = "ICACHE_L3_READ_L3BANK15",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext33__icache_l3_read_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext33_ICACHE_L3_READ_L3BANK15_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK2",
                .symbol_name = "ICACHE_L3_READ_L3BANK2",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext33__icache_l3_read_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext33_ICACHE_L3_READ_L3BANK2_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK3",
                .symbol_name = "ICACHE_L3_READ_L3BANK3",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext33__icache_l3_read_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext33_ICACHE_L3_READ_L3BANK3_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK4",
                .symbol_name = "ICACHE_L3_READ_L3BANK4",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext33__icache_l3_read_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext33_ICACHE_L3_READ_L3BANK4_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK5",
                .symbol_name = "ICACHE_L3_READ_L3BANK5",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext33__icache_l3_read_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext33_ICACHE_L3_READ_L3BANK5_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK6",
                .symbol_name = "ICACHE_L3_READ_L3BANK6",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext33__icache_l3_read_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext33_ICACHE_L3_READ_L3BANK6_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK7",
                .symbol_name = "ICACHE_L3_READ_L3BANK7",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext33__icache_l3_read_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext33_ICACHE_L3_READ_L3BANK7_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK8",
                .symbol_name = "ICACHE_L3_READ_L3BANK8",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext33__icache_l3_read_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext33_ICACHE_L3_READ_L3BANK8_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK9",
                .symbol_name = "ICACHE_L3_READ_L3BANK9",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext33__icache_l3_read_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext33_ICACHE_L3_READ_L3BANK9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext34_ICACHE_L3_READ_L3BANK16_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext34_ICACHE_L3_READ_L3BANK17_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext34_ICACHE_L3_READ_L3BANK18_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext34_ICACHE_L3_READ_L3BANK19_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext34_ICACHE_L3_READ_L3BANK20_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext34_ICACHE_L3_READ_L3BANK21_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext34_ICACHE_L3_READ_L3BANK22_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext34_ICACHE_L3_READ_L3BANK23_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext34_ICACHE_L3_READ_L3BANK24_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext34_ICACHE_L3_READ_L3BANK25_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext34_ICACHE_L3_READ_L3BANK26_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext34_ICACHE_L3_READ_L3BANK27_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext34_ICACHE_L3_READ_L3BANK28_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext34_ICACHE_L3_READ_L3BANK29_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext34_ICACHE_L3_READ_L3BANK30_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext34_ICACHE_L3_READ_L3BANK31_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext34_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext34";
    metric_set->symbol_name = "Ext34";
    metric_set->hw_config_guid = "50fbda4a-d852-437a-9178-432d1373111a";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext34_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext34__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext34__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext34__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext34__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE L3 READ L3BANK16",
                .symbol_name = "ICACHE_L3_READ_L3BANK16",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext34__icache_l3_read_l3_bank16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext34_ICACHE_L3_READ_L3BANK16_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK17",
                .symbol_name = "ICACHE_L3_READ_L3BANK17",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext34__icache_l3_read_l3_bank17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext34_ICACHE_L3_READ_L3BANK17_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK18",
                .symbol_name = "ICACHE_L3_READ_L3BANK18",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext34__icache_l3_read_l3_bank18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext34_ICACHE_L3_READ_L3BANK18_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK19",
                .symbol_name = "ICACHE_L3_READ_L3BANK19",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext34__icache_l3_read_l3_bank19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext34_ICACHE_L3_READ_L3BANK19_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK20",
                .symbol_name = "ICACHE_L3_READ_L3BANK20",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext34__icache_l3_read_l3_bank20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext34_ICACHE_L3_READ_L3BANK20_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK21",
                .symbol_name = "ICACHE_L3_READ_L3BANK21",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext34__icache_l3_read_l3_bank21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext34_ICACHE_L3_READ_L3BANK21_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK22",
                .symbol_name = "ICACHE_L3_READ_L3BANK22",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext34__icache_l3_read_l3_bank22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext34_ICACHE_L3_READ_L3BANK22_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK23",
                .symbol_name = "ICACHE_L3_READ_L3BANK23",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext34__icache_l3_read_l3_bank23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext34_ICACHE_L3_READ_L3BANK23_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK24",
                .symbol_name = "ICACHE_L3_READ_L3BANK24",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext34__icache_l3_read_l3_bank24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext34_ICACHE_L3_READ_L3BANK24_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK25",
                .symbol_name = "ICACHE_L3_READ_L3BANK25",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext34__icache_l3_read_l3_bank25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext34_ICACHE_L3_READ_L3BANK25_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK26",
                .symbol_name = "ICACHE_L3_READ_L3BANK26",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext34__icache_l3_read_l3_bank26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext34_ICACHE_L3_READ_L3BANK26_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK27",
                .symbol_name = "ICACHE_L3_READ_L3BANK27",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext34__icache_l3_read_l3_bank27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext34_ICACHE_L3_READ_L3BANK27_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK28",
                .symbol_name = "ICACHE_L3_READ_L3BANK28",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext34__icache_l3_read_l3_bank28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext34_ICACHE_L3_READ_L3BANK28_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK29",
                .symbol_name = "ICACHE_L3_READ_L3BANK29",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext34__icache_l3_read_l3_bank29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext34_ICACHE_L3_READ_L3BANK29_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK30",
                .symbol_name = "ICACHE_L3_READ_L3BANK30",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext34__icache_l3_read_l3_bank30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext34_ICACHE_L3_READ_L3BANK30_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK31",
                .symbol_name = "ICACHE_L3_READ_L3BANK31",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext34__icache_l3_read_l3_bank31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext34_ICACHE_L3_READ_L3BANK31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext35_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext35";
    metric_set->symbol_name = "Ext35";
    metric_set->hw_config_guid = "8357ba54-bded-48d6-bcb4-0f14a2da9b7b";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext35_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext35__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext35__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext35__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext35__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK0",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK0",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext35__l3_atomic_access_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK0_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK1",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK1",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext35__l3_atomic_access_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK1_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK10",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK10",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext35__l3_atomic_access_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK10_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK11",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK11",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext35__l3_atomic_access_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK11_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK12",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK12",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext35__l3_atomic_access_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK12_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK13",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK13",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext35__l3_atomic_access_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK13_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK14",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK14",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext35__l3_atomic_access_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK14_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK15",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK15",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext35__l3_atomic_access_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK15_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK2",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK2",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext35__l3_atomic_access_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK2_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK3",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK3",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext35__l3_atomic_access_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK3_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK4",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK4",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext35__l3_atomic_access_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK4_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK5",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK5",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext35__l3_atomic_access_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK5_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK6",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK6",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext35__l3_atomic_access_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK6_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK7",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK7",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext35__l3_atomic_access_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK7_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK8",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK8",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext35__l3_atomic_access_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK8_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK9",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK9",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext35__l3_atomic_access_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext35_L3_ATOMIC_ACCESS_L3BANK9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK16_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK17_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK18_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK19_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK20_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK21_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK22_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK23_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK24_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK25_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK26_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK27_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK28_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK29_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK30_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK31_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext36_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext36";
    metric_set->symbol_name = "Ext36";
    metric_set->hw_config_guid = "32c9e67d-11d7-45f7-ae53-40fe6349cb5c";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext36_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext36__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext36__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext36__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext36__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK16",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK16",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext36__l3_atomic_access_l3_bank16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK16_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK17",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK17",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext36__l3_atomic_access_l3_bank17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK17_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK18",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK18",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext36__l3_atomic_access_l3_bank18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK18_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK19",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK19",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext36__l3_atomic_access_l3_bank19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK19_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK20",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK20",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext36__l3_atomic_access_l3_bank20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK20_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK21",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK21",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext36__l3_atomic_access_l3_bank21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK21_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK22",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK22",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext36__l3_atomic_access_l3_bank22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK22_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK23",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK23",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext36__l3_atomic_access_l3_bank23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK23_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK24",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK24",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext36__l3_atomic_access_l3_bank24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK24_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK25",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK25",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext36__l3_atomic_access_l3_bank25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK25_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK26",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK26",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext36__l3_atomic_access_l3_bank26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK26_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK27",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK27",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext36__l3_atomic_access_l3_bank27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK27_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK28",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK28",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext36__l3_atomic_access_l3_bank28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK28_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK29",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK29",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext36__l3_atomic_access_l3_bank29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK29_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK30",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK30",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext36__l3_atomic_access_l3_bank30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK30_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK31",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK31",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext36__l3_atomic_access_l3_bank31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext36_L3_ATOMIC_ACCESS_L3BANK31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext37_SAMPLER_L3_READ_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext37_SAMPLER_L3_READ_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext37_SAMPLER_L3_READ_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext37_SAMPLER_L3_READ_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext37_SAMPLER_L3_READ_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext37_SAMPLER_L3_READ_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext37_SAMPLER_L3_READ_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext37_SAMPLER_L3_READ_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext37_SAMPLER_L3_READ_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext37_SAMPLER_L3_READ_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext37_SAMPLER_L3_READ_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext37_SAMPLER_L3_READ_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext37_SAMPLER_L3_READ_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext37_SAMPLER_L3_READ_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext37_SAMPLER_L3_READ_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext37_SAMPLER_L3_READ_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext37_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext37";
    metric_set->symbol_name = "Ext37";
    metric_set->hw_config_guid = "53553df5-1d80-4d9a-ad30-d72ef4503603";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext37_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext37__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext37__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext37__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext37__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER L3 READ L3BANK0",
                .symbol_name = "SAMPLER_L3_READ_L3BANK0",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext37__sampler_l3_read_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext37_SAMPLER_L3_READ_L3BANK0_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK1",
                .symbol_name = "SAMPLER_L3_READ_L3BANK1",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext37__sampler_l3_read_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext37_SAMPLER_L3_READ_L3BANK1_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK10",
                .symbol_name = "SAMPLER_L3_READ_L3BANK10",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext37__sampler_l3_read_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext37_SAMPLER_L3_READ_L3BANK10_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK11",
                .symbol_name = "SAMPLER_L3_READ_L3BANK11",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext37__sampler_l3_read_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext37_SAMPLER_L3_READ_L3BANK11_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK12",
                .symbol_name = "SAMPLER_L3_READ_L3BANK12",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext37__sampler_l3_read_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext37_SAMPLER_L3_READ_L3BANK12_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK13",
                .symbol_name = "SAMPLER_L3_READ_L3BANK13",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext37__sampler_l3_read_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext37_SAMPLER_L3_READ_L3BANK13_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK14",
                .symbol_name = "SAMPLER_L3_READ_L3BANK14",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext37__sampler_l3_read_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext37_SAMPLER_L3_READ_L3BANK14_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK15",
                .symbol_name = "SAMPLER_L3_READ_L3BANK15",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext37__sampler_l3_read_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext37_SAMPLER_L3_READ_L3BANK15_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK2",
                .symbol_name = "SAMPLER_L3_READ_L3BANK2",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext37__sampler_l3_read_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext37_SAMPLER_L3_READ_L3BANK2_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK3",
                .symbol_name = "SAMPLER_L3_READ_L3BANK3",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext37__sampler_l3_read_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext37_SAMPLER_L3_READ_L3BANK3_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK4",
                .symbol_name = "SAMPLER_L3_READ_L3BANK4",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext37__sampler_l3_read_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext37_SAMPLER_L3_READ_L3BANK4_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK5",
                .symbol_name = "SAMPLER_L3_READ_L3BANK5",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext37__sampler_l3_read_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext37_SAMPLER_L3_READ_L3BANK5_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK6",
                .symbol_name = "SAMPLER_L3_READ_L3BANK6",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext37__sampler_l3_read_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext37_SAMPLER_L3_READ_L3BANK6_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK7",
                .symbol_name = "SAMPLER_L3_READ_L3BANK7",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext37__sampler_l3_read_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext37_SAMPLER_L3_READ_L3BANK7_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK8",
                .symbol_name = "SAMPLER_L3_READ_L3BANK8",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext37__sampler_l3_read_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext37_SAMPLER_L3_READ_L3BANK8_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK9",
                .symbol_name = "SAMPLER_L3_READ_L3BANK9",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext37__sampler_l3_read_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext37_SAMPLER_L3_READ_L3BANK9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext38_SAMPLER_L3_READ_L3BANK16_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext38_SAMPLER_L3_READ_L3BANK17_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext38_SAMPLER_L3_READ_L3BANK18_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext38_SAMPLER_L3_READ_L3BANK19_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext38_SAMPLER_L3_READ_L3BANK20_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext38_SAMPLER_L3_READ_L3BANK21_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext38_SAMPLER_L3_READ_L3BANK22_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext38_SAMPLER_L3_READ_L3BANK23_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext38_SAMPLER_L3_READ_L3BANK24_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext38_SAMPLER_L3_READ_L3BANK25_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext38_SAMPLER_L3_READ_L3BANK26_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext38_SAMPLER_L3_READ_L3BANK27_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext38_SAMPLER_L3_READ_L3BANK28_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext38_SAMPLER_L3_READ_L3BANK29_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext38_SAMPLER_L3_READ_L3BANK30_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext38_SAMPLER_L3_READ_L3BANK31_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext38_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext38";
    metric_set->symbol_name = "Ext38";
    metric_set->hw_config_guid = "5e66948b-68ab-4208-93f4-44c4fdd1378e";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext38_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext38__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext38__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext38__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext38__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER L3 READ L3BANK16",
                .symbol_name = "SAMPLER_L3_READ_L3BANK16",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext38__sampler_l3_read_l3_bank16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext38_SAMPLER_L3_READ_L3BANK16_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK17",
                .symbol_name = "SAMPLER_L3_READ_L3BANK17",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext38__sampler_l3_read_l3_bank17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext38_SAMPLER_L3_READ_L3BANK17_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK18",
                .symbol_name = "SAMPLER_L3_READ_L3BANK18",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext38__sampler_l3_read_l3_bank18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext38_SAMPLER_L3_READ_L3BANK18_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK19",
                .symbol_name = "SAMPLER_L3_READ_L3BANK19",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext38__sampler_l3_read_l3_bank19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext38_SAMPLER_L3_READ_L3BANK19_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK20",
                .symbol_name = "SAMPLER_L3_READ_L3BANK20",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext38__sampler_l3_read_l3_bank20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext38_SAMPLER_L3_READ_L3BANK20_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK21",
                .symbol_name = "SAMPLER_L3_READ_L3BANK21",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext38__sampler_l3_read_l3_bank21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext38_SAMPLER_L3_READ_L3BANK21_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK22",
                .symbol_name = "SAMPLER_L3_READ_L3BANK22",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext38__sampler_l3_read_l3_bank22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext38_SAMPLER_L3_READ_L3BANK22_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK23",
                .symbol_name = "SAMPLER_L3_READ_L3BANK23",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext38__sampler_l3_read_l3_bank23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext38_SAMPLER_L3_READ_L3BANK23_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK24",
                .symbol_name = "SAMPLER_L3_READ_L3BANK24",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext38__sampler_l3_read_l3_bank24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext38_SAMPLER_L3_READ_L3BANK24_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK25",
                .symbol_name = "SAMPLER_L3_READ_L3BANK25",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext38__sampler_l3_read_l3_bank25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext38_SAMPLER_L3_READ_L3BANK25_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK26",
                .symbol_name = "SAMPLER_L3_READ_L3BANK26",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext38__sampler_l3_read_l3_bank26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext38_SAMPLER_L3_READ_L3BANK26_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK27",
                .symbol_name = "SAMPLER_L3_READ_L3BANK27",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext38__sampler_l3_read_l3_bank27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext38_SAMPLER_L3_READ_L3BANK27_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK28",
                .symbol_name = "SAMPLER_L3_READ_L3BANK28",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext38__sampler_l3_read_l3_bank28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext38_SAMPLER_L3_READ_L3BANK28_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK29",
                .symbol_name = "SAMPLER_L3_READ_L3BANK29",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext38__sampler_l3_read_l3_bank29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext38_SAMPLER_L3_READ_L3BANK29_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK30",
                .symbol_name = "SAMPLER_L3_READ_L3BANK30",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext38__sampler_l3_read_l3_bank30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext38_SAMPLER_L3_READ_L3BANK30_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK31",
                .symbol_name = "SAMPLER_L3_READ_L3BANK31",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext38__sampler_l3_read_l3_bank31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext38_SAMPLER_L3_READ_L3BANK31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext39_COLOR_L3_HIT_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext39_COLOR_L3_HIT_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext39_COLOR_L3_HIT_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext39_COLOR_L3_HIT_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext39_COLOR_L3_HIT_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext39_COLOR_L3_HIT_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext39_COLOR_L3_HIT_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext39_COLOR_L3_HIT_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext39_COLOR_L3_HIT_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext39_COLOR_L3_HIT_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext39_COLOR_L3_HIT_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext39_COLOR_L3_HIT_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext39_COLOR_L3_HIT_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext39_COLOR_L3_HIT_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext39_COLOR_L3_HIT_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext39_COLOR_L3_HIT_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext39_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext39";
    metric_set->symbol_name = "Ext39";
    metric_set->hw_config_guid = "0e04ae60-2cb4-47ea-9b5b-111c25dd9929";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext39_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext39__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext39__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "COLOR L3 HIT L3BANK0",
                .symbol_name = "COLOR_L3_HIT_L3BANK0",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext39__color_l3_hit_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext39_COLOR_L3_HIT_L3BANK0_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK1",
                .symbol_name = "COLOR_L3_HIT_L3BANK1",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext39__color_l3_hit_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext39_COLOR_L3_HIT_L3BANK1_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK10",
                .symbol_name = "COLOR_L3_HIT_L3BANK10",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext39__color_l3_hit_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext39_COLOR_L3_HIT_L3BANK10_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK11",
                .symbol_name = "COLOR_L3_HIT_L3BANK11",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext39__color_l3_hit_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext39_COLOR_L3_HIT_L3BANK11_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK12",
                .symbol_name = "COLOR_L3_HIT_L3BANK12",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext39__color_l3_hit_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext39_COLOR_L3_HIT_L3BANK12_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK13",
                .symbol_name = "COLOR_L3_HIT_L3BANK13",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext39__color_l3_hit_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext39_COLOR_L3_HIT_L3BANK13_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK14",
                .symbol_name = "COLOR_L3_HIT_L3BANK14",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext39__color_l3_hit_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext39_COLOR_L3_HIT_L3BANK14_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK15",
                .symbol_name = "COLOR_L3_HIT_L3BANK15",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext39__color_l3_hit_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext39_COLOR_L3_HIT_L3BANK15_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK2",
                .symbol_name = "COLOR_L3_HIT_L3BANK2",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext39__color_l3_hit_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext39_COLOR_L3_HIT_L3BANK2_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK3",
                .symbol_name = "COLOR_L3_HIT_L3BANK3",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext39__color_l3_hit_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext39_COLOR_L3_HIT_L3BANK3_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK4",
                .symbol_name = "COLOR_L3_HIT_L3BANK4",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext39__color_l3_hit_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext39_COLOR_L3_HIT_L3BANK4_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK5",
                .symbol_name = "COLOR_L3_HIT_L3BANK5",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext39__color_l3_hit_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext39_COLOR_L3_HIT_L3BANK5_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK6",
                .symbol_name = "COLOR_L3_HIT_L3BANK6",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext39__color_l3_hit_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext39_COLOR_L3_HIT_L3BANK6_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK7",
                .symbol_name = "COLOR_L3_HIT_L3BANK7",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext39__color_l3_hit_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext39_COLOR_L3_HIT_L3BANK7_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK8",
                .symbol_name = "COLOR_L3_HIT_L3BANK8",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext39__color_l3_hit_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext39_COLOR_L3_HIT_L3BANK8_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK9",
                .symbol_name = "COLOR_L3_HIT_L3BANK9",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext39__color_l3_hit_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext39_COLOR_L3_HIT_L3BANK9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext39__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext39__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext40_COLOR_L3_HIT_L3BANK16_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext40_COLOR_L3_HIT_L3BANK17_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext40_COLOR_L3_HIT_L3BANK18_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext40_COLOR_L3_HIT_L3BANK19_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext40_COLOR_L3_HIT_L3BANK20_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext40_COLOR_L3_HIT_L3BANK21_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext40_COLOR_L3_HIT_L3BANK22_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext40_COLOR_L3_HIT_L3BANK23_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext40_COLOR_L3_HIT_L3BANK24_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext40_COLOR_L3_HIT_L3BANK25_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext40_COLOR_L3_HIT_L3BANK26_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext40_COLOR_L3_HIT_L3BANK27_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext40_COLOR_L3_HIT_L3BANK28_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext40_COLOR_L3_HIT_L3BANK29_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext40_COLOR_L3_HIT_L3BANK30_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext40_COLOR_L3_HIT_L3BANK31_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext40_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext40";
    metric_set->symbol_name = "Ext40";
    metric_set->hw_config_guid = "46c8c61b-b6e3-4ea7-95d9-3f9861d17133";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext40_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext40__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext40__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "COLOR L3 HIT L3BANK16",
                .symbol_name = "COLOR_L3_HIT_L3BANK16",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext40__color_l3_hit_l3_bank16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext40_COLOR_L3_HIT_L3BANK16_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK17",
                .symbol_name = "COLOR_L3_HIT_L3BANK17",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext40__color_l3_hit_l3_bank17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext40_COLOR_L3_HIT_L3BANK17_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK18",
                .symbol_name = "COLOR_L3_HIT_L3BANK18",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext40__color_l3_hit_l3_bank18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext40_COLOR_L3_HIT_L3BANK18_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK19",
                .symbol_name = "COLOR_L3_HIT_L3BANK19",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext40__color_l3_hit_l3_bank19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext40_COLOR_L3_HIT_L3BANK19_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK20",
                .symbol_name = "COLOR_L3_HIT_L3BANK20",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext40__color_l3_hit_l3_bank20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext40_COLOR_L3_HIT_L3BANK20_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK21",
                .symbol_name = "COLOR_L3_HIT_L3BANK21",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext40__color_l3_hit_l3_bank21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext40_COLOR_L3_HIT_L3BANK21_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK22",
                .symbol_name = "COLOR_L3_HIT_L3BANK22",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext40__color_l3_hit_l3_bank22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext40_COLOR_L3_HIT_L3BANK22_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK23",
                .symbol_name = "COLOR_L3_HIT_L3BANK23",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext40__color_l3_hit_l3_bank23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext40_COLOR_L3_HIT_L3BANK23_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK24",
                .symbol_name = "COLOR_L3_HIT_L3BANK24",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext40__color_l3_hit_l3_bank24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext40_COLOR_L3_HIT_L3BANK24_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK25",
                .symbol_name = "COLOR_L3_HIT_L3BANK25",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext40__color_l3_hit_l3_bank25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext40_COLOR_L3_HIT_L3BANK25_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK26",
                .symbol_name = "COLOR_L3_HIT_L3BANK26",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext40__color_l3_hit_l3_bank26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext40_COLOR_L3_HIT_L3BANK26_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK27",
                .symbol_name = "COLOR_L3_HIT_L3BANK27",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext40__color_l3_hit_l3_bank27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext40_COLOR_L3_HIT_L3BANK27_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK28",
                .symbol_name = "COLOR_L3_HIT_L3BANK28",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext40__color_l3_hit_l3_bank28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext40_COLOR_L3_HIT_L3BANK28_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK29",
                .symbol_name = "COLOR_L3_HIT_L3BANK29",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext40__color_l3_hit_l3_bank29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext40_COLOR_L3_HIT_L3BANK29_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK30",
                .symbol_name = "COLOR_L3_HIT_L3BANK30",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext40__color_l3_hit_l3_bank30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext40_COLOR_L3_HIT_L3BANK30_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK31",
                .symbol_name = "COLOR_L3_HIT_L3BANK31",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext40__color_l3_hit_l3_bank31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext40_COLOR_L3_HIT_L3BANK31_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext40__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext40__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext41_DATAPORT_L3_HIT_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext41_DATAPORT_L3_HIT_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext41_DATAPORT_L3_HIT_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext41_DATAPORT_L3_HIT_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext41_DATAPORT_L3_HIT_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext41_DATAPORT_L3_HIT_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext41_DATAPORT_L3_HIT_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext41_DATAPORT_L3_HIT_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext41_DATAPORT_L3_HIT_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext41_DATAPORT_L3_HIT_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext41_DATAPORT_L3_HIT_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext41_DATAPORT_L3_HIT_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext41_DATAPORT_L3_HIT_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext41_DATAPORT_L3_HIT_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext41_DATAPORT_L3_HIT_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext41_DATAPORT_L3_HIT_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext41_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext41";
    metric_set->symbol_name = "Ext41";
    metric_set->hw_config_guid = "3c7fdece-0f76-411d-a7e3-583c22965830";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext41_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext41__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext41__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT L3 HIT L3BANK0",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK0",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext41__dataport_l3_hit_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext41_DATAPORT_L3_HIT_L3BANK0_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK1",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK1",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext41__dataport_l3_hit_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext41_DATAPORT_L3_HIT_L3BANK1_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK10",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK10",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext41__dataport_l3_hit_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext41_DATAPORT_L3_HIT_L3BANK10_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK11",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK11",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext41__dataport_l3_hit_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext41_DATAPORT_L3_HIT_L3BANK11_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK12",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK12",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext41__dataport_l3_hit_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext41_DATAPORT_L3_HIT_L3BANK12_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK13",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK13",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext41__dataport_l3_hit_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext41_DATAPORT_L3_HIT_L3BANK13_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK14",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK14",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext41__dataport_l3_hit_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext41_DATAPORT_L3_HIT_L3BANK14_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK15",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK15",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext41__dataport_l3_hit_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext41_DATAPORT_L3_HIT_L3BANK15_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK2",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK2",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext41__dataport_l3_hit_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext41_DATAPORT_L3_HIT_L3BANK2_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK3",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK3",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext41__dataport_l3_hit_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext41_DATAPORT_L3_HIT_L3BANK3_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK4",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK4",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext41__dataport_l3_hit_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext41_DATAPORT_L3_HIT_L3BANK4_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK5",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK5",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext41__dataport_l3_hit_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext41_DATAPORT_L3_HIT_L3BANK5_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK6",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK6",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext41__dataport_l3_hit_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext41_DATAPORT_L3_HIT_L3BANK6_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK7",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK7",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext41__dataport_l3_hit_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext41_DATAPORT_L3_HIT_L3BANK7_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK8",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK8",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext41__dataport_l3_hit_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext41_DATAPORT_L3_HIT_L3BANK8_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK9",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK9",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext41__dataport_l3_hit_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext41_DATAPORT_L3_HIT_L3BANK9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext41__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext41__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext42_DATAPORT_L3_HIT_L3BANK16_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext42_DATAPORT_L3_HIT_L3BANK17_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext42_DATAPORT_L3_HIT_L3BANK18_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext42_DATAPORT_L3_HIT_L3BANK19_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext42_DATAPORT_L3_HIT_L3BANK20_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext42_DATAPORT_L3_HIT_L3BANK21_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext42_DATAPORT_L3_HIT_L3BANK22_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext42_DATAPORT_L3_HIT_L3BANK23_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext42_DATAPORT_L3_HIT_L3BANK24_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext42_DATAPORT_L3_HIT_L3BANK25_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext42_DATAPORT_L3_HIT_L3BANK26_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext42_DATAPORT_L3_HIT_L3BANK27_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext42_DATAPORT_L3_HIT_L3BANK28_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext42_DATAPORT_L3_HIT_L3BANK29_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext42_DATAPORT_L3_HIT_L3BANK30_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext42_DATAPORT_L3_HIT_L3BANK31_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext42_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext42";
    metric_set->symbol_name = "Ext42";
    metric_set->hw_config_guid = "2324903a-33fe-4512-870b-2f8316f85ba1";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext42_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext42__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext42__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT L3 HIT L3BANK16",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK16",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext42__dataport_l3_hit_l3_bank16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext42_DATAPORT_L3_HIT_L3BANK16_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK17",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK17",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext42__dataport_l3_hit_l3_bank17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext42_DATAPORT_L3_HIT_L3BANK17_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK18",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK18",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext42__dataport_l3_hit_l3_bank18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext42_DATAPORT_L3_HIT_L3BANK18_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK19",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK19",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext42__dataport_l3_hit_l3_bank19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext42_DATAPORT_L3_HIT_L3BANK19_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK20",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK20",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext42__dataport_l3_hit_l3_bank20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext42_DATAPORT_L3_HIT_L3BANK20_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK21",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK21",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext42__dataport_l3_hit_l3_bank21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext42_DATAPORT_L3_HIT_L3BANK21_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK22",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK22",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext42__dataport_l3_hit_l3_bank22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext42_DATAPORT_L3_HIT_L3BANK22_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK23",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK23",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext42__dataport_l3_hit_l3_bank23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext42_DATAPORT_L3_HIT_L3BANK23_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK24",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK24",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext42__dataport_l3_hit_l3_bank24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext42_DATAPORT_L3_HIT_L3BANK24_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK25",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK25",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext42__dataport_l3_hit_l3_bank25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext42_DATAPORT_L3_HIT_L3BANK25_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK26",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK26",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext42__dataport_l3_hit_l3_bank26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext42_DATAPORT_L3_HIT_L3BANK26_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK27",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK27",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext42__dataport_l3_hit_l3_bank27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext42_DATAPORT_L3_HIT_L3BANK27_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK28",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK28",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext42__dataport_l3_hit_l3_bank28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext42_DATAPORT_L3_HIT_L3BANK28_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK29",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK29",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext42__dataport_l3_hit_l3_bank29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext42_DATAPORT_L3_HIT_L3BANK29_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK30",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK30",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext42__dataport_l3_hit_l3_bank30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext42_DATAPORT_L3_HIT_L3BANK30_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK31",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK31",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext42__dataport_l3_hit_l3_bank31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext42_DATAPORT_L3_HIT_L3BANK31_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext42__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext42__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext43_ICACHE_L3_HIT_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext43_ICACHE_L3_HIT_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext43_ICACHE_L3_HIT_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext43_ICACHE_L3_HIT_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext43_ICACHE_L3_HIT_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext43_ICACHE_L3_HIT_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext43_ICACHE_L3_HIT_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext43_ICACHE_L3_HIT_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext43_ICACHE_L3_HIT_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext43_ICACHE_L3_HIT_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext43_ICACHE_L3_HIT_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext43_ICACHE_L3_HIT_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext43_ICACHE_L3_HIT_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext43_ICACHE_L3_HIT_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext43_ICACHE_L3_HIT_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext43_ICACHE_L3_HIT_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext43_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext43";
    metric_set->symbol_name = "Ext43";
    metric_set->hw_config_guid = "cc074ca3-3e9f-4924-805e-27d69dbf2bbe";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext43_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext43__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext43__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext43__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext43__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE L3 HIT L3BANK0",
                .symbol_name = "ICACHE_L3_HIT_L3BANK0",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext43__icache_l3_hit_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext43_ICACHE_L3_HIT_L3BANK0_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK1",
                .symbol_name = "ICACHE_L3_HIT_L3BANK1",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext43__icache_l3_hit_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext43_ICACHE_L3_HIT_L3BANK1_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK10",
                .symbol_name = "ICACHE_L3_HIT_L3BANK10",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext43__icache_l3_hit_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext43_ICACHE_L3_HIT_L3BANK10_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK11",
                .symbol_name = "ICACHE_L3_HIT_L3BANK11",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext43__icache_l3_hit_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext43_ICACHE_L3_HIT_L3BANK11_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK12",
                .symbol_name = "ICACHE_L3_HIT_L3BANK12",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext43__icache_l3_hit_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext43_ICACHE_L3_HIT_L3BANK12_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK13",
                .symbol_name = "ICACHE_L3_HIT_L3BANK13",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext43__icache_l3_hit_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext43_ICACHE_L3_HIT_L3BANK13_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK14",
                .symbol_name = "ICACHE_L3_HIT_L3BANK14",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext43__icache_l3_hit_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext43_ICACHE_L3_HIT_L3BANK14_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK15",
                .symbol_name = "ICACHE_L3_HIT_L3BANK15",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext43__icache_l3_hit_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext43_ICACHE_L3_HIT_L3BANK15_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK2",
                .symbol_name = "ICACHE_L3_HIT_L3BANK2",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext43__icache_l3_hit_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext43_ICACHE_L3_HIT_L3BANK2_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK3",
                .symbol_name = "ICACHE_L3_HIT_L3BANK3",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext43__icache_l3_hit_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext43_ICACHE_L3_HIT_L3BANK3_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK4",
                .symbol_name = "ICACHE_L3_HIT_L3BANK4",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext43__icache_l3_hit_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext43_ICACHE_L3_HIT_L3BANK4_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK5",
                .symbol_name = "ICACHE_L3_HIT_L3BANK5",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext43__icache_l3_hit_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext43_ICACHE_L3_HIT_L3BANK5_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK6",
                .symbol_name = "ICACHE_L3_HIT_L3BANK6",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext43__icache_l3_hit_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext43_ICACHE_L3_HIT_L3BANK6_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK7",
                .symbol_name = "ICACHE_L3_HIT_L3BANK7",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext43__icache_l3_hit_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext43_ICACHE_L3_HIT_L3BANK7_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK8",
                .symbol_name = "ICACHE_L3_HIT_L3BANK8",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext43__icache_l3_hit_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext43_ICACHE_L3_HIT_L3BANK8_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK9",
                .symbol_name = "ICACHE_L3_HIT_L3BANK9",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext43__icache_l3_hit_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext43_ICACHE_L3_HIT_L3BANK9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext44_ICACHE_L3_HIT_L3BANK16_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext44_ICACHE_L3_HIT_L3BANK17_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext44_ICACHE_L3_HIT_L3BANK18_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext44_ICACHE_L3_HIT_L3BANK19_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext44_ICACHE_L3_HIT_L3BANK20_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext44_ICACHE_L3_HIT_L3BANK21_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext44_ICACHE_L3_HIT_L3BANK22_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext44_ICACHE_L3_HIT_L3BANK23_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext44_ICACHE_L3_HIT_L3BANK24_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext44_ICACHE_L3_HIT_L3BANK25_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext44_ICACHE_L3_HIT_L3BANK26_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext44_ICACHE_L3_HIT_L3BANK27_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext44_ICACHE_L3_HIT_L3BANK28_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext44_ICACHE_L3_HIT_L3BANK29_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext44_ICACHE_L3_HIT_L3BANK30_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext44_ICACHE_L3_HIT_L3BANK31_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext44_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext44";
    metric_set->symbol_name = "Ext44";
    metric_set->hw_config_guid = "3fd7e51e-732e-41c7-8f9d-b81500a438cf";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext44_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext44__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext44__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext44__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext44__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE L3 HIT L3BANK16",
                .symbol_name = "ICACHE_L3_HIT_L3BANK16",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext44__icache_l3_hit_l3_bank16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext44_ICACHE_L3_HIT_L3BANK16_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK17",
                .symbol_name = "ICACHE_L3_HIT_L3BANK17",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext44__icache_l3_hit_l3_bank17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext44_ICACHE_L3_HIT_L3BANK17_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK18",
                .symbol_name = "ICACHE_L3_HIT_L3BANK18",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext44__icache_l3_hit_l3_bank18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext44_ICACHE_L3_HIT_L3BANK18_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK19",
                .symbol_name = "ICACHE_L3_HIT_L3BANK19",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext44__icache_l3_hit_l3_bank19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext44_ICACHE_L3_HIT_L3BANK19_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK20",
                .symbol_name = "ICACHE_L3_HIT_L3BANK20",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext44__icache_l3_hit_l3_bank20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext44_ICACHE_L3_HIT_L3BANK20_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK21",
                .symbol_name = "ICACHE_L3_HIT_L3BANK21",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext44__icache_l3_hit_l3_bank21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext44_ICACHE_L3_HIT_L3BANK21_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK22",
                .symbol_name = "ICACHE_L3_HIT_L3BANK22",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext44__icache_l3_hit_l3_bank22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext44_ICACHE_L3_HIT_L3BANK22_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK23",
                .symbol_name = "ICACHE_L3_HIT_L3BANK23",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext44__icache_l3_hit_l3_bank23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext44_ICACHE_L3_HIT_L3BANK23_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK24",
                .symbol_name = "ICACHE_L3_HIT_L3BANK24",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext44__icache_l3_hit_l3_bank24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext44_ICACHE_L3_HIT_L3BANK24_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK25",
                .symbol_name = "ICACHE_L3_HIT_L3BANK25",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext44__icache_l3_hit_l3_bank25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext44_ICACHE_L3_HIT_L3BANK25_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK26",
                .symbol_name = "ICACHE_L3_HIT_L3BANK26",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext44__icache_l3_hit_l3_bank26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext44_ICACHE_L3_HIT_L3BANK26_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK27",
                .symbol_name = "ICACHE_L3_HIT_L3BANK27",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext44__icache_l3_hit_l3_bank27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext44_ICACHE_L3_HIT_L3BANK27_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK28",
                .symbol_name = "ICACHE_L3_HIT_L3BANK28",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext44__icache_l3_hit_l3_bank28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext44_ICACHE_L3_HIT_L3BANK28_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK29",
                .symbol_name = "ICACHE_L3_HIT_L3BANK29",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext44__icache_l3_hit_l3_bank29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext44_ICACHE_L3_HIT_L3BANK29_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK30",
                .symbol_name = "ICACHE_L3_HIT_L3BANK30",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext44__icache_l3_hit_l3_bank30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext44_ICACHE_L3_HIT_L3BANK30_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK31",
                .symbol_name = "ICACHE_L3_HIT_L3BANK31",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext44__icache_l3_hit_l3_bank31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext44_ICACHE_L3_HIT_L3BANK31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext45_SAMPLER_L3_HIT_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext45_SAMPLER_L3_HIT_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext45_SAMPLER_L3_HIT_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext45_SAMPLER_L3_HIT_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext45_SAMPLER_L3_HIT_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext45_SAMPLER_L3_HIT_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext45_SAMPLER_L3_HIT_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext45_SAMPLER_L3_HIT_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext45_SAMPLER_L3_HIT_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext45_SAMPLER_L3_HIT_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext45_SAMPLER_L3_HIT_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext45_SAMPLER_L3_HIT_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext45_SAMPLER_L3_HIT_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext45_SAMPLER_L3_HIT_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext45_SAMPLER_L3_HIT_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext45_SAMPLER_L3_HIT_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext45_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext45";
    metric_set->symbol_name = "Ext45";
    metric_set->hw_config_guid = "d71b7626-b7fb-49ce-b512-22030d666820";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext45_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext45__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext45__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext45__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext45__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER L3 HIT L3BANK0",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK0",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext45__sampler_l3_hit_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext45_SAMPLER_L3_HIT_L3BANK0_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK1",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK1",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext45__sampler_l3_hit_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext45_SAMPLER_L3_HIT_L3BANK1_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK10",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK10",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext45__sampler_l3_hit_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext45_SAMPLER_L3_HIT_L3BANK10_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK11",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK11",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext45__sampler_l3_hit_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext45_SAMPLER_L3_HIT_L3BANK11_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK12",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK12",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext45__sampler_l3_hit_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext45_SAMPLER_L3_HIT_L3BANK12_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK13",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK13",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext45__sampler_l3_hit_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext45_SAMPLER_L3_HIT_L3BANK13_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK14",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK14",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext45__sampler_l3_hit_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext45_SAMPLER_L3_HIT_L3BANK14_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK15",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK15",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext45__sampler_l3_hit_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext45_SAMPLER_L3_HIT_L3BANK15_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK2",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK2",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext45__sampler_l3_hit_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext45_SAMPLER_L3_HIT_L3BANK2_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK3",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK3",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext45__sampler_l3_hit_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext45_SAMPLER_L3_HIT_L3BANK3_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK4",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK4",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext45__sampler_l3_hit_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext45_SAMPLER_L3_HIT_L3BANK4_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK5",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK5",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext45__sampler_l3_hit_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext45_SAMPLER_L3_HIT_L3BANK5_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK6",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK6",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext45__sampler_l3_hit_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext45_SAMPLER_L3_HIT_L3BANK6_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK7",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK7",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext45__sampler_l3_hit_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext45_SAMPLER_L3_HIT_L3BANK7_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK8",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK8",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext45__sampler_l3_hit_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext45_SAMPLER_L3_HIT_L3BANK8_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK9",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK9",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext45__sampler_l3_hit_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext45_SAMPLER_L3_HIT_L3BANK9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext46_SAMPLER_L3_HIT_L3BANK16_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext46_SAMPLER_L3_HIT_L3BANK17_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext46_SAMPLER_L3_HIT_L3BANK18_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext46_SAMPLER_L3_HIT_L3BANK19_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext46_SAMPLER_L3_HIT_L3BANK20_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext46_SAMPLER_L3_HIT_L3BANK21_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext46_SAMPLER_L3_HIT_L3BANK22_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext46_SAMPLER_L3_HIT_L3BANK23_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext46_SAMPLER_L3_HIT_L3BANK24_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext46_SAMPLER_L3_HIT_L3BANK25_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext46_SAMPLER_L3_HIT_L3BANK26_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext46_SAMPLER_L3_HIT_L3BANK27_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext46_SAMPLER_L3_HIT_L3BANK28_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext46_SAMPLER_L3_HIT_L3BANK29_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext46_SAMPLER_L3_HIT_L3BANK30_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext46_SAMPLER_L3_HIT_L3BANK31_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext46_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext46";
    metric_set->symbol_name = "Ext46";
    metric_set->hw_config_guid = "e87db70a-571a-4cc6-852f-8929fe2404ca";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext46_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext46__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext46__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext46__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext46__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER L3 HIT L3BANK16",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK16",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext46__sampler_l3_hit_l3_bank16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext46_SAMPLER_L3_HIT_L3BANK16_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK17",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK17",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext46__sampler_l3_hit_l3_bank17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext46_SAMPLER_L3_HIT_L3BANK17_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK18",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK18",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext46__sampler_l3_hit_l3_bank18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext46_SAMPLER_L3_HIT_L3BANK18_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK19",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK19",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext46__sampler_l3_hit_l3_bank19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext46_SAMPLER_L3_HIT_L3BANK19_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK20",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK20",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext46__sampler_l3_hit_l3_bank20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext46_SAMPLER_L3_HIT_L3BANK20_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK21",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK21",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext46__sampler_l3_hit_l3_bank21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext46_SAMPLER_L3_HIT_L3BANK21_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK22",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK22",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext46__sampler_l3_hit_l3_bank22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext46_SAMPLER_L3_HIT_L3BANK22_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK23",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK23",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext46__sampler_l3_hit_l3_bank23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext46_SAMPLER_L3_HIT_L3BANK23_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK24",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK24",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext46__sampler_l3_hit_l3_bank24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext46_SAMPLER_L3_HIT_L3BANK24_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK25",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK25",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext46__sampler_l3_hit_l3_bank25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext46_SAMPLER_L3_HIT_L3BANK25_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK26",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK26",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext46__sampler_l3_hit_l3_bank26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext46_SAMPLER_L3_HIT_L3BANK26_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK27",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK27",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext46__sampler_l3_hit_l3_bank27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext46_SAMPLER_L3_HIT_L3BANK27_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK28",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK28",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext46__sampler_l3_hit_l3_bank28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext46_SAMPLER_L3_HIT_L3BANK28_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK29",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK29",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext46__sampler_l3_hit_l3_bank29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext46_SAMPLER_L3_HIT_L3BANK29_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK30",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK30",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext46__sampler_l3_hit_l3_bank30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext46_SAMPLER_L3_HIT_L3BANK30_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK31",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK31",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext46__sampler_l3_hit_l3_bank31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext46_SAMPLER_L3_HIT_L3BANK31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext47_Z_L3_HIT_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext47_Z_L3_HIT_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext47_Z_L3_HIT_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext47_Z_L3_HIT_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext47_Z_L3_HIT_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext47_Z_L3_HIT_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext47_Z_L3_HIT_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext47_Z_L3_HIT_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext47_Z_L3_HIT_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext47_Z_L3_HIT_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext47_Z_L3_HIT_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext47_Z_L3_HIT_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext47_Z_L3_HIT_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext47_Z_L3_HIT_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext47_Z_L3_HIT_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext47_Z_L3_HIT_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext47_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext47";
    metric_set->symbol_name = "Ext47";
    metric_set->hw_config_guid = "f31ec8fe-7987-48fc-ad8e-ebe0b25374b2";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext47_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext47__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext47__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext47__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext47__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Z L3 HIT L3BANK0",
                .symbol_name = "Z_L3_HIT_L3BANK0",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext47__z_l3_hit_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext47_Z_L3_HIT_L3BANK0_availability,
            },

            {
                .name = "Z L3 HIT L3BANK1",
                .symbol_name = "Z_L3_HIT_L3BANK1",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext47__z_l3_hit_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext47_Z_L3_HIT_L3BANK1_availability,
            },

            {
                .name = "Z L3 HIT L3BANK10",
                .symbol_name = "Z_L3_HIT_L3BANK10",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext47__z_l3_hit_l3_bank10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext47_Z_L3_HIT_L3BANK10_availability,
            },

            {
                .name = "Z L3 HIT L3BANK11",
                .symbol_name = "Z_L3_HIT_L3BANK11",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext47__z_l3_hit_l3_bank11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext47_Z_L3_HIT_L3BANK11_availability,
            },

            {
                .name = "Z L3 HIT L3BANK12",
                .symbol_name = "Z_L3_HIT_L3BANK12",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext47__z_l3_hit_l3_bank12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext47_Z_L3_HIT_L3BANK12_availability,
            },

            {
                .name = "Z L3 HIT L3BANK13",
                .symbol_name = "Z_L3_HIT_L3BANK13",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext47__z_l3_hit_l3_bank13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext47_Z_L3_HIT_L3BANK13_availability,
            },

            {
                .name = "Z L3 HIT L3BANK14",
                .symbol_name = "Z_L3_HIT_L3BANK14",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext47__z_l3_hit_l3_bank14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext47_Z_L3_HIT_L3BANK14_availability,
            },

            {
                .name = "Z L3 HIT L3BANK15",
                .symbol_name = "Z_L3_HIT_L3BANK15",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext47__z_l3_hit_l3_bank15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext47_Z_L3_HIT_L3BANK15_availability,
            },

            {
                .name = "Z L3 HIT L3BANK2",
                .symbol_name = "Z_L3_HIT_L3BANK2",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext47__z_l3_hit_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext47_Z_L3_HIT_L3BANK2_availability,
            },

            {
                .name = "Z L3 HIT L3BANK3",
                .symbol_name = "Z_L3_HIT_L3BANK3",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext47__z_l3_hit_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext47_Z_L3_HIT_L3BANK3_availability,
            },

            {
                .name = "Z L3 HIT L3BANK4",
                .symbol_name = "Z_L3_HIT_L3BANK4",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext47__z_l3_hit_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext47_Z_L3_HIT_L3BANK4_availability,
            },

            {
                .name = "Z L3 HIT L3BANK5",
                .symbol_name = "Z_L3_HIT_L3BANK5",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext47__z_l3_hit_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext47_Z_L3_HIT_L3BANK5_availability,
            },

            {
                .name = "Z L3 HIT L3BANK6",
                .symbol_name = "Z_L3_HIT_L3BANK6",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext47__z_l3_hit_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext47_Z_L3_HIT_L3BANK6_availability,
            },

            {
                .name = "Z L3 HIT L3BANK7",
                .symbol_name = "Z_L3_HIT_L3BANK7",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext47__z_l3_hit_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext47_Z_L3_HIT_L3BANK7_availability,
            },

            {
                .name = "Z L3 HIT L3BANK8",
                .symbol_name = "Z_L3_HIT_L3BANK8",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext47__z_l3_hit_l3_bank8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext47_Z_L3_HIT_L3BANK8_availability,
            },

            {
                .name = "Z L3 HIT L3BANK9",
                .symbol_name = "Z_L3_HIT_L3BANK9",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext47__z_l3_hit_l3_bank9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext47_Z_L3_HIT_L3BANK9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext48_Z_L3_HIT_L3BANK16_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext48_Z_L3_HIT_L3BANK17_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext48_Z_L3_HIT_L3BANK18_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext48_Z_L3_HIT_L3BANK19_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext48_Z_L3_HIT_L3BANK20_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext48_Z_L3_HIT_L3BANK21_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext48_Z_L3_HIT_L3BANK22_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext48_Z_L3_HIT_L3BANK23_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext48_Z_L3_HIT_L3BANK24_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext48_Z_L3_HIT_L3BANK25_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext48_Z_L3_HIT_L3BANK26_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext48_Z_L3_HIT_L3BANK27_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext48_Z_L3_HIT_L3BANK28_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext48_Z_L3_HIT_L3BANK29_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext48_Z_L3_HIT_L3BANK30_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext48_Z_L3_HIT_L3BANK31_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext48_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext48";
    metric_set->symbol_name = "Ext48";
    metric_set->hw_config_guid = "add101d4-45eb-4394-9c22-66da145c4731";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext48_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext48__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext48__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext48__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext48__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Z L3 HIT L3BANK16",
                .symbol_name = "Z_L3_HIT_L3BANK16",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext48__z_l3_hit_l3_bank16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext48_Z_L3_HIT_L3BANK16_availability,
            },

            {
                .name = "Z L3 HIT L3BANK17",
                .symbol_name = "Z_L3_HIT_L3BANK17",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext48__z_l3_hit_l3_bank17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext48_Z_L3_HIT_L3BANK17_availability,
            },

            {
                .name = "Z L3 HIT L3BANK18",
                .symbol_name = "Z_L3_HIT_L3BANK18",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext48__z_l3_hit_l3_bank18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext48_Z_L3_HIT_L3BANK18_availability,
            },

            {
                .name = "Z L3 HIT L3BANK19",
                .symbol_name = "Z_L3_HIT_L3BANK19",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext48__z_l3_hit_l3_bank19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext48_Z_L3_HIT_L3BANK19_availability,
            },

            {
                .name = "Z L3 HIT L3BANK20",
                .symbol_name = "Z_L3_HIT_L3BANK20",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext48__z_l3_hit_l3_bank20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext48_Z_L3_HIT_L3BANK20_availability,
            },

            {
                .name = "Z L3 HIT L3BANK21",
                .symbol_name = "Z_L3_HIT_L3BANK21",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext48__z_l3_hit_l3_bank21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext48_Z_L3_HIT_L3BANK21_availability,
            },

            {
                .name = "Z L3 HIT L3BANK22",
                .symbol_name = "Z_L3_HIT_L3BANK22",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext48__z_l3_hit_l3_bank22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext48_Z_L3_HIT_L3BANK22_availability,
            },

            {
                .name = "Z L3 HIT L3BANK23",
                .symbol_name = "Z_L3_HIT_L3BANK23",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext48__z_l3_hit_l3_bank23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext48_Z_L3_HIT_L3BANK23_availability,
            },

            {
                .name = "Z L3 HIT L3BANK24",
                .symbol_name = "Z_L3_HIT_L3BANK24",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext48__z_l3_hit_l3_bank24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext48_Z_L3_HIT_L3BANK24_availability,
            },

            {
                .name = "Z L3 HIT L3BANK25",
                .symbol_name = "Z_L3_HIT_L3BANK25",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext48__z_l3_hit_l3_bank25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext48_Z_L3_HIT_L3BANK25_availability,
            },

            {
                .name = "Z L3 HIT L3BANK26",
                .symbol_name = "Z_L3_HIT_L3BANK26",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext48__z_l3_hit_l3_bank26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext48_Z_L3_HIT_L3BANK26_availability,
            },

            {
                .name = "Z L3 HIT L3BANK27",
                .symbol_name = "Z_L3_HIT_L3BANK27",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext48__z_l3_hit_l3_bank27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext48_Z_L3_HIT_L3BANK27_availability,
            },

            {
                .name = "Z L3 HIT L3BANK28",
                .symbol_name = "Z_L3_HIT_L3BANK28",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext48__z_l3_hit_l3_bank28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext48_Z_L3_HIT_L3BANK28_availability,
            },

            {
                .name = "Z L3 HIT L3BANK29",
                .symbol_name = "Z_L3_HIT_L3BANK29",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext48__z_l3_hit_l3_bank29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext48_Z_L3_HIT_L3BANK29_availability,
            },

            {
                .name = "Z L3 HIT L3BANK30",
                .symbol_name = "Z_L3_HIT_L3BANK30",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext48__z_l3_hit_l3_bank30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext48_Z_L3_HIT_L3BANK30_availability,
            },

            {
                .name = "Z L3 HIT L3BANK31",
                .symbol_name = "Z_L3_HIT_L3BANK31",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext48__z_l3_hit_l3_bank31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt3_ext48_Z_L3_HIT_L3BANK31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext49_L3_SUPERQ_FULL_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext49_L3_SUPERQ_FULL_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext49_L3_SUPERQ_FULL_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext49_L3_SUPERQ_FULL_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext49_L3_SUPERQ_FULL_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext49_L3_SUPERQ_FULL_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext49_L3_SUPERQ_FULL_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext49_L3_SUPERQ_FULL_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext49_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext49";
    metric_set->symbol_name = "Ext49";
    metric_set->hw_config_guid = "da4046b1-521a-43cb-8328-c219155e59e5";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext49_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext49__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext49__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext49__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext49__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 SUPERQ FULL L3BANK0",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK0",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext49__l3_superq_full_l3_bank0__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext49_L3_SUPERQ_FULL_L3BANK0_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK1",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK1",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext49__l3_superq_full_l3_bank1__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext49_L3_SUPERQ_FULL_L3BANK1_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK2",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK2",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext49__l3_superq_full_l3_bank2__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext49_L3_SUPERQ_FULL_L3BANK2_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK3",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK3",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext49__l3_superq_full_l3_bank3__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext49_L3_SUPERQ_FULL_L3BANK3_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK4",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK4",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext49__l3_superq_full_l3_bank4__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext49_L3_SUPERQ_FULL_L3BANK4_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK5",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK5",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext49__l3_superq_full_l3_bank5__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext49_L3_SUPERQ_FULL_L3BANK5_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK6",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK6",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext49__l3_superq_full_l3_bank6__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext49_L3_SUPERQ_FULL_L3BANK6_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK7",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK7",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext49__l3_superq_full_l3_bank7__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext49_L3_SUPERQ_FULL_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext50_L3_SUPERQ_FULL_L3BANK10_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext50_L3_SUPERQ_FULL_L3BANK11_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext50_L3_SUPERQ_FULL_L3BANK12_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext50_L3_SUPERQ_FULL_L3BANK13_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext50_L3_SUPERQ_FULL_L3BANK14_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext50_L3_SUPERQ_FULL_L3BANK15_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext50_L3_SUPERQ_FULL_L3BANK8_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext50_L3_SUPERQ_FULL_L3BANK9_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext50_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext50";
    metric_set->symbol_name = "Ext50";
    metric_set->hw_config_guid = "fd655951-07ee-4a28-81d1-fbb62cea041e";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext50_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext50__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext50__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext50__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext50__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 SUPERQ FULL L3BANK10",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK10",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext50__l3_superq_full_l3_bank10__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext50_L3_SUPERQ_FULL_L3BANK10_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK11",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK11",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext50__l3_superq_full_l3_bank11__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext50_L3_SUPERQ_FULL_L3BANK11_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK12",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK12",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext50__l3_superq_full_l3_bank12__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext50_L3_SUPERQ_FULL_L3BANK12_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK13",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK13",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext50__l3_superq_full_l3_bank13__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext50_L3_SUPERQ_FULL_L3BANK13_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK14",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK14",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext50__l3_superq_full_l3_bank14__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext50_L3_SUPERQ_FULL_L3BANK14_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK15",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK15",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext50__l3_superq_full_l3_bank15__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext50_L3_SUPERQ_FULL_L3BANK15_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK8",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK8",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext50__l3_superq_full_l3_bank8__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext50_L3_SUPERQ_FULL_L3BANK8_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK9",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK9",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext50__l3_superq_full_l3_bank9__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext50_L3_SUPERQ_FULL_L3BANK9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext51_L3_SUPERQ_FULL_L3BANK16_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext51_L3_SUPERQ_FULL_L3BANK17_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext51_L3_SUPERQ_FULL_L3BANK18_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext51_L3_SUPERQ_FULL_L3BANK19_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext51_L3_SUPERQ_FULL_L3BANK20_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext51_L3_SUPERQ_FULL_L3BANK21_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext51_L3_SUPERQ_FULL_L3BANK22_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext51_L3_SUPERQ_FULL_L3BANK23_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext51_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext51";
    metric_set->symbol_name = "Ext51";
    metric_set->hw_config_guid = "22089a93-123e-4b18-80c6-5aca789ae5a6";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext51_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext51__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext51__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext51__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext51__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 SUPERQ FULL L3BANK16",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK16",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext51__l3_superq_full_l3_bank16__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext51_L3_SUPERQ_FULL_L3BANK16_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK17",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK17",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext51__l3_superq_full_l3_bank17__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext51_L3_SUPERQ_FULL_L3BANK17_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK18",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK18",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext51__l3_superq_full_l3_bank18__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext51_L3_SUPERQ_FULL_L3BANK18_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK19",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK19",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext51__l3_superq_full_l3_bank19__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext51_L3_SUPERQ_FULL_L3BANK19_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK20",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK20",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext51__l3_superq_full_l3_bank20__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext51_L3_SUPERQ_FULL_L3BANK20_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK21",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK21",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext51__l3_superq_full_l3_bank21__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext51_L3_SUPERQ_FULL_L3BANK21_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK22",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK22",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext51__l3_superq_full_l3_bank22__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext51_L3_SUPERQ_FULL_L3BANK22_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK23",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK23",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext51__l3_superq_full_l3_bank23__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext51_L3_SUPERQ_FULL_L3BANK23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext52_L3_SUPERQ_FULL_L3BANK24_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext52_L3_SUPERQ_FULL_L3BANK25_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext52_L3_SUPERQ_FULL_L3BANK26_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext52_L3_SUPERQ_FULL_L3BANK27_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext52_L3_SUPERQ_FULL_L3BANK28_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext52_L3_SUPERQ_FULL_L3BANK29_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext52_L3_SUPERQ_FULL_L3BANK30_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext52_L3_SUPERQ_FULL_L3BANK31_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext52_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext52";
    metric_set->symbol_name = "Ext52";
    metric_set->hw_config_guid = "b8d0b133-7e12-4338-adf3-41034b6a37cd";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext52_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext52__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext52__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext52__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext52__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 SUPERQ FULL L3BANK24",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK24",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext52__l3_superq_full_l3_bank24__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext52_L3_SUPERQ_FULL_L3BANK24_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK25",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK25",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext52__l3_superq_full_l3_bank25__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext52_L3_SUPERQ_FULL_L3BANK25_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK26",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK26",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext52__l3_superq_full_l3_bank26__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext52_L3_SUPERQ_FULL_L3BANK26_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK27",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK27",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext52__l3_superq_full_l3_bank27__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext52_L3_SUPERQ_FULL_L3BANK27_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK28",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK28",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext52__l3_superq_full_l3_bank28__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext52_L3_SUPERQ_FULL_L3BANK28_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK29",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK29",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext52__l3_superq_full_l3_bank29__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext52_L3_SUPERQ_FULL_L3BANK29_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK30",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK30",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext52__l3_superq_full_l3_bank30__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext52_L3_SUPERQ_FULL_L3BANK30_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK31",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK31",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext52__l3_superq_full_l3_bank31__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext52_L3_SUPERQ_FULL_L3BANK31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext53_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext53_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext53_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext53";
    metric_set->symbol_name = "Ext53";
    metric_set->hw_config_guid = "3012f753-92cb-4f10-b5a8-437ac9bb77f1";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext53_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext53__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext53__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext53__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext53__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext53__xve_load_store_cache_read_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext53_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext53__xve_load_store_cache_read_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext53_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext54_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext54_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext54_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext54";
    metric_set->symbol_name = "Ext54";
    metric_set->hw_config_guid = "f585cd71-e1d5-4c8c-912e-399f0680c73f";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext54_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext54__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext54__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext54__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext54__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext54__xve_load_store_cache_read_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext54_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE3",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext54__xve_load_store_cache_read_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext54_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext55_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext55_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext55_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext55";
    metric_set->symbol_name = "Ext55";
    metric_set->hw_config_guid = "f16c9548-0371-4a07-9522-44f9289e2756";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext55_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext55__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext55__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext55__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext55__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext55__xve_load_store_cache_read_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext55_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE5",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext55__xve_load_store_cache_read_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext55_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext56_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext56_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext56_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext56";
    metric_set->symbol_name = "Ext56";
    metric_set->hw_config_guid = "806924c4-d2c4-4861-b2cd-6d3ce66586cf";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext56_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext56__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext56__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext56__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext56__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext56__xve_load_store_cache_read_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext56_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext56__xve_load_store_cache_read_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext56_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext57_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext57_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext57_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext57";
    metric_set->symbol_name = "Ext57";
    metric_set->hw_config_guid = "4a24b85d-8511-468b-98ca-9944600637a8";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext57_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext57__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext57__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext57__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext57__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE8",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE8",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext57__xve_load_store_cache_read_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext57_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE9",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE9",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext57__xve_load_store_cache_read_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext57_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext58_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext58_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext58_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext58";
    metric_set->symbol_name = "Ext58";
    metric_set->hw_config_guid = "3573dd0a-8981-45a3-85e5-7850871e9eca";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext58_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext58__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext58__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext58__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext58__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE10",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE10",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext58__xve_load_store_cache_read_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext58_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE11",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE11",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext58__xve_load_store_cache_read_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext58_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext59_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext59_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext59_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext59";
    metric_set->symbol_name = "Ext59";
    metric_set->hw_config_guid = "4dbde56d-e0bb-4f3a-b2a7-0a87baf4462e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext59_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext59__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext59__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext59__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext59__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE12",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE12",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext59__xve_load_store_cache_read_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext59_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE13",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE13",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext59__xve_load_store_cache_read_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext59_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext60_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext60_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext60_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext60";
    metric_set->symbol_name = "Ext60";
    metric_set->hw_config_guid = "d24e53df-6340-4a08-8449-54d69fdad628";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext60_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext60__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext60__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext60__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext60__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE14",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE14",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext60__xve_load_store_cache_read_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext60_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE15",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE15",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext60__xve_load_store_cache_read_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext60_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext61_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext61_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext61_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext61";
    metric_set->symbol_name = "Ext61";
    metric_set->hw_config_guid = "0e24a924-838e-4f24-bb83-1c6aa4e9a602";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext61_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext61__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext61__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext61__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext61__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE16",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE16",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext61__xve_load_store_cache_read_message_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext61_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE16_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE17",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE17",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext61__xve_load_store_cache_read_message_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext61_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE17_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext62_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext62_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext62_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext62";
    metric_set->symbol_name = "Ext62";
    metric_set->hw_config_guid = "c6f5a056-c412-4425-9877-a2309ebd61bb";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext62_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext62__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext62__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext62__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext62__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE18",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE18",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext62__xve_load_store_cache_read_message_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext62_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE18_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE19",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE19",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext62__xve_load_store_cache_read_message_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext62_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext63_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext63_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext63_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext63";
    metric_set->symbol_name = "Ext63";
    metric_set->hw_config_guid = "e301dc02-b677-468a-9038-c741af4d91ed";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext63_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext63__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext63__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext63__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext63__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE20",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE20",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext63__xve_load_store_cache_read_message_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext63_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE20_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE21",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE21",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext63__xve_load_store_cache_read_message_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext63_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE21_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext64_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext64_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext64_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext64";
    metric_set->symbol_name = "Ext64";
    metric_set->hw_config_guid = "e595dd56-de7c-40ff-bea9-b9a15d893b11";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext64_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext64__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext64__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext64__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext64__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE22",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE22",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext64__xve_load_store_cache_read_message_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext64_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE22_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE23",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE23",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext64__xve_load_store_cache_read_message_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext64_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext65_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext65_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext65_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext65";
    metric_set->symbol_name = "Ext65";
    metric_set->hw_config_guid = "7c8329df-0d11-4685-9762-8530d350aa19";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext65_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext65__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext65__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext65__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext65__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE24",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE24",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext65__xve_load_store_cache_read_message_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext65_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE24_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE25",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE25",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext65__xve_load_store_cache_read_message_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext65_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE25_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext66_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext66_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext66_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext66";
    metric_set->symbol_name = "Ext66";
    metric_set->hw_config_guid = "d02aa389-0a8e-42f0-b62b-7b8091f23fe7";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext66_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext66__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext66__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext66__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext66__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE26",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE26",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext66__xve_load_store_cache_read_message_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext66_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE26_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE27",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE27",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext66__xve_load_store_cache_read_message_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext66_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext67_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext67_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext67_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext67";
    metric_set->symbol_name = "Ext67";
    metric_set->hw_config_guid = "cf345893-06de-44cb-9d0b-3dde2f62947d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext67_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext67__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext67__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext67__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext67__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE28",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE28",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext67__xve_load_store_cache_read_message_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext67_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE28_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE29",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE29",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext67__xve_load_store_cache_read_message_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext67_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE29_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext68_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext68_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext68_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext68";
    metric_set->symbol_name = "Ext68";
    metric_set->hw_config_guid = "23bd55f6-39b5-48af-8cf8-b7c136e60052";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext68_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext68__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext68__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext68__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext68__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE30",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE30",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext68__xve_load_store_cache_read_message_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext68_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE30_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE31",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE31",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext68__xve_load_store_cache_read_message_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext68_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext69_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext69_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext69_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext69";
    metric_set->symbol_name = "Ext69";
    metric_set->hw_config_guid = "464517de-6883-4550-86c5-4e084b2a34dc";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext69_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext69__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext69__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext69__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext69__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE0",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext69__xve_load_store_cache_write_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext69_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE1",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext69__xve_load_store_cache_write_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext69_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext70_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext70_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext70_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext70";
    metric_set->symbol_name = "Ext70";
    metric_set->hw_config_guid = "ccd967c5-9110-4c66-aabb-435114ebf67a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext70_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext70__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext70__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext70__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext70__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE2",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext70__xve_load_store_cache_write_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext70_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE3",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext70__xve_load_store_cache_write_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext70_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext71_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext71_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext71_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext71";
    metric_set->symbol_name = "Ext71";
    metric_set->hw_config_guid = "df75cd02-66d3-41f2-96ad-d53003d4b0b8";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext71_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext71__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext71__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext71__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext71__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE4",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext71__xve_load_store_cache_write_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext71_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE5",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext71__xve_load_store_cache_write_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext71_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext72_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext72_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext72_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext72";
    metric_set->symbol_name = "Ext72";
    metric_set->hw_config_guid = "adfba67d-3d40-4b20-92a8-70d11c8cffbb";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext72_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext72__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext72__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext72__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext72__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE6",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext72__xve_load_store_cache_write_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext72_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE7",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext72__xve_load_store_cache_write_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext72_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext73_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext73_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext73_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext73";
    metric_set->symbol_name = "Ext73";
    metric_set->hw_config_guid = "e13dd0e5-e6ba-4a86-8e32-d5971abd8571";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext73_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext73__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext73__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext73__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext73__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE8",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE8",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext73__xve_load_store_cache_write_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext73_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE9",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE9",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext73__xve_load_store_cache_write_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext73_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext74_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext74_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext74_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext74";
    metric_set->symbol_name = "Ext74";
    metric_set->hw_config_guid = "e75ed2f8-19f0-44d0-ae03-ca2a8afbdbc7";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext74_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext74__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext74__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext74__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext74__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE10",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE10",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext74__xve_load_store_cache_write_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext74_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE11",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE11",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext74__xve_load_store_cache_write_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext74_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext75_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext75_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext75_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext75";
    metric_set->symbol_name = "Ext75";
    metric_set->hw_config_guid = "ddac10e6-c812-4b70-a61e-e6f9e43e47d1";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext75_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext75__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext75__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext75__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext75__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE12",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE12",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext75__xve_load_store_cache_write_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext75_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE13",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE13",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext75__xve_load_store_cache_write_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext75_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext76_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext76_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext76_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext76";
    metric_set->symbol_name = "Ext76";
    metric_set->hw_config_guid = "8eea86e6-a456-499a-9c4d-dec0dcfd9a8c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext76_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext76__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext76__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext76__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext76__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE14",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE14",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext76__xve_load_store_cache_write_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext76_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE15",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE15",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext76__xve_load_store_cache_write_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext76_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext77_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext77_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext77_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext77";
    metric_set->symbol_name = "Ext77";
    metric_set->hw_config_guid = "fedc5df4-a74e-4de8-9296-96571b72092a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext77_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext77__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext77__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext77__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext77__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE16",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE16",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext77__xve_load_store_cache_write_message_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext77_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE16_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE17",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE17",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext77__xve_load_store_cache_write_message_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext77_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE17_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext78_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext78_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext78_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext78";
    metric_set->symbol_name = "Ext78";
    metric_set->hw_config_guid = "c144b291-ed97-49e3-beab-2bbbf83353e8";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext78_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext78__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext78__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext78__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext78__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE18",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE18",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext78__xve_load_store_cache_write_message_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext78_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE18_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE19",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE19",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext78__xve_load_store_cache_write_message_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext78_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext79_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext79_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext79_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext79";
    metric_set->symbol_name = "Ext79";
    metric_set->hw_config_guid = "15f74cc9-7e20-46fa-bbd5-f8f363c99d8d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext79_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext79__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext79__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext79__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext79__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE20",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE20",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext79__xve_load_store_cache_write_message_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext79_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE20_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE21",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE21",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext79__xve_load_store_cache_write_message_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext79_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE21_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext80_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext80_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext80_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext80";
    metric_set->symbol_name = "Ext80";
    metric_set->hw_config_guid = "8a2cc3e1-3df7-4f4a-ba68-73bd1fd0c371";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext80_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext80__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext80__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext80__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext80__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE22",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE22",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext80__xve_load_store_cache_write_message_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext80_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE22_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE23",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE23",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext80__xve_load_store_cache_write_message_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext80_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext81_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext81_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext81_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext81";
    metric_set->symbol_name = "Ext81";
    metric_set->hw_config_guid = "44a0a4a3-e4c3-4a48-bd62-47154ca53a10";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext81_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext81__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext81__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext81__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext81__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE24",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE24",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext81__xve_load_store_cache_write_message_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext81_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE24_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE25",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE25",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext81__xve_load_store_cache_write_message_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext81_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE25_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext82_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext82_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext82_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext82";
    metric_set->symbol_name = "Ext82";
    metric_set->hw_config_guid = "66cd1f83-fe8c-42ef-9b9b-6674a054e256";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext82_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext82__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext82__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext82__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext82__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE26",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE26",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext82__xve_load_store_cache_write_message_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext82_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE26_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE27",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE27",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext82__xve_load_store_cache_write_message_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext82_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext83_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext83_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext83_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext83";
    metric_set->symbol_name = "Ext83";
    metric_set->hw_config_guid = "77059291-c7bb-4048-ab5f-ab239b75f8f3";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext83_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext83__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext83__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext83__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext83__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE28",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE28",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext83__xve_load_store_cache_write_message_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext83_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE28_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE29",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE29",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext83__xve_load_store_cache_write_message_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext83_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE29_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext84_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext84_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext84_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext84";
    metric_set->symbol_name = "Ext84";
    metric_set->hw_config_guid = "73d8a4d2-dadb-4b04-b368-d21f1587206d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext84_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext84__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext84__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext84__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext84__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE30",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE30",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext84__xve_load_store_cache_write_message_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext84_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE30_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE31",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE31",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext84__xve_load_store_cache_write_message_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext84_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext85_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext85_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext85";
    metric_set->symbol_name = "Ext85";
    metric_set->hw_config_guid = "463c75f3-e572-4f30-a6e0-86635e2e2bb5";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext85_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext85__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext85__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext85__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext85__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE0",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext85__xve_load_store_cache_atomic_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext85_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext86_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext86_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext86";
    metric_set->symbol_name = "Ext86";
    metric_set->hw_config_guid = "41c4ea0d-eeab-4e80-b8ef-e0bfbbf178e4";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext86_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext86__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext86__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext86__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext86__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE1",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext86__xve_load_store_cache_atomic_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext86_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext87_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext87_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext87";
    metric_set->symbol_name = "Ext87";
    metric_set->hw_config_guid = "2d7cb182-179b-4d5e-ac1a-0fb084054a79";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext87_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext87__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext87__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext87__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext87__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE2",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext87__xve_load_store_cache_atomic_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext87_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext88_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext88_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext88";
    metric_set->symbol_name = "Ext88";
    metric_set->hw_config_guid = "00c41d05-9419-43a2-baa7-157ba0558803";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext88_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext88__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext88__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext88__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext88__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE3",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext88__xve_load_store_cache_atomic_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext88_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext89_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext89_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext89";
    metric_set->symbol_name = "Ext89";
    metric_set->hw_config_guid = "743a4a2d-4cbc-43d2-870e-bb2ccaf85fef";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext89_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext89__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext89__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext89__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext89__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE4",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext89__xve_load_store_cache_atomic_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext89_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext90_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext90_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext90";
    metric_set->symbol_name = "Ext90";
    metric_set->hw_config_guid = "2d4814e9-bbbd-474f-8705-e84b358bb946";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext90_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext90__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext90__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext90__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext90__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE5",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext90__xve_load_store_cache_atomic_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext90_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext91_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext91_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext91";
    metric_set->symbol_name = "Ext91";
    metric_set->hw_config_guid = "cdac43dd-b724-412a-bba3-cbca3655f487";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext91_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext91__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext91__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext91__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext91__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE6",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext91__xve_load_store_cache_atomic_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext91_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext92_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext92_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext92";
    metric_set->symbol_name = "Ext92";
    metric_set->hw_config_guid = "e8486fa5-fdf7-4629-8f90-cf4365951bab";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext92_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext92__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext92__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext92__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext92__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE7",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext92__xve_load_store_cache_atomic_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext92_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext93_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext93_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext93";
    metric_set->symbol_name = "Ext93";
    metric_set->hw_config_guid = "808604f1-6872-4afa-9b81-47df20489b9f";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext93_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext93__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext93__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext93__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext93__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE8",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE8",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext93__xve_load_store_cache_atomic_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext93_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE8_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext94_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext94_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext94";
    metric_set->symbol_name = "Ext94";
    metric_set->hw_config_guid = "a06f53f5-e778-48a7-9bcc-d6aaf9fd6e7b";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext94_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext94__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext94__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext94__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext94__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE9",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE9",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext94__xve_load_store_cache_atomic_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext94_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext95_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext95_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext95";
    metric_set->symbol_name = "Ext95";
    metric_set->hw_config_guid = "cef87716-edfd-4d06-985f-1d04654dcdca";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext95_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext95__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext95__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext95__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext95__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE10",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE10",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext95__xve_load_store_cache_atomic_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext95_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE10_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext96_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext96_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext96";
    metric_set->symbol_name = "Ext96";
    metric_set->hw_config_guid = "20e3d0ca-8d80-4590-997c-818512c59e5d";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext96_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext96__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext96__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext96__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext96__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE11",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE11",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext96__xve_load_store_cache_atomic_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext96_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext97_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext97_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext97";
    metric_set->symbol_name = "Ext97";
    metric_set->hw_config_guid = "37fc43b8-fce9-4eba-a268-aa8242bba6d7";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext97_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext97__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext97__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext97__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext97__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE12",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE12",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext97__xve_load_store_cache_atomic_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext97_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE12_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext98_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext98_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext98";
    metric_set->symbol_name = "Ext98";
    metric_set->hw_config_guid = "c962e059-3012-4bd3-98e6-b25c7306bb38";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext98_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext98__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext98__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext98__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext98__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE13",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE13",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext98__xve_load_store_cache_atomic_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext98_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext99_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext99_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext99";
    metric_set->symbol_name = "Ext99";
    metric_set->hw_config_guid = "5462b931-faf7-4351-abb9-e31a93cd0c67";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext99_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext99__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext99__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext99__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext99__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE14",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE14",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext99__xve_load_store_cache_atomic_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext99_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE14_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext100_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext100_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext100";
    metric_set->symbol_name = "Ext100";
    metric_set->hw_config_guid = "2f212e4b-0dab-40cf-9b07-2ca40d7f8c9c";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext100_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext100__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext100__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext100__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext100__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE15",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE15",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext100__xve_load_store_cache_atomic_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext100_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext101_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext101_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext101";
    metric_set->symbol_name = "Ext101";
    metric_set->hw_config_guid = "945c799b-3062-4a46-995a-2527d8c6a550";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext101_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext101__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext101__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext101__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext101__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE16",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE16",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext101__xve_load_store_cache_atomic_message_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext101_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE16_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext102_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext102_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext102";
    metric_set->symbol_name = "Ext102";
    metric_set->hw_config_guid = "c2e93414-bb8d-43b4-a992-97f998abfefb";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext102_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext102__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext102__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext102__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext102__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE17",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE17",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext102__xve_load_store_cache_atomic_message_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext102_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE17_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext103_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext103_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext103";
    metric_set->symbol_name = "Ext103";
    metric_set->hw_config_guid = "fd4fca73-0631-42d7-89c1-0821a3e0f3c3";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext103_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext103__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext103__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext103__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext103__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE18",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE18",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext103__xve_load_store_cache_atomic_message_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext103_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE18_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext104_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext104_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext104";
    metric_set->symbol_name = "Ext104";
    metric_set->hw_config_guid = "4c457fa7-afa6-4ab4-8489-e6eb0d7fbfa7";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext104_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext104__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext104__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext104__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext104__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE19",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE19",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext104__xve_load_store_cache_atomic_message_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext104_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext105_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext105_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext105";
    metric_set->symbol_name = "Ext105";
    metric_set->hw_config_guid = "218b02bc-7e36-488f-894d-9d97b9501b1a";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext105_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext105__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext105__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext105__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext105__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE20",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE20",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext105__xve_load_store_cache_atomic_message_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext105_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE20_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext106_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext106_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext106";
    metric_set->symbol_name = "Ext106";
    metric_set->hw_config_guid = "673836b5-04ac-405b-b85c-cbe99892ba08";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext106_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext106__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext106__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext106__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext106__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE21",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE21",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext106__xve_load_store_cache_atomic_message_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext106_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE21_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext107_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext107_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext107";
    metric_set->symbol_name = "Ext107";
    metric_set->hw_config_guid = "3fa5d581-bfb6-4afd-a13d-9af9db03938f";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext107_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext107__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext107__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext107__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext107__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE22",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE22",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext107__xve_load_store_cache_atomic_message_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext107_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE22_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext108_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext108_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext108";
    metric_set->symbol_name = "Ext108";
    metric_set->hw_config_guid = "516bd2fc-3b14-4700-97e5-988aac08db2a";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext108_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext108__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext108__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext108__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext108__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE23",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE23",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext108__xve_load_store_cache_atomic_message_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext108_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext109_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext109_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext109";
    metric_set->symbol_name = "Ext109";
    metric_set->hw_config_guid = "6897c9a4-ae80-4001-915e-9201413ae86f";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext109_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext109__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext109__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext109__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext109__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE24",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE24",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext109__xve_load_store_cache_atomic_message_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext109_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE24_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext110_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext110_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext110";
    metric_set->symbol_name = "Ext110";
    metric_set->hw_config_guid = "3922417a-c9a0-41fd-83ee-1de270990952";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext110_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext110__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext110__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext110__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext110__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE25",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE25",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext110__xve_load_store_cache_atomic_message_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext110_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE25_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext111_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext111_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext111";
    metric_set->symbol_name = "Ext111";
    metric_set->hw_config_guid = "2121affe-e3d8-496f-89cf-e9b21861ca69";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext111_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext111__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext111__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext111__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext111__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE26",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE26",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext111__xve_load_store_cache_atomic_message_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext111_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE26_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext112_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext112_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext112";
    metric_set->symbol_name = "Ext112";
    metric_set->hw_config_guid = "68cc12ab-8876-4071-8e2b-ea662e59d9ee";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext112_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext112__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext112__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext112__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext112__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE27",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE27",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext112__xve_load_store_cache_atomic_message_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext112_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext113_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext113_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext113";
    metric_set->symbol_name = "Ext113";
    metric_set->hw_config_guid = "35fe4526-b6a1-438c-8592-b98c00bd5776";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext113_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext113__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext113__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext113__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext113__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE28",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE28",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext113__xve_load_store_cache_atomic_message_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext113_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE28_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext114_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext114_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext114";
    metric_set->symbol_name = "Ext114";
    metric_set->hw_config_guid = "1093f7ed-ac49-48d0-ae94-0985d6a59ad9";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext114_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext114__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext114__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext114__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext114__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE29",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE29",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext114__xve_load_store_cache_atomic_message_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext114_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE29_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext115_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext115_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext115";
    metric_set->symbol_name = "Ext115";
    metric_set->hw_config_guid = "65011d06-3903-4ec8-9e1d-54cb8ad171de";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext115_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext115__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext115__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext115__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext115__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE30",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE30",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext115__xve_load_store_cache_atomic_message_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext115_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE30_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext116_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext116_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext116";
    metric_set->symbol_name = "Ext116";
    metric_set->hw_config_guid = "07a01ff3-9f44-4798-93f7-8defeeee8a20";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext116_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext116__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext116__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext116__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext116__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE31",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE31",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext116__xve_load_store_cache_atomic_message_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext116_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext117_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext117_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext117_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext117";
    metric_set->symbol_name = "Ext117";
    metric_set->hw_config_guid = "aeb29684-3152-48c8-8cb7-4bc25712605f";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext117_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext117__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext117__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext117__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext117__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE0",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext117__xve_load_store_cache_fence_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext117_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE1",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext117__xve_load_store_cache_fence_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext117_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext118_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext118_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext118_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext118";
    metric_set->symbol_name = "Ext118";
    metric_set->hw_config_guid = "beffa74f-caca-4b88-8f7d-7f01c3bc033b";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext118_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext118__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext118__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext118__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext118__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE2",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext118__xve_load_store_cache_fence_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext118_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE3",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext118__xve_load_store_cache_fence_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext118_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext119_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext119_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext119_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext119";
    metric_set->symbol_name = "Ext119";
    metric_set->hw_config_guid = "415ffe47-ea31-4697-a982-ee90636ed944";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext119_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext119__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext119__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext119__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext119__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE4",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext119__xve_load_store_cache_fence_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext119_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE5",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext119__xve_load_store_cache_fence_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext119_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext120_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext120_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext120_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext120";
    metric_set->symbol_name = "Ext120";
    metric_set->hw_config_guid = "8112be50-e97f-44dc-b790-bc09eca28009";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext120_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext120__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext120__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext120__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext120__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE6",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext120__xve_load_store_cache_fence_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext120_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE7",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext120__xve_load_store_cache_fence_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext120_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext121_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext121_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext121_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext121";
    metric_set->symbol_name = "Ext121";
    metric_set->hw_config_guid = "e4c09690-3425-467a-a9cc-4a858c817c0f";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext121_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext121__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext121__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext121__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext121__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE8",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE8",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext121__xve_load_store_cache_fence_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext121_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE9",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE9",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext121__xve_load_store_cache_fence_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext121_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext122_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext122_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext122_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext122";
    metric_set->symbol_name = "Ext122";
    metric_set->hw_config_guid = "61157f65-aab4-4b3d-b780-658829e378e2";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext122_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext122__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext122__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext122__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext122__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE10",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE10",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext122__xve_load_store_cache_fence_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext122_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE11",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE11",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext122__xve_load_store_cache_fence_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext122_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext123_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext123_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext123_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext123";
    metric_set->symbol_name = "Ext123";
    metric_set->hw_config_guid = "4a875c0a-59be-4dc2-bdd1-948745fe142e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext123_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext123__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext123__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext123__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext123__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE12",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE12",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext123__xve_load_store_cache_fence_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext123_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE13",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE13",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext123__xve_load_store_cache_fence_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext123_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext124_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext124_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext124_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext124";
    metric_set->symbol_name = "Ext124";
    metric_set->hw_config_guid = "8c1d463d-eee4-4f13-b01b-4b120fbbb4ad";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext124_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext124__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext124__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext124__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext124__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE14",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE14",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext124__xve_load_store_cache_fence_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext124_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE15",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE15",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext124__xve_load_store_cache_fence_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext124_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext125_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext125_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext125_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext125";
    metric_set->symbol_name = "Ext125";
    metric_set->hw_config_guid = "b6abefa1-e939-431b-8975-e1c687f437b3";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext125_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext125__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext125__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext125__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext125__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE16",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE16",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext125__xve_load_store_cache_fence_message_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext125_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE16_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE17",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE17",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext125__xve_load_store_cache_fence_message_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext125_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE17_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext126_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext126_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext126_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext126";
    metric_set->symbol_name = "Ext126";
    metric_set->hw_config_guid = "7aa427eb-754a-4222-b199-d41bc47ad3c8";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext126_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext126__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext126__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext126__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext126__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE18",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE18",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext126__xve_load_store_cache_fence_message_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext126_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE18_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE19",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE19",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext126__xve_load_store_cache_fence_message_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext126_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext127_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext127_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext127_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext127";
    metric_set->symbol_name = "Ext127";
    metric_set->hw_config_guid = "101df6ed-1648-43a4-a44a-21440a9df6b1";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext127_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext127__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext127__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext127__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext127__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE20",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE20",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext127__xve_load_store_cache_fence_message_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext127_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE20_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE21",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE21",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext127__xve_load_store_cache_fence_message_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext127_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE21_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext128_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext128_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext128_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext128";
    metric_set->symbol_name = "Ext128";
    metric_set->hw_config_guid = "edf10822-9b87-4c5a-9d08-de730b73783c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext128_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext128__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext128__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext128__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext128__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE22",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE22",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext128__xve_load_store_cache_fence_message_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext128_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE22_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE23",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE23",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext128__xve_load_store_cache_fence_message_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext128_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext129_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext129_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext129_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext129";
    metric_set->symbol_name = "Ext129";
    metric_set->hw_config_guid = "57adc349-a036-4227-bb0b-f35df5cdefc0";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext129_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext129__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext129__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext129__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext129__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE24",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE24",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext129__xve_load_store_cache_fence_message_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext129_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE24_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE25",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE25",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext129__xve_load_store_cache_fence_message_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext129_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE25_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext130_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext130_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext130_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext130";
    metric_set->symbol_name = "Ext130";
    metric_set->hw_config_guid = "fa55a401-6330-4838-ba1d-97d99d1b3dab";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext130_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext130__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext130__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext130__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext130__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE26",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE26",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext130__xve_load_store_cache_fence_message_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext130_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE26_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE27",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE27",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext130__xve_load_store_cache_fence_message_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext130_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext131_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext131_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext131_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext131";
    metric_set->symbol_name = "Ext131";
    metric_set->hw_config_guid = "b3dcbad6-531c-42f5-be91-de0a33aa7a74";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext131_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext131__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext131__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext131__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext131__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE28",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE28",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext131__xve_load_store_cache_fence_message_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext131_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE28_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE29",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE29",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext131__xve_load_store_cache_fence_message_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext131_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE29_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext132_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext132_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext132_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext132";
    metric_set->symbol_name = "Ext132";
    metric_set->hw_config_guid = "f2043fc3-5aae-42c7-aa3f-eabd0cf24b60";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext132_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext132__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext132__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext132__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext132__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE30",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE30",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext132__xve_load_store_cache_fence_message_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext132_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE30_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE31",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE31",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext132__xve_load_store_cache_fence_message_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext132_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext133_XVE_SLM_READ_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext133_XVE_SLM_READ_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext133_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext133";
    metric_set->symbol_name = "Ext133";
    metric_set->hw_config_guid = "fc8faaca-0410-41a8-baa5-881d1c172763";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext133_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext133__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext133__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext133__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext133__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE0",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext133__xve_slm_read_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext133_XVE_SLM_READ_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE1",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext133__xve_slm_read_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext133_XVE_SLM_READ_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext134_XVE_SLM_READ_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext134_XVE_SLM_READ_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext134_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext134";
    metric_set->symbol_name = "Ext134";
    metric_set->hw_config_guid = "c87b7319-7935-4642-b124-c14ad8fda69d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext134_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext134__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext134__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext134__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext134__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE2",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext134__xve_slm_read_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext134_XVE_SLM_READ_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE3",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext134__xve_slm_read_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext134_XVE_SLM_READ_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext135_XVE_SLM_READ_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext135_XVE_SLM_READ_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext135_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext135";
    metric_set->symbol_name = "Ext135";
    metric_set->hw_config_guid = "3e0b0511-a1d8-4bfe-b1ef-48520609b5bb";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext135_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext135__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext135__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext135__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext135__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE4",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext135__xve_slm_read_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext135_XVE_SLM_READ_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE5",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext135__xve_slm_read_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext135_XVE_SLM_READ_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext136_XVE_SLM_READ_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext136_XVE_SLM_READ_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext136_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext136";
    metric_set->symbol_name = "Ext136";
    metric_set->hw_config_guid = "44085566-4f70-4640-aafd-bbc83062552a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext136_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext136__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext136__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext136__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext136__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE6",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext136__xve_slm_read_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext136_XVE_SLM_READ_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE7",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext136__xve_slm_read_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext136_XVE_SLM_READ_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext137_XVE_SLM_READ_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext137_XVE_SLM_READ_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext137_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext137";
    metric_set->symbol_name = "Ext137";
    metric_set->hw_config_guid = "c7d9a6b4-b939-4eb2-a272-1737f6f3df45";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext137_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext137__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext137__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext137__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext137__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE8",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE8",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext137__xve_slm_read_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext137_XVE_SLM_READ_MESSAGE_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE9",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE9",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext137__xve_slm_read_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext137_XVE_SLM_READ_MESSAGE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext138_XVE_SLM_READ_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext138_XVE_SLM_READ_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext138_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext138";
    metric_set->symbol_name = "Ext138";
    metric_set->hw_config_guid = "428b3770-8cd8-469c-b83f-545610b80760";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext138_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext138__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext138__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext138__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext138__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE10",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE10",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext138__xve_slm_read_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext138_XVE_SLM_READ_MESSAGE_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE11",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE11",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext138__xve_slm_read_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext138_XVE_SLM_READ_MESSAGE_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext139_XVE_SLM_READ_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext139_XVE_SLM_READ_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext139_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext139";
    metric_set->symbol_name = "Ext139";
    metric_set->hw_config_guid = "4e566d7d-9e9d-439a-9d4c-bc2fd96d7716";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext139_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext139__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext139__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext139__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext139__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE12",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE12",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext139__xve_slm_read_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext139_XVE_SLM_READ_MESSAGE_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE13",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE13",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext139__xve_slm_read_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext139_XVE_SLM_READ_MESSAGE_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext140_XVE_SLM_READ_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext140_XVE_SLM_READ_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext140_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext140";
    metric_set->symbol_name = "Ext140";
    metric_set->hw_config_guid = "9f0b112a-780a-4e61-9d1f-47f90b536d59";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext140_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext140__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext140__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext140__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext140__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE14",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE14",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext140__xve_slm_read_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext140_XVE_SLM_READ_MESSAGE_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE15",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE15",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext140__xve_slm_read_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext140_XVE_SLM_READ_MESSAGE_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext141_XVE_SLM_READ_MESSAGE_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext141_XVE_SLM_READ_MESSAGE_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext141_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext141";
    metric_set->symbol_name = "Ext141";
    metric_set->hw_config_guid = "854fb71e-5727-4f1d-9384-52b395a4d8a3";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext141_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext141__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext141__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext141__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext141__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE16",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE16",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext141__xve_slm_read_message_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext141_XVE_SLM_READ_MESSAGE_COUNT_XECORE16_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE17",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE17",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext141__xve_slm_read_message_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext141_XVE_SLM_READ_MESSAGE_COUNT_XECORE17_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext142_XVE_SLM_READ_MESSAGE_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext142_XVE_SLM_READ_MESSAGE_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext142_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext142";
    metric_set->symbol_name = "Ext142";
    metric_set->hw_config_guid = "fe0561e1-8d92-495c-b849-4d9707cf5682";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext142_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext142__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext142__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext142__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext142__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE18",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE18",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext142__xve_slm_read_message_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext142_XVE_SLM_READ_MESSAGE_COUNT_XECORE18_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE19",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE19",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext142__xve_slm_read_message_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext142_XVE_SLM_READ_MESSAGE_COUNT_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext143_XVE_SLM_READ_MESSAGE_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext143_XVE_SLM_READ_MESSAGE_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext143_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext143";
    metric_set->symbol_name = "Ext143";
    metric_set->hw_config_guid = "46dbfe20-297f-437b-a33f-55e3a55b3f49";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext143_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext143__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext143__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext143__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext143__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE20",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE20",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext143__xve_slm_read_message_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext143_XVE_SLM_READ_MESSAGE_COUNT_XECORE20_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE21",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE21",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext143__xve_slm_read_message_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext143_XVE_SLM_READ_MESSAGE_COUNT_XECORE21_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext144_XVE_SLM_READ_MESSAGE_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext144_XVE_SLM_READ_MESSAGE_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext144_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext144";
    metric_set->symbol_name = "Ext144";
    metric_set->hw_config_guid = "771f932d-6d5d-455a-ac07-95b7944cf0f3";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext144_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext144__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext144__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext144__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext144__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE22",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE22",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext144__xve_slm_read_message_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext144_XVE_SLM_READ_MESSAGE_COUNT_XECORE22_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE23",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE23",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext144__xve_slm_read_message_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext144_XVE_SLM_READ_MESSAGE_COUNT_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext145_XVE_SLM_READ_MESSAGE_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext145_XVE_SLM_READ_MESSAGE_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext145_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext145";
    metric_set->symbol_name = "Ext145";
    metric_set->hw_config_guid = "8798172d-cd55-4b8b-bdd4-b0e4506f5814";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext145_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext145__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext145__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext145__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext145__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE24",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE24",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext145__xve_slm_read_message_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext145_XVE_SLM_READ_MESSAGE_COUNT_XECORE24_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE25",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE25",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext145__xve_slm_read_message_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext145_XVE_SLM_READ_MESSAGE_COUNT_XECORE25_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext146_XVE_SLM_READ_MESSAGE_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext146_XVE_SLM_READ_MESSAGE_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext146_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext146";
    metric_set->symbol_name = "Ext146";
    metric_set->hw_config_guid = "cdb10de1-e17b-4a8b-b90c-19de2c4759f9";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext146_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext146__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext146__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext146__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext146__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE26",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE26",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext146__xve_slm_read_message_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext146_XVE_SLM_READ_MESSAGE_COUNT_XECORE26_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE27",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE27",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext146__xve_slm_read_message_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext146_XVE_SLM_READ_MESSAGE_COUNT_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext147_XVE_SLM_READ_MESSAGE_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext147_XVE_SLM_READ_MESSAGE_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext147_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext147";
    metric_set->symbol_name = "Ext147";
    metric_set->hw_config_guid = "23705ec8-4cd3-4907-a1ad-3fe56529d8ff";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext147_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext147__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext147__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext147__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext147__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE28",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE28",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext147__xve_slm_read_message_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext147_XVE_SLM_READ_MESSAGE_COUNT_XECORE28_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE29",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE29",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext147__xve_slm_read_message_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext147_XVE_SLM_READ_MESSAGE_COUNT_XECORE29_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext148_XVE_SLM_READ_MESSAGE_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext148_XVE_SLM_READ_MESSAGE_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext148_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext148";
    metric_set->symbol_name = "Ext148";
    metric_set->hw_config_guid = "dbed477b-2c30-478d-b3fa-b5615416b1af";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext148_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext148__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext148__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext148__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext148__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE30",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE30",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext148__xve_slm_read_message_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext148_XVE_SLM_READ_MESSAGE_COUNT_XECORE30_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE31",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE31",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext148__xve_slm_read_message_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext148_XVE_SLM_READ_MESSAGE_COUNT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext149_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext149_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext149_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext149";
    metric_set->symbol_name = "Ext149";
    metric_set->hw_config_guid = "8f6adfed-5fbc-42c7-80f2-30904a388408";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext149_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext149__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext149__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext149__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext149__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE0",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext149__xve_slm_write_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext149_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE1",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext149__xve_slm_write_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext149_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext150_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext150_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext150_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext150";
    metric_set->symbol_name = "Ext150";
    metric_set->hw_config_guid = "aed081c7-ab5e-46c5-bedf-91477e538dd6";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext150_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext150__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext150__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext150__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext150__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE2",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext150__xve_slm_write_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext150_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE3",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext150__xve_slm_write_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext150_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext151_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext151_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext151_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext151";
    metric_set->symbol_name = "Ext151";
    metric_set->hw_config_guid = "a09e1665-c5dd-4819-81fa-04a797f9de26";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext151_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext151__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext151__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext151__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext151__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE4",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext151__xve_slm_write_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext151_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE5",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext151__xve_slm_write_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext151_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext152_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext152_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext152_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext152";
    metric_set->symbol_name = "Ext152";
    metric_set->hw_config_guid = "c963fbd4-f12b-4c8b-b5a8-03aff5190950";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext152_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext152__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext152__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext152__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext152__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE6",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext152__xve_slm_write_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext152_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE7",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext152__xve_slm_write_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext152_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext153_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext153_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext153_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext153";
    metric_set->symbol_name = "Ext153";
    metric_set->hw_config_guid = "a7cf7aba-86a2-45dd-baa3-e877df9883f3";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext153_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext153__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext153__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext153__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext153__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE8",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE8",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext153__xve_slm_write_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext153_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE9",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE9",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext153__xve_slm_write_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext153_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext154_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext154_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext154_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext154";
    metric_set->symbol_name = "Ext154";
    metric_set->hw_config_guid = "5207e446-2d9c-4d66-8afa-2f474c9d403a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext154_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext154__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext154__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext154__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext154__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE10",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE10",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext154__xve_slm_write_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext154_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE11",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE11",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext154__xve_slm_write_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext154_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext155_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext155_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext155_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext155";
    metric_set->symbol_name = "Ext155";
    metric_set->hw_config_guid = "446e638a-6570-4b0a-b980-15071ca6a136";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext155_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext155__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext155__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext155__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext155__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE12",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE12",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext155__xve_slm_write_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext155_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE13",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE13",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext155__xve_slm_write_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext155_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext156_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext156_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext156_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext156";
    metric_set->symbol_name = "Ext156";
    metric_set->hw_config_guid = "4c6764e2-9e79-4cb7-ae35-03459c6d06e4";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext156_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext156__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext156__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext156__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext156__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE14",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE14",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext156__xve_slm_write_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext156_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE15",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE15",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext156__xve_slm_write_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext156_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext157_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext157_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext157_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext157";
    metric_set->symbol_name = "Ext157";
    metric_set->hw_config_guid = "c148c5e1-7709-4fbe-ae06-1f23721141c9";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext157_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext157__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext157__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext157__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext157__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE16",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE16",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext157__xve_slm_write_message_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext157_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE16_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE17",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE17",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext157__xve_slm_write_message_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext157_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE17_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext158_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext158_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext158_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext158";
    metric_set->symbol_name = "Ext158";
    metric_set->hw_config_guid = "a733cb3b-6a08-44a2-b732-11e7ba701391";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext158_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext158__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext158__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext158__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext158__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE18",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE18",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext158__xve_slm_write_message_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext158_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE18_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE19",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE19",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext158__xve_slm_write_message_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext158_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext159_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext159_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext159_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext159";
    metric_set->symbol_name = "Ext159";
    metric_set->hw_config_guid = "15186c13-8523-470b-bda5-363a5b4e001a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext159_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext159__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext159__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext159__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext159__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE20",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE20",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext159__xve_slm_write_message_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext159_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE20_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE21",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE21",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext159__xve_slm_write_message_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext159_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE21_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext160_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext160_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext160_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext160";
    metric_set->symbol_name = "Ext160";
    metric_set->hw_config_guid = "df25a2c1-8375-4034-8ad9-f291c80a3f9c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext160_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext160__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext160__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext160__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext160__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE22",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE22",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext160__xve_slm_write_message_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext160_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE22_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE23",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE23",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext160__xve_slm_write_message_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext160_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext161_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext161_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext161_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext161";
    metric_set->symbol_name = "Ext161";
    metric_set->hw_config_guid = "97bb9d99-1be8-4add-a674-50795062f1a7";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext161_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext161__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext161__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext161__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext161__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE24",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE24",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext161__xve_slm_write_message_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext161_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE24_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE25",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE25",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext161__xve_slm_write_message_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext161_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE25_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext162_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext162_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext162_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext162";
    metric_set->symbol_name = "Ext162";
    metric_set->hw_config_guid = "725d052c-1ead-4fd5-96fc-68d7db607dc7";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext162_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext162__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext162__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext162__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext162__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE26",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE26",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext162__xve_slm_write_message_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext162_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE26_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE27",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE27",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext162__xve_slm_write_message_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext162_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext163_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext163_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext163_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext163";
    metric_set->symbol_name = "Ext163";
    metric_set->hw_config_guid = "63a891bb-dcce-41a0-8c54-cddd68cd298b";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext163_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext163__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext163__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext163__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext163__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE28",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE28",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext163__xve_slm_write_message_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext163_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE28_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE29",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE29",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext163__xve_slm_write_message_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext163_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE29_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext164_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext164_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext164_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext164";
    metric_set->symbol_name = "Ext164";
    metric_set->hw_config_guid = "0d6008ca-0cbb-4be9-a615-e9ecec99f5d7";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext164_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext164__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext164__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext164__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext164__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE30",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE30",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext164__xve_slm_write_message_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext164_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE30_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE31",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE31",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext164__xve_slm_write_message_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext164_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext165_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext165_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext165";
    metric_set->symbol_name = "Ext165";
    metric_set->hw_config_guid = "7df82e88-2ee2-4fbc-8adb-d727d7642c39";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext165_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext165__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext165__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext165__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext165__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE0",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext165__xve_slm_atomic_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext165_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext166_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext166_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext166";
    metric_set->symbol_name = "Ext166";
    metric_set->hw_config_guid = "3e04e13c-9dea-45d0-ae38-0596b159f871";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext166_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext166__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext166__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext166__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext166__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE1",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext166__xve_slm_atomic_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext166_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext167_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext167_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext167";
    metric_set->symbol_name = "Ext167";
    metric_set->hw_config_guid = "47678de2-1d55-41be-9fce-6f7d5e771f87";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext167_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext167__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext167__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext167__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext167__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE2",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext167__xve_slm_atomic_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext167_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext168_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext168_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext168";
    metric_set->symbol_name = "Ext168";
    metric_set->hw_config_guid = "0dbdebc2-4202-460e-941b-d3b4a321f450";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext168_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext168__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext168__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext168__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext168__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE3",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext168__xve_slm_atomic_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext168_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext169_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext169_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext169";
    metric_set->symbol_name = "Ext169";
    metric_set->hw_config_guid = "406d841d-d415-434e-94d4-5756af4a9e37";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext169_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext169__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext169__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext169__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext169__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE4",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext169__xve_slm_atomic_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext169_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext170_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext170_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext170";
    metric_set->symbol_name = "Ext170";
    metric_set->hw_config_guid = "3e3ce4f4-1ead-4705-8243-a7786c061089";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext170_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext170__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext170__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext170__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext170__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE5",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext170__xve_slm_atomic_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext170_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext171_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext171_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext171";
    metric_set->symbol_name = "Ext171";
    metric_set->hw_config_guid = "e9e8cc3e-2c88-4b2c-a8d2-67f00c9699a5";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext171_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext171__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext171__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext171__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext171__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE6",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext171__xve_slm_atomic_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext171_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext172_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext172_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext172";
    metric_set->symbol_name = "Ext172";
    metric_set->hw_config_guid = "23e25067-e274-4172-a380-e032c4d685d6";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext172_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext172__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext172__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext172__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext172__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE7",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext172__xve_slm_atomic_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext172_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext173_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext173_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext173";
    metric_set->symbol_name = "Ext173";
    metric_set->hw_config_guid = "21d3e3ca-2381-47d9-bf55-0aa699ebac4b";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext173_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext173__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext173__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext173__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext173__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE8",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE8",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext173__xve_slm_atomic_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext173_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE8_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext174_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext174_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext174";
    metric_set->symbol_name = "Ext174";
    metric_set->hw_config_guid = "0b4f4666-f7af-484e-8f18-68762db73ad7";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext174_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext174__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext174__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext174__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext174__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE9",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE9",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext174__xve_slm_atomic_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext174_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext175_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext175_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext175";
    metric_set->symbol_name = "Ext175";
    metric_set->hw_config_guid = "27c6aca7-31ed-477e-a48a-34fefb2a02a8";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext175_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext175__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext175__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext175__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext175__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE10",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE10",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext175__xve_slm_atomic_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext175_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE10_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext176_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext176_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext176";
    metric_set->symbol_name = "Ext176";
    metric_set->hw_config_guid = "813597c0-4e8c-408c-8410-e6e5ece2b810";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext176_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext176__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext176__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext176__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext176__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE11",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE11",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext176__xve_slm_atomic_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext176_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext177_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext177_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext177";
    metric_set->symbol_name = "Ext177";
    metric_set->hw_config_guid = "a31bccd0-3d2c-4697-8c8b-2e4c0920b30b";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext177_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext177__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext177__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext177__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext177__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE12",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE12",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext177__xve_slm_atomic_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext177_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE12_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext178_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext178_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext178";
    metric_set->symbol_name = "Ext178";
    metric_set->hw_config_guid = "d936d62e-18f5-4216-84a6-e419ae29b3c7";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext178_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext178__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext178__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext178__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext178__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE13",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE13",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext178__xve_slm_atomic_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext178_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext179_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext179_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext179";
    metric_set->symbol_name = "Ext179";
    metric_set->hw_config_guid = "49b08c39-b26e-42e8-99b7-f1be426862cb";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext179_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext179__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext179__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext179__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext179__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE14",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE14",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext179__xve_slm_atomic_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext179_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE14_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext180_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext180_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext180";
    metric_set->symbol_name = "Ext180";
    metric_set->hw_config_guid = "2c9db1da-1263-422b-9ae6-b2d59b5ec7b4";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext180_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext180__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext180__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext180__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext180__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE15",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE15",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext180__xve_slm_atomic_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext180_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext181_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext181_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext181";
    metric_set->symbol_name = "Ext181";
    metric_set->hw_config_guid = "135f67bb-5cc5-408c-a5aa-760f9df1a3c1";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext181_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext181__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext181__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext181__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext181__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE16",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE16",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext181__xve_slm_atomic_message_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext181_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE16_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext182_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext182_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext182";
    metric_set->symbol_name = "Ext182";
    metric_set->hw_config_guid = "c106cace-c1ea-4023-a288-f4b0a2487cc3";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext182_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext182__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext182__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext182__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext182__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE17",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE17",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext182__xve_slm_atomic_message_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext182_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE17_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext183_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext183_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext183";
    metric_set->symbol_name = "Ext183";
    metric_set->hw_config_guid = "4483d3ce-c377-4a00-8f10-7159c70fecd1";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext183_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext183__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext183__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext183__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext183__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE18",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE18",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext183__xve_slm_atomic_message_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext183_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE18_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext184_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext184_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext184";
    metric_set->symbol_name = "Ext184";
    metric_set->hw_config_guid = "eaef6bf8-dd2a-4a07-a948-d837765220ff";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext184_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext184__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext184__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext184__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext184__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE19",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE19",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext184__xve_slm_atomic_message_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext184_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext185_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext185_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext185";
    metric_set->symbol_name = "Ext185";
    metric_set->hw_config_guid = "00a90659-f144-4e89-b782-5dc13e3b3ca3";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext185_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext185__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext185__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext185__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext185__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE20",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE20",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext185__xve_slm_atomic_message_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext185_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE20_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext186_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext186_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext186";
    metric_set->symbol_name = "Ext186";
    metric_set->hw_config_guid = "b74242c4-91fb-4fed-a5bf-7154b99fa647";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext186_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext186__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext186__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext186__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext186__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE21",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE21",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext186__xve_slm_atomic_message_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext186_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE21_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext187_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext187_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext187";
    metric_set->symbol_name = "Ext187";
    metric_set->hw_config_guid = "14d62995-8763-403b-aa49-28c9f09f32c4";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext187_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext187__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext187__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext187__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext187__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE22",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE22",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext187__xve_slm_atomic_message_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext187_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE22_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext188_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext188_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext188";
    metric_set->symbol_name = "Ext188";
    metric_set->hw_config_guid = "1f8abc30-c7f6-469e-9a6c-1b6c62208c75";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext188_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext188__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext188__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext188__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext188__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE23",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE23",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext188__xve_slm_atomic_message_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext188_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext189_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext189_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext189";
    metric_set->symbol_name = "Ext189";
    metric_set->hw_config_guid = "b8d49514-56d9-4a63-b5a2-539f97739cf3";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext189_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext189__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext189__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext189__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext189__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE24",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE24",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext189__xve_slm_atomic_message_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext189_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE24_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext190_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext190_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext190";
    metric_set->symbol_name = "Ext190";
    metric_set->hw_config_guid = "1cec7b0a-c4c7-4a32-ae0b-9b809c84a7a0";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext190_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext190__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext190__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext190__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext190__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE25",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE25",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext190__xve_slm_atomic_message_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext190_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE25_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext191_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext191_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext191";
    metric_set->symbol_name = "Ext191";
    metric_set->hw_config_guid = "3c9f5268-8d6f-4f54-8f76-a5364a32509d";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext191_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext191__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext191__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext191__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext191__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE26",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE26",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext191__xve_slm_atomic_message_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext191_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE26_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext192_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext192_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext192";
    metric_set->symbol_name = "Ext192";
    metric_set->hw_config_guid = "fe743705-afe0-4964-8976-ef793e6730c3";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext192_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext192__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext192__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext192__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext192__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE27",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE27",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext192__xve_slm_atomic_message_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext192_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext193_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext193_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext193";
    metric_set->symbol_name = "Ext193";
    metric_set->hw_config_guid = "3764f231-efa0-46c8-8fd1-d7524f7d287d";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext193_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext193__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext193__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext193__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext193__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE28",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE28",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext193__xve_slm_atomic_message_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext193_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE28_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext194_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext194_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext194";
    metric_set->symbol_name = "Ext194";
    metric_set->hw_config_guid = "7ae1c3db-b806-43e8-a5cd-2f9fdbbbdf2e";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext194_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext194__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext194__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext194__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext194__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE29",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE29",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext194__xve_slm_atomic_message_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext194_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE29_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext195_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext195_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext195";
    metric_set->symbol_name = "Ext195";
    metric_set->hw_config_guid = "addc5fb2-b8e8-4aab-b696-c033136f0207";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext195_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext195__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext195__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext195__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext195__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE30",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE30",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext195__xve_slm_atomic_message_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext195_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE30_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext196_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext196_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext196";
    metric_set->symbol_name = "Ext196";
    metric_set->hw_config_guid = "b57b99a2-d4df-46f1-b851-a0ac6e5f728d";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext196_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext196__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext196__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext196__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext196__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE31",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE31",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext196__xve_slm_atomic_message_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext196_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext197_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext197_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext197_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext197";
    metric_set->symbol_name = "Ext197";
    metric_set->hw_config_guid = "bb509d13-b4b4-4d2e-844d-9f67591c66bd";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext197_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext197__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext197__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext197__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext197__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE0",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext197__xve_slm_fence_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext197_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE1",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext197__xve_slm_fence_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext197_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext198_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext198_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext198_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext198";
    metric_set->symbol_name = "Ext198";
    metric_set->hw_config_guid = "15e524f3-6392-401d-b3be-02b317cbd359";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext198_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext198__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext198__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext198__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext198__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE2",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext198__xve_slm_fence_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext198_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE3",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext198__xve_slm_fence_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext198_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext199_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext199_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext199_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext199";
    metric_set->symbol_name = "Ext199";
    metric_set->hw_config_guid = "f65fb347-b70a-486e-b1b5-a44da3da8b66";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext199_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext199__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext199__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext199__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext199__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE4",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext199__xve_slm_fence_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext199_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE5",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext199__xve_slm_fence_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext199_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext200_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext200_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext200_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext200";
    metric_set->symbol_name = "Ext200";
    metric_set->hw_config_guid = "570e0476-84a4-42a2-8022-38fecca851ad";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext200_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext200__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext200__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext200__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext200__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE6",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext200__xve_slm_fence_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext200_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE7",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext200__xve_slm_fence_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext200_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext201_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext201_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext201_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext201";
    metric_set->symbol_name = "Ext201";
    metric_set->hw_config_guid = "4d7b3d3e-cafe-41f8-bb69-06d3a5d87305";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext201_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext201__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext201__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext201__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext201__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE8",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE8",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext201__xve_slm_fence_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext201_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE9",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE9",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext201__xve_slm_fence_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext201_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext202_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext202_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext202_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext202";
    metric_set->symbol_name = "Ext202";
    metric_set->hw_config_guid = "356bc819-2d0a-40c6-afcf-531107e99c87";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext202_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext202__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext202__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext202__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext202__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE10",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE10",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext202__xve_slm_fence_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext202_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE11",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE11",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext202__xve_slm_fence_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext202_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext203_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext203_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext203_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext203";
    metric_set->symbol_name = "Ext203";
    metric_set->hw_config_guid = "6a08a183-8d09-4e98-a198-b72edf387ceb";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext203_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext203__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext203__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext203__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext203__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE12",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE12",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext203__xve_slm_fence_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext203_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE13",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE13",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext203__xve_slm_fence_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext203_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext204_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext204_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext204_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext204";
    metric_set->symbol_name = "Ext204";
    metric_set->hw_config_guid = "7afa64c7-c65b-4671-b6fc-c99a9b7fe6d4";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext204_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext204__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext204__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext204__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext204__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE14",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE14",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext204__xve_slm_fence_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext204_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE15",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE15",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext204__xve_slm_fence_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext204_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext205_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext205_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext205_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext205";
    metric_set->symbol_name = "Ext205";
    metric_set->hw_config_guid = "92562fac-284e-4612-b25e-378432c85ad3";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext205_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext205__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext205__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext205__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext205__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE16",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE16",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext205__xve_slm_fence_message_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext205_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE16_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE17",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE17",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext205__xve_slm_fence_message_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext205_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE17_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext206_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext206_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext206_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext206";
    metric_set->symbol_name = "Ext206";
    metric_set->hw_config_guid = "eeeb0ea8-ea9a-42e5-b793-e9143baf6425";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext206_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext206__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext206__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext206__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext206__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE18",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE18",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext206__xve_slm_fence_message_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext206_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE18_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE19",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE19",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext206__xve_slm_fence_message_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext206_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext207_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext207_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext207_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext207";
    metric_set->symbol_name = "Ext207";
    metric_set->hw_config_guid = "de748c4d-cf66-43e6-921e-d9d13b47f817";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext207_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext207__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext207__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext207__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext207__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE20",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE20",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext207__xve_slm_fence_message_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext207_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE20_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE21",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE21",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext207__xve_slm_fence_message_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext207_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE21_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext208_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext208_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext208_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext208";
    metric_set->symbol_name = "Ext208";
    metric_set->hw_config_guid = "50c6035f-68f0-45a8-b316-1dcda3d00e9a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext208_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext208__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext208__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext208__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext208__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE22",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE22",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext208__xve_slm_fence_message_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext208_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE22_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE23",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE23",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext208__xve_slm_fence_message_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext208_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext209_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext209_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext209_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext209";
    metric_set->symbol_name = "Ext209";
    metric_set->hw_config_guid = "0c6c792b-9f14-44c1-896d-3c122c75ab69";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext209_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext209__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext209__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext209__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext209__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE24",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE24",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext209__xve_slm_fence_message_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext209_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE24_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE25",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE25",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext209__xve_slm_fence_message_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext209_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE25_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext210_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext210_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext210_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext210";
    metric_set->symbol_name = "Ext210";
    metric_set->hw_config_guid = "a931106d-e624-4d08-8fda-ecaead88f576";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext210_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext210__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext210__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext210__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext210__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE26",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE26",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext210__xve_slm_fence_message_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext210_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE26_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE27",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE27",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext210__xve_slm_fence_message_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext210_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext211_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext211_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext211_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext211";
    metric_set->symbol_name = "Ext211";
    metric_set->hw_config_guid = "baa9de2f-f71f-4824-95f0-5fc9d96c7fc5";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext211_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext211__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext211__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext211__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext211__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE28",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE28",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext211__xve_slm_fence_message_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext211_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE28_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE29",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE29",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext211__xve_slm_fence_message_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext211_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE29_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext212_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext212_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext212_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext212";
    metric_set->symbol_name = "Ext212";
    metric_set->hw_config_guid = "bbbd7113-221b-4fca-aae2-5c8a259cbc48";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext212_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext212__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext212__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext212__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext212__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE30",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE30",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext212__xve_slm_fence_message_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext212_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE30_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE31",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE31",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext212__xve_slm_fence_message_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext212_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext213_LOAD_STORE_CACHE_ACCESS_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext213_LOAD_STORE_CACHE_ACCESS_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext213_LOAD_STORE_CACHE_ACCESS_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext213_LOAD_STORE_CACHE_ACCESS_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext213_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext213";
    metric_set->symbol_name = "Ext213";
    metric_set->hw_config_guid = "6ca2babc-de4f-469e-ab01-d291e28d63e7";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext213_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext213__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext213__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext213__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext213__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE0",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext213__load_store_cache_access_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext213_LOAD_STORE_CACHE_ACCESS_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE1",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext213__load_store_cache_access_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext213_LOAD_STORE_CACHE_ACCESS_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE2",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext213__load_store_cache_access_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext213_LOAD_STORE_CACHE_ACCESS_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE3",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext213__load_store_cache_access_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext213_LOAD_STORE_CACHE_ACCESS_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext214_LOAD_STORE_CACHE_ACCESS_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext214_LOAD_STORE_CACHE_ACCESS_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext214_LOAD_STORE_CACHE_ACCESS_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext214_LOAD_STORE_CACHE_ACCESS_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext214_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext214";
    metric_set->symbol_name = "Ext214";
    metric_set->hw_config_guid = "74a2399e-2681-4433-8878-4dfe42324fcc";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext214_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext214__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext214__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext214__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext214__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE4",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext214__load_store_cache_access_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext214_LOAD_STORE_CACHE_ACCESS_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE5",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext214__load_store_cache_access_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext214_LOAD_STORE_CACHE_ACCESS_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE6",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext214__load_store_cache_access_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext214_LOAD_STORE_CACHE_ACCESS_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE7",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext214__load_store_cache_access_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext214_LOAD_STORE_CACHE_ACCESS_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext215_LOAD_STORE_CACHE_ACCESS_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext215_LOAD_STORE_CACHE_ACCESS_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext215_LOAD_STORE_CACHE_ACCESS_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext215_LOAD_STORE_CACHE_ACCESS_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext215_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext215";
    metric_set->symbol_name = "Ext215";
    metric_set->hw_config_guid = "401e46da-ef68-4a45-a2e7-7daa5b376228";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext215_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext215__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext215__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext215__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext215__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE10",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE10",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext215__load_store_cache_access_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext215_LOAD_STORE_CACHE_ACCESS_XECORE10_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE11",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE11",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext215__load_store_cache_access_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext215_LOAD_STORE_CACHE_ACCESS_XECORE11_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE8",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE8",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext215__load_store_cache_access_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext215_LOAD_STORE_CACHE_ACCESS_XECORE8_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE9",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE9",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext215__load_store_cache_access_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext215_LOAD_STORE_CACHE_ACCESS_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext216_LOAD_STORE_CACHE_ACCESS_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext216_LOAD_STORE_CACHE_ACCESS_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext216_LOAD_STORE_CACHE_ACCESS_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext216_LOAD_STORE_CACHE_ACCESS_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext216_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext216";
    metric_set->symbol_name = "Ext216";
    metric_set->hw_config_guid = "b7ae12df-db7e-4936-b449-c52f80ee5d29";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext216_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext216__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext216__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext216__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext216__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE12",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE12",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext216__load_store_cache_access_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext216_LOAD_STORE_CACHE_ACCESS_XECORE12_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE13",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE13",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext216__load_store_cache_access_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext216_LOAD_STORE_CACHE_ACCESS_XECORE13_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE14",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE14",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext216__load_store_cache_access_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext216_LOAD_STORE_CACHE_ACCESS_XECORE14_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE15",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE15",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext216__load_store_cache_access_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext216_LOAD_STORE_CACHE_ACCESS_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext217_LOAD_STORE_CACHE_ACCESS_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext217_LOAD_STORE_CACHE_ACCESS_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext217_LOAD_STORE_CACHE_ACCESS_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext217_LOAD_STORE_CACHE_ACCESS_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext217_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext217";
    metric_set->symbol_name = "Ext217";
    metric_set->hw_config_guid = "c69966b7-9ef1-430a-8936-0976458b2291";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext217_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext217__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext217__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext217__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext217__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE16",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE16",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext217__load_store_cache_access_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext217_LOAD_STORE_CACHE_ACCESS_XECORE16_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE17",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE17",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext217__load_store_cache_access_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext217_LOAD_STORE_CACHE_ACCESS_XECORE17_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE18",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE18",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext217__load_store_cache_access_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext217_LOAD_STORE_CACHE_ACCESS_XECORE18_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE19",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE19",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext217__load_store_cache_access_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext217_LOAD_STORE_CACHE_ACCESS_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext218_LOAD_STORE_CACHE_ACCESS_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext218_LOAD_STORE_CACHE_ACCESS_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext218_LOAD_STORE_CACHE_ACCESS_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext218_LOAD_STORE_CACHE_ACCESS_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext218_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext218";
    metric_set->symbol_name = "Ext218";
    metric_set->hw_config_guid = "01cb7b35-7ed2-43b5-b046-efde9201ca35";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext218_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext218__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext218__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext218__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext218__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE20",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE20",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext218__load_store_cache_access_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext218_LOAD_STORE_CACHE_ACCESS_XECORE20_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE21",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE21",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext218__load_store_cache_access_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext218_LOAD_STORE_CACHE_ACCESS_XECORE21_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE22",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE22",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext218__load_store_cache_access_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext218_LOAD_STORE_CACHE_ACCESS_XECORE22_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE23",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE23",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext218__load_store_cache_access_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext218_LOAD_STORE_CACHE_ACCESS_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext219_LOAD_STORE_CACHE_ACCESS_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext219_LOAD_STORE_CACHE_ACCESS_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext219_LOAD_STORE_CACHE_ACCESS_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext219_LOAD_STORE_CACHE_ACCESS_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext219_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext219";
    metric_set->symbol_name = "Ext219";
    metric_set->hw_config_guid = "c614285f-3ef0-43b8-9b09-1b13adbe2e8f";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext219_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext219__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext219__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext219__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext219__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE24",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE24",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext219__load_store_cache_access_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext219_LOAD_STORE_CACHE_ACCESS_XECORE24_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE25",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE25",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext219__load_store_cache_access_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext219_LOAD_STORE_CACHE_ACCESS_XECORE25_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE26",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE26",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext219__load_store_cache_access_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext219_LOAD_STORE_CACHE_ACCESS_XECORE26_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE27",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE27",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext219__load_store_cache_access_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext219_LOAD_STORE_CACHE_ACCESS_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext220_LOAD_STORE_CACHE_ACCESS_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext220_LOAD_STORE_CACHE_ACCESS_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext220_LOAD_STORE_CACHE_ACCESS_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext220_LOAD_STORE_CACHE_ACCESS_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext220_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext220";
    metric_set->symbol_name = "Ext220";
    metric_set->hw_config_guid = "4bdb50d9-dfc5-42d2-86aa-d8592e876856";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext220_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext220__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext220__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext220__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext220__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE28",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE28",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext220__load_store_cache_access_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext220_LOAD_STORE_CACHE_ACCESS_XECORE28_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE29",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE29",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext220__load_store_cache_access_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext220_LOAD_STORE_CACHE_ACCESS_XECORE29_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE30",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE30",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext220__load_store_cache_access_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext220_LOAD_STORE_CACHE_ACCESS_XECORE30_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE31",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE31",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext220__load_store_cache_access_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext220_LOAD_STORE_CACHE_ACCESS_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext221_LOAD_STORE_CACHE_HIT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext221_LOAD_STORE_CACHE_HIT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext221_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext221";
    metric_set->symbol_name = "Ext221";
    metric_set->hw_config_guid = "50714f9c-2bb3-459c-b546-8a374589bf9e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext221_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext221__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext221__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext221__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext221__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE0",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext221__load_store_cache_hit_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext221_LOAD_STORE_CACHE_HIT_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE1",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext221__load_store_cache_hit_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext221_LOAD_STORE_CACHE_HIT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext222_LOAD_STORE_CACHE_HIT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext222_LOAD_STORE_CACHE_HIT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext222_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext222";
    metric_set->symbol_name = "Ext222";
    metric_set->hw_config_guid = "fcfd6090-d189-4cd7-9c85-3a5acc193e7f";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext222_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext222__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext222__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext222__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext222__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE2",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext222__load_store_cache_hit_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext222_LOAD_STORE_CACHE_HIT_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE3",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext222__load_store_cache_hit_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext222_LOAD_STORE_CACHE_HIT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext223_LOAD_STORE_CACHE_HIT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext223_LOAD_STORE_CACHE_HIT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext223_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext223";
    metric_set->symbol_name = "Ext223";
    metric_set->hw_config_guid = "4ed943c0-2d87-4749-876f-811e1b39e607";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext223_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext223__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext223__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext223__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext223__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE4",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext223__load_store_cache_hit_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext223_LOAD_STORE_CACHE_HIT_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE5",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext223__load_store_cache_hit_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext223_LOAD_STORE_CACHE_HIT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext224_LOAD_STORE_CACHE_HIT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext224_LOAD_STORE_CACHE_HIT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext224_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext224";
    metric_set->symbol_name = "Ext224";
    metric_set->hw_config_guid = "2b3af12b-71c7-4f36-bb8f-049547bf5c2d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext224_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext224__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext224__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext224__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext224__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE6",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext224__load_store_cache_hit_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext224_LOAD_STORE_CACHE_HIT_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE7",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext224__load_store_cache_hit_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext224_LOAD_STORE_CACHE_HIT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext225_LOAD_STORE_CACHE_HIT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext225_LOAD_STORE_CACHE_HIT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext225_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext225";
    metric_set->symbol_name = "Ext225";
    metric_set->hw_config_guid = "1dde6c6e-a7aa-4f8f-aaf4-3b26dd6bca69";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext225_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext225__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext225__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext225__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext225__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE8",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE8",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext225__load_store_cache_hit_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext225_LOAD_STORE_CACHE_HIT_XECORE8_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE9",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE9",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext225__load_store_cache_hit_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext225_LOAD_STORE_CACHE_HIT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext226_LOAD_STORE_CACHE_HIT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext226_LOAD_STORE_CACHE_HIT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext226_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext226";
    metric_set->symbol_name = "Ext226";
    metric_set->hw_config_guid = "d9db7f79-0da3-4ab3-8b28-8dd70416656f";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext226_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext226__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext226__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext226__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext226__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE10",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE10",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext226__load_store_cache_hit_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext226_LOAD_STORE_CACHE_HIT_XECORE10_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE11",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE11",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext226__load_store_cache_hit_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext226_LOAD_STORE_CACHE_HIT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext227_LOAD_STORE_CACHE_HIT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext227_LOAD_STORE_CACHE_HIT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext227_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext227";
    metric_set->symbol_name = "Ext227";
    metric_set->hw_config_guid = "d98e7c96-ff33-493f-9e6e-0e5c2ff4d3b3";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext227_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext227__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext227__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext227__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext227__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE12",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE12",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext227__load_store_cache_hit_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext227_LOAD_STORE_CACHE_HIT_XECORE12_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE13",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE13",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext227__load_store_cache_hit_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext227_LOAD_STORE_CACHE_HIT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext228_LOAD_STORE_CACHE_HIT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext228_LOAD_STORE_CACHE_HIT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext228_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext228";
    metric_set->symbol_name = "Ext228";
    metric_set->hw_config_guid = "ee084440-5ff3-4348-98aa-69f9bc50bc13";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext228_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext228__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext228__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext228__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext228__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE14",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE14",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext228__load_store_cache_hit_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext228_LOAD_STORE_CACHE_HIT_XECORE14_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE15",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE15",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext228__load_store_cache_hit_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext228_LOAD_STORE_CACHE_HIT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext229_LOAD_STORE_CACHE_HIT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext229_LOAD_STORE_CACHE_HIT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext229_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext229";
    metric_set->symbol_name = "Ext229";
    metric_set->hw_config_guid = "8591ba5f-8306-4275-92a8-d9059ad66ed0";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext229_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext229__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext229__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext229__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext229__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE16",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE16",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext229__load_store_cache_hit_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext229_LOAD_STORE_CACHE_HIT_XECORE16_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE17",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE17",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext229__load_store_cache_hit_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext229_LOAD_STORE_CACHE_HIT_XECORE17_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext230_LOAD_STORE_CACHE_HIT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext230_LOAD_STORE_CACHE_HIT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext230_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext230";
    metric_set->symbol_name = "Ext230";
    metric_set->hw_config_guid = "00e97ab6-80e8-4fb7-8735-d2c9fd2e57e0";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext230_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext230__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext230__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext230__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext230__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE18",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE18",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext230__load_store_cache_hit_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext230_LOAD_STORE_CACHE_HIT_XECORE18_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE19",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE19",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext230__load_store_cache_hit_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext230_LOAD_STORE_CACHE_HIT_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext231_LOAD_STORE_CACHE_HIT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext231_LOAD_STORE_CACHE_HIT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext231_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext231";
    metric_set->symbol_name = "Ext231";
    metric_set->hw_config_guid = "8843165e-fc6d-4b1a-8356-201b7b0bdb25";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext231_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext231__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext231__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext231__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext231__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE20",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE20",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext231__load_store_cache_hit_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext231_LOAD_STORE_CACHE_HIT_XECORE20_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE21",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE21",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext231__load_store_cache_hit_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext231_LOAD_STORE_CACHE_HIT_XECORE21_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext232_LOAD_STORE_CACHE_HIT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext232_LOAD_STORE_CACHE_HIT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext232_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext232";
    metric_set->symbol_name = "Ext232";
    metric_set->hw_config_guid = "964b5b29-6acf-4be2-b50b-030c7a8c3fc8";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext232_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext232__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext232__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext232__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext232__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE22",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE22",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext232__load_store_cache_hit_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext232_LOAD_STORE_CACHE_HIT_XECORE22_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE23",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE23",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext232__load_store_cache_hit_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext232_LOAD_STORE_CACHE_HIT_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext233_LOAD_STORE_CACHE_HIT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext233_LOAD_STORE_CACHE_HIT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext233_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext233";
    metric_set->symbol_name = "Ext233";
    metric_set->hw_config_guid = "796a2acb-6ddb-4567-9c5e-ad1b18f74271";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext233_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext233__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext233__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext233__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext233__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE24",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE24",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext233__load_store_cache_hit_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext233_LOAD_STORE_CACHE_HIT_XECORE24_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE25",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE25",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext233__load_store_cache_hit_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext233_LOAD_STORE_CACHE_HIT_XECORE25_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext234_LOAD_STORE_CACHE_HIT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext234_LOAD_STORE_CACHE_HIT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext234_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext234";
    metric_set->symbol_name = "Ext234";
    metric_set->hw_config_guid = "8c5e4033-e50a-4f55-a17f-2fca9ac26074";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext234_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext234__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext234__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext234__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext234__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE26",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE26",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext234__load_store_cache_hit_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext234_LOAD_STORE_CACHE_HIT_XECORE26_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE27",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE27",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext234__load_store_cache_hit_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext234_LOAD_STORE_CACHE_HIT_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext235_LOAD_STORE_CACHE_HIT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext235_LOAD_STORE_CACHE_HIT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext235_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext235";
    metric_set->symbol_name = "Ext235";
    metric_set->hw_config_guid = "6717aa54-589d-4ccc-b40a-a2fb3dd9e11a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext235_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext235__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext235__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext235__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext235__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE28",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE28",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext235__load_store_cache_hit_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext235_LOAD_STORE_CACHE_HIT_XECORE28_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE29",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE29",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext235__load_store_cache_hit_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext235_LOAD_STORE_CACHE_HIT_XECORE29_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext236_LOAD_STORE_CACHE_HIT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext236_LOAD_STORE_CACHE_HIT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext236_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext236";
    metric_set->symbol_name = "Ext236";
    metric_set->hw_config_guid = "4e1d6474-b268-4c2e-9437-208ee88b8a46";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext236_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext236__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext236__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext236__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext236__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE30",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE30",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext236__load_store_cache_hit_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext236_LOAD_STORE_CACHE_HIT_XECORE30_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE31",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE31",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext236__load_store_cache_hit_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext236_LOAD_STORE_CACHE_HIT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext237_LOAD_STORE_CACHE_L3_READ_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext237_LOAD_STORE_CACHE_L3_READ_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext237_LOAD_STORE_CACHE_L3_READ_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext237_LOAD_STORE_CACHE_L3_READ_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext237_LOAD_STORE_CACHE_L3_READ_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext237_LOAD_STORE_CACHE_L3_READ_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext237_LOAD_STORE_CACHE_L3_READ_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext237_LOAD_STORE_CACHE_L3_READ_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext237_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext237";
    metric_set->symbol_name = "Ext237";
    metric_set->hw_config_guid = "88f46503-19d1-42d1-be21-a3655e1b0136";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext237_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext237__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext237__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext237__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext237__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE0",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext237__load_store_cache_l3_read_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext237_LOAD_STORE_CACHE_L3_READ_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE1",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext237__load_store_cache_l3_read_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext237_LOAD_STORE_CACHE_L3_READ_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE2",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext237__load_store_cache_l3_read_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext237_LOAD_STORE_CACHE_L3_READ_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE3",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext237__load_store_cache_l3_read_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext237_LOAD_STORE_CACHE_L3_READ_XECORE3_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE4",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext237__load_store_cache_l3_read_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext237_LOAD_STORE_CACHE_L3_READ_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE5",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext237__load_store_cache_l3_read_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext237_LOAD_STORE_CACHE_L3_READ_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE6",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext237__load_store_cache_l3_read_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext237_LOAD_STORE_CACHE_L3_READ_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE7",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext237__load_store_cache_l3_read_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext237_LOAD_STORE_CACHE_L3_READ_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext238_LOAD_STORE_CACHE_L3_READ_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext238_LOAD_STORE_CACHE_L3_READ_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext238_LOAD_STORE_CACHE_L3_READ_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext238_LOAD_STORE_CACHE_L3_READ_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext238_LOAD_STORE_CACHE_L3_READ_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext238_LOAD_STORE_CACHE_L3_READ_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext238_LOAD_STORE_CACHE_L3_READ_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext238_LOAD_STORE_CACHE_L3_READ_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext238_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext238";
    metric_set->symbol_name = "Ext238";
    metric_set->hw_config_guid = "5da6f145-39c5-44cc-8329-0998439ee9c5";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext238_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext238__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext238__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext238__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext238__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE10",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE10",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext238__load_store_cache_l3_read_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext238_LOAD_STORE_CACHE_L3_READ_XECORE10_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE11",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE11",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext238__load_store_cache_l3_read_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext238_LOAD_STORE_CACHE_L3_READ_XECORE11_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE12",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE12",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext238__load_store_cache_l3_read_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext238_LOAD_STORE_CACHE_L3_READ_XECORE12_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE13",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE13",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext238__load_store_cache_l3_read_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext238_LOAD_STORE_CACHE_L3_READ_XECORE13_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE14",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE14",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext238__load_store_cache_l3_read_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext238_LOAD_STORE_CACHE_L3_READ_XECORE14_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE15",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE15",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext238__load_store_cache_l3_read_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext238_LOAD_STORE_CACHE_L3_READ_XECORE15_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE8",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE8",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext238__load_store_cache_l3_read_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext238_LOAD_STORE_CACHE_L3_READ_XECORE8_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE9",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE9",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext238__load_store_cache_l3_read_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext238_LOAD_STORE_CACHE_L3_READ_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext239_LOAD_STORE_CACHE_L3_READ_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext239_LOAD_STORE_CACHE_L3_READ_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext239_LOAD_STORE_CACHE_L3_READ_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext239_LOAD_STORE_CACHE_L3_READ_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext239_LOAD_STORE_CACHE_L3_READ_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext239_LOAD_STORE_CACHE_L3_READ_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext239_LOAD_STORE_CACHE_L3_READ_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext239_LOAD_STORE_CACHE_L3_READ_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext239_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext239";
    metric_set->symbol_name = "Ext239";
    metric_set->hw_config_guid = "4543c6ec-412e-4dee-b121-a3b02275a132";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext239_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext239__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext239__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext239__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext239__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE16",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE16",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext239__load_store_cache_l3_read_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext239_LOAD_STORE_CACHE_L3_READ_XECORE16_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE17",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE17",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext239__load_store_cache_l3_read_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext239_LOAD_STORE_CACHE_L3_READ_XECORE17_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE18",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE18",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext239__load_store_cache_l3_read_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext239_LOAD_STORE_CACHE_L3_READ_XECORE18_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE19",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE19",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext239__load_store_cache_l3_read_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext239_LOAD_STORE_CACHE_L3_READ_XECORE19_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE20",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE20",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext239__load_store_cache_l3_read_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext239_LOAD_STORE_CACHE_L3_READ_XECORE20_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE21",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE21",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext239__load_store_cache_l3_read_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext239_LOAD_STORE_CACHE_L3_READ_XECORE21_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE22",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE22",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext239__load_store_cache_l3_read_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext239_LOAD_STORE_CACHE_L3_READ_XECORE22_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE23",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE23",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext239__load_store_cache_l3_read_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext239_LOAD_STORE_CACHE_L3_READ_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext240_LOAD_STORE_CACHE_L3_READ_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext240_LOAD_STORE_CACHE_L3_READ_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext240_LOAD_STORE_CACHE_L3_READ_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext240_LOAD_STORE_CACHE_L3_READ_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext240_LOAD_STORE_CACHE_L3_READ_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext240_LOAD_STORE_CACHE_L3_READ_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext240_LOAD_STORE_CACHE_L3_READ_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext240_LOAD_STORE_CACHE_L3_READ_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext240_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext240";
    metric_set->symbol_name = "Ext240";
    metric_set->hw_config_guid = "e6b031df-b3fe-4fd4-97c3-7c26f28dac6f";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext240_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext240__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext240__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext240__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext240__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE24",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE24",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext240__load_store_cache_l3_read_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext240_LOAD_STORE_CACHE_L3_READ_XECORE24_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE25",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE25",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext240__load_store_cache_l3_read_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext240_LOAD_STORE_CACHE_L3_READ_XECORE25_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE26",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE26",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext240__load_store_cache_l3_read_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext240_LOAD_STORE_CACHE_L3_READ_XECORE26_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE27",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE27",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext240__load_store_cache_l3_read_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext240_LOAD_STORE_CACHE_L3_READ_XECORE27_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE28",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE28",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext240__load_store_cache_l3_read_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext240_LOAD_STORE_CACHE_L3_READ_XECORE28_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE29",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE29",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext240__load_store_cache_l3_read_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext240_LOAD_STORE_CACHE_L3_READ_XECORE29_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE30",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE30",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext240__load_store_cache_l3_read_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext240_LOAD_STORE_CACHE_L3_READ_XECORE30_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE31",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE31",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext240__load_store_cache_l3_read_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext240_LOAD_STORE_CACHE_L3_READ_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext241_LOAD_STORE_CACHE_L3_WRITE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext241_LOAD_STORE_CACHE_L3_WRITE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext241_LOAD_STORE_CACHE_L3_WRITE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext241_LOAD_STORE_CACHE_L3_WRITE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext241_LOAD_STORE_CACHE_L3_WRITE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext241_LOAD_STORE_CACHE_L3_WRITE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext241_LOAD_STORE_CACHE_L3_WRITE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext241_LOAD_STORE_CACHE_L3_WRITE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext241_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext241";
    metric_set->symbol_name = "Ext241";
    metric_set->hw_config_guid = "4ab6ae4f-59e0-4dee-b907-026737066065";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext241_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext241__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext241__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext241__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext241__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE0",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext241__load_store_cache_l3_write_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext241_LOAD_STORE_CACHE_L3_WRITE_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE1",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext241__load_store_cache_l3_write_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext241_LOAD_STORE_CACHE_L3_WRITE_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE2",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext241__load_store_cache_l3_write_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext241_LOAD_STORE_CACHE_L3_WRITE_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE3",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext241__load_store_cache_l3_write_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext241_LOAD_STORE_CACHE_L3_WRITE_XECORE3_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE4",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext241__load_store_cache_l3_write_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext241_LOAD_STORE_CACHE_L3_WRITE_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE5",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext241__load_store_cache_l3_write_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext241_LOAD_STORE_CACHE_L3_WRITE_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE6",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext241__load_store_cache_l3_write_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext241_LOAD_STORE_CACHE_L3_WRITE_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE7",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext241__load_store_cache_l3_write_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext241_LOAD_STORE_CACHE_L3_WRITE_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext242_LOAD_STORE_CACHE_L3_WRITE_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext242_LOAD_STORE_CACHE_L3_WRITE_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext242_LOAD_STORE_CACHE_L3_WRITE_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext242_LOAD_STORE_CACHE_L3_WRITE_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext242_LOAD_STORE_CACHE_L3_WRITE_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext242_LOAD_STORE_CACHE_L3_WRITE_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext242_LOAD_STORE_CACHE_L3_WRITE_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext242_LOAD_STORE_CACHE_L3_WRITE_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext242_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext242";
    metric_set->symbol_name = "Ext242";
    metric_set->hw_config_guid = "db802a4a-11cd-43aa-8baa-3b951ed19672";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext242_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext242__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext242__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext242__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext242__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE10",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE10",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext242__load_store_cache_l3_write_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext242_LOAD_STORE_CACHE_L3_WRITE_XECORE10_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE11",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE11",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext242__load_store_cache_l3_write_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext242_LOAD_STORE_CACHE_L3_WRITE_XECORE11_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE12",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE12",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext242__load_store_cache_l3_write_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext242_LOAD_STORE_CACHE_L3_WRITE_XECORE12_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE13",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE13",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext242__load_store_cache_l3_write_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext242_LOAD_STORE_CACHE_L3_WRITE_XECORE13_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE14",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE14",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext242__load_store_cache_l3_write_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext242_LOAD_STORE_CACHE_L3_WRITE_XECORE14_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE15",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE15",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext242__load_store_cache_l3_write_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext242_LOAD_STORE_CACHE_L3_WRITE_XECORE15_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE8",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE8",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext242__load_store_cache_l3_write_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext242_LOAD_STORE_CACHE_L3_WRITE_XECORE8_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE9",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE9",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext242__load_store_cache_l3_write_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext242_LOAD_STORE_CACHE_L3_WRITE_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext243_LOAD_STORE_CACHE_L3_WRITE_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext243_LOAD_STORE_CACHE_L3_WRITE_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext243_LOAD_STORE_CACHE_L3_WRITE_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext243_LOAD_STORE_CACHE_L3_WRITE_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext243_LOAD_STORE_CACHE_L3_WRITE_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext243_LOAD_STORE_CACHE_L3_WRITE_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext243_LOAD_STORE_CACHE_L3_WRITE_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext243_LOAD_STORE_CACHE_L3_WRITE_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext243_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext243";
    metric_set->symbol_name = "Ext243";
    metric_set->hw_config_guid = "e7f929f5-f382-4bb2-b32b-e808e816a751";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext243_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext243__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext243__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext243__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext243__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE16",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE16",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext243__load_store_cache_l3_write_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext243_LOAD_STORE_CACHE_L3_WRITE_XECORE16_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE17",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE17",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext243__load_store_cache_l3_write_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext243_LOAD_STORE_CACHE_L3_WRITE_XECORE17_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE18",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE18",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext243__load_store_cache_l3_write_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext243_LOAD_STORE_CACHE_L3_WRITE_XECORE18_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE19",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE19",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext243__load_store_cache_l3_write_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext243_LOAD_STORE_CACHE_L3_WRITE_XECORE19_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE20",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE20",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext243__load_store_cache_l3_write_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext243_LOAD_STORE_CACHE_L3_WRITE_XECORE20_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE21",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE21",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext243__load_store_cache_l3_write_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext243_LOAD_STORE_CACHE_L3_WRITE_XECORE21_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE22",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE22",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext243__load_store_cache_l3_write_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext243_LOAD_STORE_CACHE_L3_WRITE_XECORE22_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE23",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE23",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext243__load_store_cache_l3_write_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext243_LOAD_STORE_CACHE_L3_WRITE_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext244_LOAD_STORE_CACHE_L3_WRITE_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext244_LOAD_STORE_CACHE_L3_WRITE_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext244_LOAD_STORE_CACHE_L3_WRITE_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext244_LOAD_STORE_CACHE_L3_WRITE_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext244_LOAD_STORE_CACHE_L3_WRITE_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext244_LOAD_STORE_CACHE_L3_WRITE_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext244_LOAD_STORE_CACHE_L3_WRITE_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext244_LOAD_STORE_CACHE_L3_WRITE_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext244_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext244";
    metric_set->symbol_name = "Ext244";
    metric_set->hw_config_guid = "81a25cda-94c8-4b9a-b9e5-38994ed22ab0";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext244_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext244__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext244__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext244__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext244__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE24",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE24",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext244__load_store_cache_l3_write_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext244_LOAD_STORE_CACHE_L3_WRITE_XECORE24_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE25",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE25",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext244__load_store_cache_l3_write_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext244_LOAD_STORE_CACHE_L3_WRITE_XECORE25_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE26",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE26",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext244__load_store_cache_l3_write_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext244_LOAD_STORE_CACHE_L3_WRITE_XECORE26_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE27",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE27",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext244__load_store_cache_l3_write_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext244_LOAD_STORE_CACHE_L3_WRITE_XECORE27_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE28",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE28",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext244__load_store_cache_l3_write_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext244_LOAD_STORE_CACHE_L3_WRITE_XECORE28_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE29",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE29",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext244__load_store_cache_l3_write_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext244_LOAD_STORE_CACHE_L3_WRITE_XECORE29_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE30",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE30",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext244__load_store_cache_l3_write_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext244_LOAD_STORE_CACHE_L3_WRITE_XECORE30_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE31",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE31",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext244__load_store_cache_l3_write_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext244_LOAD_STORE_CACHE_L3_WRITE_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext245_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext245_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext245_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext245_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext245_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext245";
    metric_set->symbol_name = "Ext245";
    metric_set->hw_config_guid = "6a234e4e-a4a9-483c-b0b1-f6be43dfb64c";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext245_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext245__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext245__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext245__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext245__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE0",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext245__load_store_cache_partial_write_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext245_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE1",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext245__load_store_cache_partial_write_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext245_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE2",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext245__load_store_cache_partial_write_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext245_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE3",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext245__load_store_cache_partial_write_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext245_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext246_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext246_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext246_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext246_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext246_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext246";
    metric_set->symbol_name = "Ext246";
    metric_set->hw_config_guid = "94757ea4-0b0b-401f-93a2-b119ed4f5204";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext246_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext246__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext246__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext246__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext246__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE4",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext246__load_store_cache_partial_write_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext246_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE5",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext246__load_store_cache_partial_write_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext246_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE6",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext246__load_store_cache_partial_write_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext246_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE7",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext246__load_store_cache_partial_write_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext246_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext247_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext247_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext247_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext247_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext247_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext247";
    metric_set->symbol_name = "Ext247";
    metric_set->hw_config_guid = "b90ea8da-5965-4457-97aa-49a688fb0d39";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext247_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext247__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext247__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext247__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext247__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE10",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE10",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext247__load_store_cache_partial_write_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext247_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE10_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE11",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE11",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext247__load_store_cache_partial_write_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext247_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE11_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE8",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE8",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext247__load_store_cache_partial_write_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext247_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE8_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE9",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE9",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext247__load_store_cache_partial_write_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext247_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext248_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext248_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext248_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext248_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext248_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext248";
    metric_set->symbol_name = "Ext248";
    metric_set->hw_config_guid = "74996160-a911-4eb8-9db3-e83969d92a35";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext248_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext248__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext248__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext248__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext248__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE12",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE12",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext248__load_store_cache_partial_write_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext248_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE12_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE13",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE13",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext248__load_store_cache_partial_write_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext248_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE13_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE14",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE14",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext248__load_store_cache_partial_write_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext248_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE14_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE15",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE15",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext248__load_store_cache_partial_write_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext248_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext249_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext249_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext249_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext249_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext249_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext249";
    metric_set->symbol_name = "Ext249";
    metric_set->hw_config_guid = "f287382f-3de7-43af-a4c5-20ec8d84b7b1";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext249_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext249__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext249__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext249__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext249__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE16",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE16",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext249__load_store_cache_partial_write_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext249_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE16_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE17",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE17",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext249__load_store_cache_partial_write_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext249_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE17_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE18",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE18",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext249__load_store_cache_partial_write_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext249_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE18_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE19",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE19",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext249__load_store_cache_partial_write_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext249_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext250_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext250_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext250_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext250_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext250_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext250";
    metric_set->symbol_name = "Ext250";
    metric_set->hw_config_guid = "a92c55c1-352f-44fc-a86c-3f0b0e525d97";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext250_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext250__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext250__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext250__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext250__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE20",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE20",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext250__load_store_cache_partial_write_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext250_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE20_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE21",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE21",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext250__load_store_cache_partial_write_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext250_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE21_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE22",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE22",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext250__load_store_cache_partial_write_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext250_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE22_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE23",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE23",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext250__load_store_cache_partial_write_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext250_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext251_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext251_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext251_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext251_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext251_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext251";
    metric_set->symbol_name = "Ext251";
    metric_set->hw_config_guid = "dd5abc73-e90e-4da0-82ed-53c3a598ccf1";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext251_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext251__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext251__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext251__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext251__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE24",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE24",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext251__load_store_cache_partial_write_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext251_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE24_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE25",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE25",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext251__load_store_cache_partial_write_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext251_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE25_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE26",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE26",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext251__load_store_cache_partial_write_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext251_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE26_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE27",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE27",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext251__load_store_cache_partial_write_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext251_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext252_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext252_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext252_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext252_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext252_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext252";
    metric_set->symbol_name = "Ext252";
    metric_set->hw_config_guid = "f4e6e4c6-94f3-4684-813c-b99cb703a638";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext252_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext252__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext252__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext252__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext252__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE28",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE28",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext252__load_store_cache_partial_write_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext252_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE28_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE29",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE29",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext252__load_store_cache_partial_write_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext252_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE29_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE30",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE30",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext252__load_store_cache_partial_write_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext252_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE30_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE31",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE31",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext252__load_store_cache_partial_write_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext252_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext253_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext253_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext253_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext253_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext253_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext253";
    metric_set->symbol_name = "Ext253";
    metric_set->hw_config_guid = "9eb32240-9aee-4864-8229-20ddbb84d6f2";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext253_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext253__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext253__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext253__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext253__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE0",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE0",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext253__xve_load_store_cache_register_request_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext253_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE1",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE1",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext253__xve_load_store_cache_register_request_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext253_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE2",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE2",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext253__xve_load_store_cache_register_request_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext253_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE3",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE3",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext253__xve_load_store_cache_register_request_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext253_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext254_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext254_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext254_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext254_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext254_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext254";
    metric_set->symbol_name = "Ext254";
    metric_set->hw_config_guid = "6e1f70bd-36b6-432d-8576-5461e5ce55eb";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext254_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext254__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext254__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext254__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext254__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE4",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE4",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext254__xve_load_store_cache_register_request_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext254_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE5",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE5",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext254__xve_load_store_cache_register_request_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext254_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE6",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE6",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext254__xve_load_store_cache_register_request_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext254_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE7",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE7",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext254__xve_load_store_cache_register_request_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext254_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext255_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext255_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext255_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext255_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext255_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext255";
    metric_set->symbol_name = "Ext255";
    metric_set->hw_config_guid = "0104ce81-df1b-4f1c-acc4-14cb239f06c1";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext255_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext255__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext255__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext255__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext255__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE10",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE10",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext255__xve_load_store_cache_register_request_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext255_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE11",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE11",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext255__xve_load_store_cache_register_request_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext255_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE11_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE8",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE8",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext255__xve_load_store_cache_register_request_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext255_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE9",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE9",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext255__xve_load_store_cache_register_request_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext255_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext256_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext256_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext256_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext256_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext256_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext256";
    metric_set->symbol_name = "Ext256";
    metric_set->hw_config_guid = "4baeb5dd-8732-4330-8196-dd8b921d710f";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext256_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext256__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext256__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext256__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext256__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE12",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE12",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext256__xve_load_store_cache_register_request_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext256_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE13",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE13",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext256__xve_load_store_cache_register_request_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext256_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE13_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE14",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE14",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext256__xve_load_store_cache_register_request_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext256_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE15",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE15",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext256__xve_load_store_cache_register_request_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext256_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext257_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext257_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext257_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext257_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext257_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext257";
    metric_set->symbol_name = "Ext257";
    metric_set->hw_config_guid = "9e4277a2-341a-4e2b-820d-f53beec1dd6b";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext257_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext257__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext257__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext257__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext257__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE16",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE16",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext257__xve_load_store_cache_register_request_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext257_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE16_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE17",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE17",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext257__xve_load_store_cache_register_request_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext257_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE17_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE18",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE18",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext257__xve_load_store_cache_register_request_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext257_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE18_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE19",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE19",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext257__xve_load_store_cache_register_request_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext257_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext258_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext258_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext258_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext258_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext258_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext258";
    metric_set->symbol_name = "Ext258";
    metric_set->hw_config_guid = "e318efaa-f015-4ee9-ae9d-485a352c06f6";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext258_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext258__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext258__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext258__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext258__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE20",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE20",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext258__xve_load_store_cache_register_request_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext258_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE20_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE21",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE21",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext258__xve_load_store_cache_register_request_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext258_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE21_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE22",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE22",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext258__xve_load_store_cache_register_request_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext258_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE22_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE23",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE23",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext258__xve_load_store_cache_register_request_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext258_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext259_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext259_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext259_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext259_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext259_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext259";
    metric_set->symbol_name = "Ext259";
    metric_set->hw_config_guid = "cf9912aa-c74c-40f0-9120-07ef68972190";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext259_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext259__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext259__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext259__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext259__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE24",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE24",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext259__xve_load_store_cache_register_request_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext259_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE24_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE25",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE25",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext259__xve_load_store_cache_register_request_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext259_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE25_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE26",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE26",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext259__xve_load_store_cache_register_request_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext259_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE26_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE27",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE27",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext259__xve_load_store_cache_register_request_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext259_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext260_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext260_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext260_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext260_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext260_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext260";
    metric_set->symbol_name = "Ext260";
    metric_set->hw_config_guid = "b4b0f306-7714-4fd7-b32f-5bf89d0ea022";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext260_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext260__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext260__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext260__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext260__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE28",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE28",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext260__xve_load_store_cache_register_request_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext260_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE28_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE29",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE29",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext260__xve_load_store_cache_register_request_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext260_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE29_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE30",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE30",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext260__xve_load_store_cache_register_request_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext260_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE30_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE31",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE31",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext260__xve_load_store_cache_register_request_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext260_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext261_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext261_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext261_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext261_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext261_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext261";
    metric_set->symbol_name = "Ext261";
    metric_set->hw_config_guid = "0a9b31d6-473b-46c9-8ad1-d9ae2e47cc8c";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext261_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext261__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext261__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext261__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext261__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE0",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE0",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext261__xve_load_store_cache_register_response_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext261_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE1",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE1",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext261__xve_load_store_cache_register_response_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext261_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE2",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE2",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext261__xve_load_store_cache_register_response_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext261_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE3",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE3",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext261__xve_load_store_cache_register_response_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext261_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext262_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext262_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext262_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext262_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext262_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext262";
    metric_set->symbol_name = "Ext262";
    metric_set->hw_config_guid = "17f09c56-52ed-4d95-a2c4-8d364f7f2055";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext262_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext262__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext262__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext262__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext262__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE4",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE4",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext262__xve_load_store_cache_register_response_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext262_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE5",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE5",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext262__xve_load_store_cache_register_response_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext262_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE6",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE6",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext262__xve_load_store_cache_register_response_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext262_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE7",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE7",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext262__xve_load_store_cache_register_response_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext262_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext263_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext263_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext263_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext263_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext263_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext263";
    metric_set->symbol_name = "Ext263";
    metric_set->hw_config_guid = "755de6ba-8321-4b8e-8b29-30928734d252";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext263_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext263__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext263__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext263__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext263__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE10",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE10",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext263__xve_load_store_cache_register_response_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext263_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE11",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE11",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext263__xve_load_store_cache_register_response_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext263_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE11_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE8",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE8",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext263__xve_load_store_cache_register_response_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext263_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE9",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE9",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext263__xve_load_store_cache_register_response_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext263_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext264_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext264_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext264_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext264_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext264_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext264";
    metric_set->symbol_name = "Ext264";
    metric_set->hw_config_guid = "b622f02d-6710-4412-94f9-4e4abba0bbaa";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext264_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext264__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext264__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext264__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext264__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE12",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE12",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext264__xve_load_store_cache_register_response_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext264_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE13",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE13",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext264__xve_load_store_cache_register_response_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext264_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE13_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE14",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE14",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext264__xve_load_store_cache_register_response_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext264_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE15",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE15",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext264__xve_load_store_cache_register_response_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext264_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext265_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext265_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext265_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext265_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext265_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext265";
    metric_set->symbol_name = "Ext265";
    metric_set->hw_config_guid = "e448a51b-7b45-4454-b682-b3488a24b167";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext265_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext265__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext265__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext265__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext265__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE16",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE16",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext265__xve_load_store_cache_register_response_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext265_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE16_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE17",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE17",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext265__xve_load_store_cache_register_response_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext265_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE17_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE18",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE18",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext265__xve_load_store_cache_register_response_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext265_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE18_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE19",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE19",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext265__xve_load_store_cache_register_response_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext265_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext266_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext266_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext266_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext266_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext266_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext266";
    metric_set->symbol_name = "Ext266";
    metric_set->hw_config_guid = "df480a9e-5d23-4477-b5cf-e89d7590ff9c";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext266_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext266__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext266__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext266__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext266__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE20",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE20",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext266__xve_load_store_cache_register_response_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext266_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE20_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE21",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE21",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext266__xve_load_store_cache_register_response_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext266_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE21_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE22",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE22",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext266__xve_load_store_cache_register_response_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext266_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE22_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE23",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE23",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext266__xve_load_store_cache_register_response_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext266_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext267_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext267_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext267_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext267_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext267_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext267";
    metric_set->symbol_name = "Ext267";
    metric_set->hw_config_guid = "d2569d38-f95c-4996-9f95-aa61ba11015a";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext267_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext267__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext267__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext267__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext267__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE24",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE24",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext267__xve_load_store_cache_register_response_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext267_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE24_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE25",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE25",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext267__xve_load_store_cache_register_response_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext267_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE25_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE26",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE26",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext267__xve_load_store_cache_register_response_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext267_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE26_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE27",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE27",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext267__xve_load_store_cache_register_response_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext267_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext268_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext268_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext268_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext268_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext268_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext268";
    metric_set->symbol_name = "Ext268";
    metric_set->hw_config_guid = "95a739c5-5a9c-47df-836f-3b323b9d8df8";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext268_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext268__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext268__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext268__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext268__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE28",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE28",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext268__xve_load_store_cache_register_response_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext268_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE28_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE29",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE29",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext268__xve_load_store_cache_register_response_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext268_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE29_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE30",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE30",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext268__xve_load_store_cache_register_response_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext268_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE30_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE31",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE31",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext268__xve_load_store_cache_register_response_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext268_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext269_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext269_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext269_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext269_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext269_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext269";
    metric_set->symbol_name = "Ext269";
    metric_set->hw_config_guid = "4ee78f20-69b6-4bcd-9d6f-06ebee2e2f54";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext269_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext269__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext269__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext269__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext269__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext269__load_store_cache_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext269_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext269__load_store_cache_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext269_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext269__load_store_cache_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext269_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext269__load_store_cache_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext269_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext270_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext270_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext270_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext270_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext270_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext270";
    metric_set->symbol_name = "Ext270";
    metric_set->hw_config_guid = "e9217a53-0407-4df2-a014-8df62ecd2dcc";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext270_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext270__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext270__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext270__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext270__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext270__load_store_cache_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext270_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext270__load_store_cache_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext270_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext270__load_store_cache_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext270_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext270__load_store_cache_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext270_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext271_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext271_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext271_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext271_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext271_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext271";
    metric_set->symbol_name = "Ext271";
    metric_set->hw_config_guid = "7d6d9a79-6ddf-4970-9fcd-ece8cfc4f26b";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext271_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext271__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext271__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext271__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext271__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE10",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE10",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext271__load_store_cache_input_available_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext271_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE10_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE11",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE11",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext271__load_store_cache_input_available_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext271_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE11_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE8",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE8",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext271__load_store_cache_input_available_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext271_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE8_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE9",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE9",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext271__load_store_cache_input_available_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext271_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext272_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext272_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext272_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext272_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext272_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext272";
    metric_set->symbol_name = "Ext272";
    metric_set->hw_config_guid = "0ecd2c83-ea1b-4801-b6c0-c571e301477b";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext272_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext272__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext272__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext272__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext272__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE12",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE12",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext272__load_store_cache_input_available_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext272_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE12_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE13",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE13",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext272__load_store_cache_input_available_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext272_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE13_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE14",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE14",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext272__load_store_cache_input_available_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext272_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE14_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE15",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE15",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext272__load_store_cache_input_available_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext272_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext273_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext273_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext273_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext273_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext273_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext273";
    metric_set->symbol_name = "Ext273";
    metric_set->hw_config_guid = "377395f6-3e5d-45ab-a2ff-980f1f795590";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext273_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext273__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext273__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext273__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext273__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE16",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE16",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext273__load_store_cache_input_available_xecore16__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext273_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE16_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE17",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE17",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext273__load_store_cache_input_available_xecore17__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext273_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE17_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE18",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE18",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext273__load_store_cache_input_available_xecore18__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext273_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE18_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE19",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE19",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext273__load_store_cache_input_available_xecore19__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext273_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext274_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext274_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext274_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext274_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext274_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext274";
    metric_set->symbol_name = "Ext274";
    metric_set->hw_config_guid = "ebf4b987-f2e1-45c5-83c1-145baa637929";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext274_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext274__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext274__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext274__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext274__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE20",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE20",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext274__load_store_cache_input_available_xecore20__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext274_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE20_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE21",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE21",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext274__load_store_cache_input_available_xecore21__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext274_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE21_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE22",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE22",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext274__load_store_cache_input_available_xecore22__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext274_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE22_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE23",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE23",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext274__load_store_cache_input_available_xecore23__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext274_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext275_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext275_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext275_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext275_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext275_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext275";
    metric_set->symbol_name = "Ext275";
    metric_set->hw_config_guid = "e0559ea9-aae3-4ede-8d15-30dcc8c4a202";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext275_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext275__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext275__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext275__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext275__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE24",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE24",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext275__load_store_cache_input_available_xecore24__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext275_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE24_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE25",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE25",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext275__load_store_cache_input_available_xecore25__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext275_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE25_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE26",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE26",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext275__load_store_cache_input_available_xecore26__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext275_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE26_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE27",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE27",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext275__load_store_cache_input_available_xecore27__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext275_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext276_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext276_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext276_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext276_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext276_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext276";
    metric_set->symbol_name = "Ext276";
    metric_set->hw_config_guid = "180b2a02-9d8c-4bf9-be0b-31cf265c21da";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext276_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext276__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext276__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext276__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext276__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE28",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE28",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext276__load_store_cache_input_available_xecore28__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext276_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE28_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE29",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE29",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext276__load_store_cache_input_available_xecore29__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext276_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE29_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE30",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE30",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext276__load_store_cache_input_available_xecore30__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext276_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE30_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE31",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE31",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext276__load_store_cache_input_available_xecore31__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext276_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext277_LOAD_STORE_CACHE_OUTPUT_READY_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext277_LOAD_STORE_CACHE_OUTPUT_READY_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext277_LOAD_STORE_CACHE_OUTPUT_READY_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext277_LOAD_STORE_CACHE_OUTPUT_READY_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext277_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext277";
    metric_set->symbol_name = "Ext277";
    metric_set->hw_config_guid = "4e381e22-6068-4a63-9fea-270aee7731af";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext277_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext277__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext277__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext277__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext277__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE0",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext277__load_store_cache_output_ready_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext277_LOAD_STORE_CACHE_OUTPUT_READY_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE1",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext277__load_store_cache_output_ready_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext277_LOAD_STORE_CACHE_OUTPUT_READY_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE2",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext277__load_store_cache_output_ready_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext277_LOAD_STORE_CACHE_OUTPUT_READY_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE3",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext277__load_store_cache_output_ready_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext277_LOAD_STORE_CACHE_OUTPUT_READY_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext278_LOAD_STORE_CACHE_OUTPUT_READY_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext278_LOAD_STORE_CACHE_OUTPUT_READY_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext278_LOAD_STORE_CACHE_OUTPUT_READY_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext278_LOAD_STORE_CACHE_OUTPUT_READY_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext278_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext278";
    metric_set->symbol_name = "Ext278";
    metric_set->hw_config_guid = "3e47b601-d0e5-4eac-a32a-d4419b455ef6";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext278_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext278__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext278__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext278__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext278__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE4",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext278__load_store_cache_output_ready_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext278_LOAD_STORE_CACHE_OUTPUT_READY_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE5",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext278__load_store_cache_output_ready_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext278_LOAD_STORE_CACHE_OUTPUT_READY_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE6",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext278__load_store_cache_output_ready_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext278_LOAD_STORE_CACHE_OUTPUT_READY_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE7",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext278__load_store_cache_output_ready_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext278_LOAD_STORE_CACHE_OUTPUT_READY_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext279_LOAD_STORE_CACHE_OUTPUT_READY_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext279_LOAD_STORE_CACHE_OUTPUT_READY_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext279_LOAD_STORE_CACHE_OUTPUT_READY_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext279_LOAD_STORE_CACHE_OUTPUT_READY_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext279_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext279";
    metric_set->symbol_name = "Ext279";
    metric_set->hw_config_guid = "45b87d00-391e-46a0-8750-61da7a17db1c";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext279_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext279__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext279__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext279__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext279__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE10",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE10",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext279__load_store_cache_output_ready_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext279_LOAD_STORE_CACHE_OUTPUT_READY_XECORE10_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE11",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE11",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext279__load_store_cache_output_ready_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext279_LOAD_STORE_CACHE_OUTPUT_READY_XECORE11_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE8",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE8",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext279__load_store_cache_output_ready_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext279_LOAD_STORE_CACHE_OUTPUT_READY_XECORE8_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE9",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE9",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext279__load_store_cache_output_ready_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext279_LOAD_STORE_CACHE_OUTPUT_READY_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext280_LOAD_STORE_CACHE_OUTPUT_READY_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext280_LOAD_STORE_CACHE_OUTPUT_READY_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext280_LOAD_STORE_CACHE_OUTPUT_READY_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext280_LOAD_STORE_CACHE_OUTPUT_READY_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext280_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext280";
    metric_set->symbol_name = "Ext280";
    metric_set->hw_config_guid = "85c3a4dc-ebc9-45e6-b572-fab58fa5bdd2";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext280_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext280__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext280__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext280__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext280__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE12",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE12",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext280__load_store_cache_output_ready_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext280_LOAD_STORE_CACHE_OUTPUT_READY_XECORE12_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE13",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE13",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext280__load_store_cache_output_ready_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext280_LOAD_STORE_CACHE_OUTPUT_READY_XECORE13_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE14",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE14",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext280__load_store_cache_output_ready_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext280_LOAD_STORE_CACHE_OUTPUT_READY_XECORE14_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE15",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE15",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext280__load_store_cache_output_ready_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext280_LOAD_STORE_CACHE_OUTPUT_READY_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext281_LOAD_STORE_CACHE_OUTPUT_READY_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext281_LOAD_STORE_CACHE_OUTPUT_READY_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext281_LOAD_STORE_CACHE_OUTPUT_READY_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext281_LOAD_STORE_CACHE_OUTPUT_READY_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext281_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext281";
    metric_set->symbol_name = "Ext281";
    metric_set->hw_config_guid = "d7725644-0058-46cd-935d-55e1bf8d0e8b";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext281_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext281__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext281__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext281__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext281__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE16",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE16",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext281__load_store_cache_output_ready_xecore16__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext281_LOAD_STORE_CACHE_OUTPUT_READY_XECORE16_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE17",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE17",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext281__load_store_cache_output_ready_xecore17__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext281_LOAD_STORE_CACHE_OUTPUT_READY_XECORE17_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE18",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE18",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext281__load_store_cache_output_ready_xecore18__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext281_LOAD_STORE_CACHE_OUTPUT_READY_XECORE18_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE19",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE19",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext281__load_store_cache_output_ready_xecore19__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext281_LOAD_STORE_CACHE_OUTPUT_READY_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext282_LOAD_STORE_CACHE_OUTPUT_READY_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext282_LOAD_STORE_CACHE_OUTPUT_READY_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext282_LOAD_STORE_CACHE_OUTPUT_READY_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext282_LOAD_STORE_CACHE_OUTPUT_READY_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext282_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext282";
    metric_set->symbol_name = "Ext282";
    metric_set->hw_config_guid = "234accb5-7742-4ff5-b3d6-598cc74a4f95";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext282_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext282__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext282__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext282__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext282__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE20",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE20",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext282__load_store_cache_output_ready_xecore20__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext282_LOAD_STORE_CACHE_OUTPUT_READY_XECORE20_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE21",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE21",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext282__load_store_cache_output_ready_xecore21__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext282_LOAD_STORE_CACHE_OUTPUT_READY_XECORE21_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE22",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE22",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext282__load_store_cache_output_ready_xecore22__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext282_LOAD_STORE_CACHE_OUTPUT_READY_XECORE22_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE23",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE23",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext282__load_store_cache_output_ready_xecore23__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext282_LOAD_STORE_CACHE_OUTPUT_READY_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext283_LOAD_STORE_CACHE_OUTPUT_READY_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext283_LOAD_STORE_CACHE_OUTPUT_READY_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext283_LOAD_STORE_CACHE_OUTPUT_READY_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext283_LOAD_STORE_CACHE_OUTPUT_READY_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext283_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext283";
    metric_set->symbol_name = "Ext283";
    metric_set->hw_config_guid = "75c93a0c-e686-4e48-baca-a557d2284a06";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext283_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext283__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext283__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext283__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext283__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE24",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE24",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext283__load_store_cache_output_ready_xecore24__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext283_LOAD_STORE_CACHE_OUTPUT_READY_XECORE24_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE25",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE25",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext283__load_store_cache_output_ready_xecore25__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext283_LOAD_STORE_CACHE_OUTPUT_READY_XECORE25_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE26",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE26",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext283__load_store_cache_output_ready_xecore26__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext283_LOAD_STORE_CACHE_OUTPUT_READY_XECORE26_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE27",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE27",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext283__load_store_cache_output_ready_xecore27__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext283_LOAD_STORE_CACHE_OUTPUT_READY_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext284_LOAD_STORE_CACHE_OUTPUT_READY_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext284_LOAD_STORE_CACHE_OUTPUT_READY_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext284_LOAD_STORE_CACHE_OUTPUT_READY_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext284_LOAD_STORE_CACHE_OUTPUT_READY_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext284_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext284";
    metric_set->symbol_name = "Ext284";
    metric_set->hw_config_guid = "6059f40a-ba6c-4032-8eb0-a3a60760d22e";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext284_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext284__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext284__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext284__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext284__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE28",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE28",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext284__load_store_cache_output_ready_xecore28__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext284_LOAD_STORE_CACHE_OUTPUT_READY_XECORE28_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE29",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE29",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext284__load_store_cache_output_ready_xecore29__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext284_LOAD_STORE_CACHE_OUTPUT_READY_XECORE29_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE30",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE30",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext284__load_store_cache_output_ready_xecore30__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext284_LOAD_STORE_CACHE_OUTPUT_READY_XECORE30_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE31",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE31",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext284__load_store_cache_output_ready_xecore31__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt3_ext284_LOAD_STORE_CACHE_OUTPUT_READY_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext285_L3_STALL_L3BANK30_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext285_L3_STALL_L3BANK31_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext285_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext285";
    metric_set->symbol_name = "Ext285";
    metric_set->hw_config_guid = "030a5d74-26a8-40ea-b40e-be5f1e0cd212";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext285_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext285__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext285__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext285__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext285__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BANK STALL L3BANK30",
                .symbol_name = "L3_STALL_L3BANK30",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext285__l3_stall_l3_bank30__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext285_L3_STALL_L3BANK30_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK31",
                .symbol_name = "L3_STALL_L3BANK31",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext285__l3_stall_l3_bank31__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt3_ext285_L3_STALL_L3BANK31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext286_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext286_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext286_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext286_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext286_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext286_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext286_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext286_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext286_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext286";
    metric_set->symbol_name = "Ext286";
    metric_set->hw_config_guid = "92ecf953-51a1-47dd-b5f4-f942e64b9c7c";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext286_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext286__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext286__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "COLOR PIPE CACHE LATENCY2 STALL L3NODE0",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE0",
                .desc = "Percentage of time in which Color Pipeline stalled due to Render Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext286__color_pipe_cache_latency2_stall_l3_node0__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext286_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE0_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY2 STALL L3NODE1",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE1",
                .desc = "Percentage of time in which Color Pipeline stalled due to Render Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext286__color_pipe_cache_latency2_stall_l3_node1__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext286_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE1_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY2 STALL L3NODE2",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE2",
                .desc = "Percentage of time in which Color Pipeline stalled due to Render Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext286__color_pipe_cache_latency2_stall_l3_node2__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext286_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE2_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY2 STALL L3NODE3",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE3",
                .desc = "Percentage of time in which Color Pipeline stalled due to Render Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext286__color_pipe_cache_latency2_stall_l3_node3__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext286_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE3_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY2 STALL L3NODE4",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE4",
                .desc = "Percentage of time in which Color Pipeline stalled due to Render Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext286__color_pipe_cache_latency2_stall_l3_node4__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext286_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE4_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY2 STALL L3NODE5",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE5",
                .desc = "Percentage of time in which Color Pipeline stalled due to Render Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext286__color_pipe_cache_latency2_stall_l3_node5__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext286_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE5_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY2 STALL L3NODE6",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE6",
                .desc = "Percentage of time in which Color Pipeline stalled due to Render Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext286__color_pipe_cache_latency2_stall_l3_node6__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext286_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE6_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY2 STALL L3NODE7",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE7",
                .desc = "Percentage of time in which Color Pipeline stalled due to Render Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext286__color_pipe_cache_latency2_stall_l3_node7__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext286_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext286__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext286__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext288_SAMPLER_OUTPUT_READY_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext288_SAMPLER_OUTPUT_READY_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext288_SAMPLER_OUTPUT_READY_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext288_SAMPLER_OUTPUT_READY_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext288_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext288";
    metric_set->symbol_name = "Ext288";
    metric_set->hw_config_guid = "1f9ac2d2-5aee-4e58-acb1-9d609849ac7a";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext288_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext288__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext288__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext288__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext288__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE0",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE0",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext288__sampler_output_ready_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext288_SAMPLER_OUTPUT_READY_XECORE0_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE1",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE1",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext288__sampler_output_ready_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext288_SAMPLER_OUTPUT_READY_XECORE1_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE2",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE2",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext288__sampler_output_ready_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext288_SAMPLER_OUTPUT_READY_XECORE2_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE3",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE3",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext288__sampler_output_ready_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext288_SAMPLER_OUTPUT_READY_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext289_SAMPLER_OUTPUT_READY_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext289_SAMPLER_OUTPUT_READY_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext289_SAMPLER_OUTPUT_READY_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext289_SAMPLER_OUTPUT_READY_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext289_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext289";
    metric_set->symbol_name = "Ext289";
    metric_set->hw_config_guid = "aa8781c1-b216-4aec-918a-142fe18607ac";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext289_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext289__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext289__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext289__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext289__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE4",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE4",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext289__sampler_output_ready_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext289_SAMPLER_OUTPUT_READY_XECORE4_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE5",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE5",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext289__sampler_output_ready_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext289_SAMPLER_OUTPUT_READY_XECORE5_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE6",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE6",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext289__sampler_output_ready_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext289_SAMPLER_OUTPUT_READY_XECORE6_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE7",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE7",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext289__sampler_output_ready_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext289_SAMPLER_OUTPUT_READY_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext290_SAMPLER_OUTPUT_READY_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext290_SAMPLER_OUTPUT_READY_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext290_SAMPLER_OUTPUT_READY_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext290_SAMPLER_OUTPUT_READY_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext290_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext290";
    metric_set->symbol_name = "Ext290";
    metric_set->hw_config_guid = "16a4c831-37d6-4fff-a77f-0e4c5b325510";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext290_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext290__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext290__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext290__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext290__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE10",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE10",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext290__sampler_output_ready_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext290_SAMPLER_OUTPUT_READY_XECORE10_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE11",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE11",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext290__sampler_output_ready_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext290_SAMPLER_OUTPUT_READY_XECORE11_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE8",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE8",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext290__sampler_output_ready_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext290_SAMPLER_OUTPUT_READY_XECORE8_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE9",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE9",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext290__sampler_output_ready_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext290_SAMPLER_OUTPUT_READY_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext291_SAMPLER_OUTPUT_READY_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext291_SAMPLER_OUTPUT_READY_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext291_SAMPLER_OUTPUT_READY_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext291_SAMPLER_OUTPUT_READY_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext291_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext291";
    metric_set->symbol_name = "Ext291";
    metric_set->hw_config_guid = "be7c8afd-0a80-4cd9-8266-faf796deb5d8";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext291_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext291__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext291__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext291__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext291__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE12",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE12",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext291__sampler_output_ready_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext291_SAMPLER_OUTPUT_READY_XECORE12_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE13",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE13",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext291__sampler_output_ready_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext291_SAMPLER_OUTPUT_READY_XECORE13_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE14",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE14",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext291__sampler_output_ready_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext291_SAMPLER_OUTPUT_READY_XECORE14_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE15",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE15",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext291__sampler_output_ready_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext291_SAMPLER_OUTPUT_READY_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext292_SAMPLER_OUTPUT_READY_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext292_SAMPLER_OUTPUT_READY_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext292_SAMPLER_OUTPUT_READY_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext292_SAMPLER_OUTPUT_READY_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext292_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext292";
    metric_set->symbol_name = "Ext292";
    metric_set->hw_config_guid = "d87b1ecd-4ef5-4632-9f83-19ca481f2ece";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext292_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext292__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext292__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext292__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext292__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE16",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE16",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext292__sampler_output_ready_xecore16__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext292_SAMPLER_OUTPUT_READY_XECORE16_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE17",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE17",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext292__sampler_output_ready_xecore17__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext292_SAMPLER_OUTPUT_READY_XECORE17_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE18",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE18",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext292__sampler_output_ready_xecore18__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext292_SAMPLER_OUTPUT_READY_XECORE18_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE19",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE19",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext292__sampler_output_ready_xecore19__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext292_SAMPLER_OUTPUT_READY_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext293_SAMPLER_OUTPUT_READY_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext293_SAMPLER_OUTPUT_READY_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext293_SAMPLER_OUTPUT_READY_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext293_SAMPLER_OUTPUT_READY_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext293_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext293";
    metric_set->symbol_name = "Ext293";
    metric_set->hw_config_guid = "918f11cd-e0a7-4503-87b3-0f16c4464d77";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext293_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext293__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext293__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext293__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext293__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE20",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE20",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext293__sampler_output_ready_xecore20__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext293_SAMPLER_OUTPUT_READY_XECORE20_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE21",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE21",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext293__sampler_output_ready_xecore21__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext293_SAMPLER_OUTPUT_READY_XECORE21_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE22",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE22",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext293__sampler_output_ready_xecore22__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext293_SAMPLER_OUTPUT_READY_XECORE22_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE23",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE23",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext293__sampler_output_ready_xecore23__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext293_SAMPLER_OUTPUT_READY_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext294_SAMPLER_OUTPUT_READY_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext294_SAMPLER_OUTPUT_READY_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext294_SAMPLER_OUTPUT_READY_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext294_SAMPLER_OUTPUT_READY_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext294_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext294";
    metric_set->symbol_name = "Ext294";
    metric_set->hw_config_guid = "1b1d6474-3018-4d9a-938e-11d81cc70491";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext294_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext294__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext294__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext294__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext294__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE24",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE24",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext294__sampler_output_ready_xecore24__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext294_SAMPLER_OUTPUT_READY_XECORE24_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE25",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE25",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext294__sampler_output_ready_xecore25__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext294_SAMPLER_OUTPUT_READY_XECORE25_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE26",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE26",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext294__sampler_output_ready_xecore26__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext294_SAMPLER_OUTPUT_READY_XECORE26_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE27",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE27",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext294__sampler_output_ready_xecore27__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext294_SAMPLER_OUTPUT_READY_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext295_SAMPLER_OUTPUT_READY_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext295_SAMPLER_OUTPUT_READY_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext295_SAMPLER_OUTPUT_READY_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext295_SAMPLER_OUTPUT_READY_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext295_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext295";
    metric_set->symbol_name = "Ext295";
    metric_set->hw_config_guid = "50114a1e-a637-4027-9ee5-42d12d569896";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext295_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext295__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext295__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext295__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext295__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE28",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE28",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext295__sampler_output_ready_xecore28__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext295_SAMPLER_OUTPUT_READY_XECORE28_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE29",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE29",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext295__sampler_output_ready_xecore29__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext295_SAMPLER_OUTPUT_READY_XECORE29_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE30",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE30",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext295__sampler_output_ready_xecore30__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext295_SAMPLER_OUTPUT_READY_XECORE30_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE31",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE31",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext295__sampler_output_ready_xecore31__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext295_SAMPLER_OUTPUT_READY_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext296_SAMPLER_BUSY_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext296_SAMPLER_BUSY_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext296_SAMPLER_BUSY_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext296_SAMPLER_BUSY_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext296_SAMPLER_BUSY_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext296_SAMPLER_BUSY_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext296_SAMPLER_BUSY_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext296_SAMPLER_BUSY_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext296_SAMPLER_BUSY_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext296_SAMPLER_BUSY_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext296_SAMPLER_BUSY_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext296_SAMPLER_BUSY_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext296_SAMPLER_BUSY_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext296_SAMPLER_BUSY_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext296_SAMPLER_BUSY_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext296_SAMPLER_BUSY_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext296_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext296";
    metric_set->symbol_name = "Ext296";
    metric_set->hw_config_guid = "d67549fb-4308-437b-8c48-662a3782b3fa";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext296_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext296__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext296__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext296__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext296__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER BUSY XECORE0",
                .symbol_name = "SAMPLER_BUSY_XECORE0",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext296__sampler_busy_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext296_SAMPLER_BUSY_XECORE0_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE1",
                .symbol_name = "SAMPLER_BUSY_XECORE1",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext296__sampler_busy_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext296_SAMPLER_BUSY_XECORE1_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE10",
                .symbol_name = "SAMPLER_BUSY_XECORE10",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext296__sampler_busy_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext296_SAMPLER_BUSY_XECORE10_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE11",
                .symbol_name = "SAMPLER_BUSY_XECORE11",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext296__sampler_busy_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext296_SAMPLER_BUSY_XECORE11_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE12",
                .symbol_name = "SAMPLER_BUSY_XECORE12",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext296__sampler_busy_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext296_SAMPLER_BUSY_XECORE12_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE13",
                .symbol_name = "SAMPLER_BUSY_XECORE13",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext296__sampler_busy_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext296_SAMPLER_BUSY_XECORE13_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE14",
                .symbol_name = "SAMPLER_BUSY_XECORE14",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext296__sampler_busy_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext296_SAMPLER_BUSY_XECORE14_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE15",
                .symbol_name = "SAMPLER_BUSY_XECORE15",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext296__sampler_busy_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext296_SAMPLER_BUSY_XECORE15_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE2",
                .symbol_name = "SAMPLER_BUSY_XECORE2",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext296__sampler_busy_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext296_SAMPLER_BUSY_XECORE2_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE3",
                .symbol_name = "SAMPLER_BUSY_XECORE3",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext296__sampler_busy_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext296_SAMPLER_BUSY_XECORE3_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE4",
                .symbol_name = "SAMPLER_BUSY_XECORE4",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext296__sampler_busy_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext296_SAMPLER_BUSY_XECORE4_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE5",
                .symbol_name = "SAMPLER_BUSY_XECORE5",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext296__sampler_busy_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext296_SAMPLER_BUSY_XECORE5_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE6",
                .symbol_name = "SAMPLER_BUSY_XECORE6",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext296__sampler_busy_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext296_SAMPLER_BUSY_XECORE6_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE7",
                .symbol_name = "SAMPLER_BUSY_XECORE7",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext296__sampler_busy_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext296_SAMPLER_BUSY_XECORE7_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE8",
                .symbol_name = "SAMPLER_BUSY_XECORE8",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext296__sampler_busy_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext296_SAMPLER_BUSY_XECORE8_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE9",
                .symbol_name = "SAMPLER_BUSY_XECORE9",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext296__sampler_busy_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext296_SAMPLER_BUSY_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext297_SAMPLER_BUSY_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext297_SAMPLER_BUSY_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext297_SAMPLER_BUSY_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext297_SAMPLER_BUSY_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext297_SAMPLER_BUSY_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext297_SAMPLER_BUSY_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext297_SAMPLER_BUSY_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext297_SAMPLER_BUSY_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext297_SAMPLER_BUSY_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext297_SAMPLER_BUSY_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext297_SAMPLER_BUSY_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext297_SAMPLER_BUSY_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext297_SAMPLER_BUSY_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext297_SAMPLER_BUSY_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext297_SAMPLER_BUSY_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext297_SAMPLER_BUSY_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext297_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext297";
    metric_set->symbol_name = "Ext297";
    metric_set->hw_config_guid = "1b1a9373-ac71-43d2-a428-b02826a6d5bb";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext297_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext297__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext297__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext297__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext297__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER BUSY XECORE16",
                .symbol_name = "SAMPLER_BUSY_XECORE16",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext297__sampler_busy_xecore16__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext297_SAMPLER_BUSY_XECORE16_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE17",
                .symbol_name = "SAMPLER_BUSY_XECORE17",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext297__sampler_busy_xecore17__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext297_SAMPLER_BUSY_XECORE17_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE18",
                .symbol_name = "SAMPLER_BUSY_XECORE18",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext297__sampler_busy_xecore18__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext297_SAMPLER_BUSY_XECORE18_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE19",
                .symbol_name = "SAMPLER_BUSY_XECORE19",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext297__sampler_busy_xecore19__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext297_SAMPLER_BUSY_XECORE19_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE20",
                .symbol_name = "SAMPLER_BUSY_XECORE20",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext297__sampler_busy_xecore20__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext297_SAMPLER_BUSY_XECORE20_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE21",
                .symbol_name = "SAMPLER_BUSY_XECORE21",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext297__sampler_busy_xecore21__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext297_SAMPLER_BUSY_XECORE21_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE22",
                .symbol_name = "SAMPLER_BUSY_XECORE22",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext297__sampler_busy_xecore22__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext297_SAMPLER_BUSY_XECORE22_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE23",
                .symbol_name = "SAMPLER_BUSY_XECORE23",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext297__sampler_busy_xecore23__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext297_SAMPLER_BUSY_XECORE23_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE24",
                .symbol_name = "SAMPLER_BUSY_XECORE24",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext297__sampler_busy_xecore24__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext297_SAMPLER_BUSY_XECORE24_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE25",
                .symbol_name = "SAMPLER_BUSY_XECORE25",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext297__sampler_busy_xecore25__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext297_SAMPLER_BUSY_XECORE25_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE26",
                .symbol_name = "SAMPLER_BUSY_XECORE26",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext297__sampler_busy_xecore26__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext297_SAMPLER_BUSY_XECORE26_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE27",
                .symbol_name = "SAMPLER_BUSY_XECORE27",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext297__sampler_busy_xecore27__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext297_SAMPLER_BUSY_XECORE27_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE28",
                .symbol_name = "SAMPLER_BUSY_XECORE28",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext297__sampler_busy_xecore28__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext297_SAMPLER_BUSY_XECORE28_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE29",
                .symbol_name = "SAMPLER_BUSY_XECORE29",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext297__sampler_busy_xecore29__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext297_SAMPLER_BUSY_XECORE29_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE30",
                .symbol_name = "SAMPLER_BUSY_XECORE30",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext297__sampler_busy_xecore30__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext297_SAMPLER_BUSY_XECORE30_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE31",
                .symbol_name = "SAMPLER_BUSY_XECORE31",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext297__sampler_busy_xecore31__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext297_SAMPLER_BUSY_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext298_SAMPLER_MEMORY_LATENCY_STALL_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext298_SAMPLER_MEMORY_LATENCY_STALL_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext298_SAMPLER_MEMORY_LATENCY_STALL_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext298_SAMPLER_MEMORY_LATENCY_STALL_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext298_SAMPLER_MEMORY_LATENCY_STALL_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext298_SAMPLER_MEMORY_LATENCY_STALL_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext298_SAMPLER_MEMORY_LATENCY_STALL_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext298_SAMPLER_MEMORY_LATENCY_STALL_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext298_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext298";
    metric_set->symbol_name = "Ext298";
    metric_set->hw_config_guid = "87e14c77-8814-4632-941c-567a5aed2b97";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext298_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext298__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext298__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext298__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext298__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE0",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE0",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext298__sampler_memory_latency_stall_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext298_SAMPLER_MEMORY_LATENCY_STALL_XECORE0_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE1",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE1",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext298__sampler_memory_latency_stall_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext298_SAMPLER_MEMORY_LATENCY_STALL_XECORE1_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE2",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE2",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext298__sampler_memory_latency_stall_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext298_SAMPLER_MEMORY_LATENCY_STALL_XECORE2_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE3",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE3",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext298__sampler_memory_latency_stall_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext298_SAMPLER_MEMORY_LATENCY_STALL_XECORE3_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE4",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE4",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext298__sampler_memory_latency_stall_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext298_SAMPLER_MEMORY_LATENCY_STALL_XECORE4_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE5",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE5",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext298__sampler_memory_latency_stall_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext298_SAMPLER_MEMORY_LATENCY_STALL_XECORE5_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE6",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE6",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext298__sampler_memory_latency_stall_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext298_SAMPLER_MEMORY_LATENCY_STALL_XECORE6_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE7",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE7",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext298__sampler_memory_latency_stall_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext298_SAMPLER_MEMORY_LATENCY_STALL_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext299_SAMPLER_MEMORY_LATENCY_STALL_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext299_SAMPLER_MEMORY_LATENCY_STALL_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext299_SAMPLER_MEMORY_LATENCY_STALL_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext299_SAMPLER_MEMORY_LATENCY_STALL_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext299_SAMPLER_MEMORY_LATENCY_STALL_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext299_SAMPLER_MEMORY_LATENCY_STALL_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext299_SAMPLER_MEMORY_LATENCY_STALL_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext299_SAMPLER_MEMORY_LATENCY_STALL_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext299_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext299";
    metric_set->symbol_name = "Ext299";
    metric_set->hw_config_guid = "13ce3184-9cd0-4c5b-bedd-a6fa38d76456";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext299_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext299__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext299__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext299__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext299__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE10",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE10",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext299__sampler_memory_latency_stall_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext299_SAMPLER_MEMORY_LATENCY_STALL_XECORE10_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE11",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE11",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext299__sampler_memory_latency_stall_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext299_SAMPLER_MEMORY_LATENCY_STALL_XECORE11_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE12",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE12",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext299__sampler_memory_latency_stall_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext299_SAMPLER_MEMORY_LATENCY_STALL_XECORE12_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE13",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE13",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext299__sampler_memory_latency_stall_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext299_SAMPLER_MEMORY_LATENCY_STALL_XECORE13_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE14",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE14",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext299__sampler_memory_latency_stall_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext299_SAMPLER_MEMORY_LATENCY_STALL_XECORE14_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE15",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE15",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext299__sampler_memory_latency_stall_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext299_SAMPLER_MEMORY_LATENCY_STALL_XECORE15_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE8",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE8",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext299__sampler_memory_latency_stall_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext299_SAMPLER_MEMORY_LATENCY_STALL_XECORE8_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE9",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE9",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext299__sampler_memory_latency_stall_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext299_SAMPLER_MEMORY_LATENCY_STALL_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext300_SAMPLER_MEMORY_LATENCY_STALL_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext300_SAMPLER_MEMORY_LATENCY_STALL_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext300_SAMPLER_MEMORY_LATENCY_STALL_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext300_SAMPLER_MEMORY_LATENCY_STALL_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext300_SAMPLER_MEMORY_LATENCY_STALL_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext300_SAMPLER_MEMORY_LATENCY_STALL_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext300_SAMPLER_MEMORY_LATENCY_STALL_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext300_SAMPLER_MEMORY_LATENCY_STALL_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext300_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext300";
    metric_set->symbol_name = "Ext300";
    metric_set->hw_config_guid = "015cec04-576e-496b-b4d8-53409c442065";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext300_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext300__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext300__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext300__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext300__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE16",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE16",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext300__sampler_memory_latency_stall_xecore16__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext300_SAMPLER_MEMORY_LATENCY_STALL_XECORE16_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE17",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE17",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext300__sampler_memory_latency_stall_xecore17__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext300_SAMPLER_MEMORY_LATENCY_STALL_XECORE17_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE18",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE18",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext300__sampler_memory_latency_stall_xecore18__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext300_SAMPLER_MEMORY_LATENCY_STALL_XECORE18_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE19",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE19",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext300__sampler_memory_latency_stall_xecore19__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext300_SAMPLER_MEMORY_LATENCY_STALL_XECORE19_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE20",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE20",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext300__sampler_memory_latency_stall_xecore20__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext300_SAMPLER_MEMORY_LATENCY_STALL_XECORE20_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE21",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE21",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext300__sampler_memory_latency_stall_xecore21__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext300_SAMPLER_MEMORY_LATENCY_STALL_XECORE21_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE22",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE22",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext300__sampler_memory_latency_stall_xecore22__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext300_SAMPLER_MEMORY_LATENCY_STALL_XECORE22_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE23",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE23",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext300__sampler_memory_latency_stall_xecore23__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext300_SAMPLER_MEMORY_LATENCY_STALL_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext301_SAMPLER_MEMORY_LATENCY_STALL_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext301_SAMPLER_MEMORY_LATENCY_STALL_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext301_SAMPLER_MEMORY_LATENCY_STALL_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext301_SAMPLER_MEMORY_LATENCY_STALL_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext301_SAMPLER_MEMORY_LATENCY_STALL_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext301_SAMPLER_MEMORY_LATENCY_STALL_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext301_SAMPLER_MEMORY_LATENCY_STALL_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext301_SAMPLER_MEMORY_LATENCY_STALL_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext301_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext301";
    metric_set->symbol_name = "Ext301";
    metric_set->hw_config_guid = "8b9a7b9c-a688-43ea-9c4b-fa6ba53852ab";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext301_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext301__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext301__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext301__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext301__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE24",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE24",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext301__sampler_memory_latency_stall_xecore24__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext301_SAMPLER_MEMORY_LATENCY_STALL_XECORE24_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE25",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE25",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext301__sampler_memory_latency_stall_xecore25__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext301_SAMPLER_MEMORY_LATENCY_STALL_XECORE25_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE26",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE26",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext301__sampler_memory_latency_stall_xecore26__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext301_SAMPLER_MEMORY_LATENCY_STALL_XECORE26_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE27",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE27",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext301__sampler_memory_latency_stall_xecore27__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext301_SAMPLER_MEMORY_LATENCY_STALL_XECORE27_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE28",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE28",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext301__sampler_memory_latency_stall_xecore28__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext301_SAMPLER_MEMORY_LATENCY_STALL_XECORE28_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE29",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE29",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext301__sampler_memory_latency_stall_xecore29__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext301_SAMPLER_MEMORY_LATENCY_STALL_XECORE29_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE30",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE30",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext301__sampler_memory_latency_stall_xecore30__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext301_SAMPLER_MEMORY_LATENCY_STALL_XECORE30_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE31",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE31",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext301__sampler_memory_latency_stall_xecore31__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext301_SAMPLER_MEMORY_LATENCY_STALL_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext302_SAMPLER_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext302_SAMPLER_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext302_SAMPLER_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext302_SAMPLER_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext302_SAMPLER_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext302_SAMPLER_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext302_SAMPLER_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext302_SAMPLER_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext302_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext302";
    metric_set->symbol_name = "Ext302";
    metric_set->hw_config_guid = "7b0d1439-3ea4-48b4-97a7-934789bb750b";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext302_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext302__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext302__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext302__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext302__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE0",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext302__sampler_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext302_SAMPLER_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE1",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext302__sampler_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext302_SAMPLER_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE2",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext302__sampler_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext302_SAMPLER_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE3",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext302__sampler_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext302_SAMPLER_INPUT_AVAILABLE_XECORE3_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE4",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext302__sampler_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext302_SAMPLER_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE5",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext302__sampler_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext302_SAMPLER_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE6",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext302__sampler_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext302_SAMPLER_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE7",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext302__sampler_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext302_SAMPLER_INPUT_AVAILABLE_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext303_SAMPLER_INPUT_AVAILABLE_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext303_SAMPLER_INPUT_AVAILABLE_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext303_SAMPLER_INPUT_AVAILABLE_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext303_SAMPLER_INPUT_AVAILABLE_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext303_SAMPLER_INPUT_AVAILABLE_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext303_SAMPLER_INPUT_AVAILABLE_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext303_SAMPLER_INPUT_AVAILABLE_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext303_SAMPLER_INPUT_AVAILABLE_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext303_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext303";
    metric_set->symbol_name = "Ext303";
    metric_set->hw_config_guid = "ae51b0bc-1de2-472c-915c-ac570a5d25ca";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext303_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext303__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext303__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext303__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext303__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE10",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE10",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext303__sampler_input_available_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext303_SAMPLER_INPUT_AVAILABLE_XECORE10_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE11",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE11",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext303__sampler_input_available_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext303_SAMPLER_INPUT_AVAILABLE_XECORE11_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE12",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE12",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext303__sampler_input_available_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext303_SAMPLER_INPUT_AVAILABLE_XECORE12_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE13",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE13",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext303__sampler_input_available_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext303_SAMPLER_INPUT_AVAILABLE_XECORE13_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE14",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE14",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext303__sampler_input_available_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext303_SAMPLER_INPUT_AVAILABLE_XECORE14_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE15",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE15",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext303__sampler_input_available_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext303_SAMPLER_INPUT_AVAILABLE_XECORE15_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE8",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE8",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext303__sampler_input_available_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext303_SAMPLER_INPUT_AVAILABLE_XECORE8_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE9",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE9",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext303__sampler_input_available_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext303_SAMPLER_INPUT_AVAILABLE_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext304_SAMPLER_INPUT_AVAILABLE_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext304_SAMPLER_INPUT_AVAILABLE_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext304_SAMPLER_INPUT_AVAILABLE_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext304_SAMPLER_INPUT_AVAILABLE_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext304_SAMPLER_INPUT_AVAILABLE_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext304_SAMPLER_INPUT_AVAILABLE_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext304_SAMPLER_INPUT_AVAILABLE_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext304_SAMPLER_INPUT_AVAILABLE_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext304_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext304";
    metric_set->symbol_name = "Ext304";
    metric_set->hw_config_guid = "3e837b13-a03e-4f77-8bc0-bfdaed855b49";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext304_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext304__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext304__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext304__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext304__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE16",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE16",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext304__sampler_input_available_xecore16__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext304_SAMPLER_INPUT_AVAILABLE_XECORE16_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE17",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE17",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext304__sampler_input_available_xecore17__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext304_SAMPLER_INPUT_AVAILABLE_XECORE17_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE18",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE18",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext304__sampler_input_available_xecore18__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext304_SAMPLER_INPUT_AVAILABLE_XECORE18_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE19",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE19",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext304__sampler_input_available_xecore19__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext304_SAMPLER_INPUT_AVAILABLE_XECORE19_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE20",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE20",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext304__sampler_input_available_xecore20__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext304_SAMPLER_INPUT_AVAILABLE_XECORE20_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE21",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE21",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext304__sampler_input_available_xecore21__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext304_SAMPLER_INPUT_AVAILABLE_XECORE21_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE22",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE22",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext304__sampler_input_available_xecore22__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext304_SAMPLER_INPUT_AVAILABLE_XECORE22_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE23",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE23",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext304__sampler_input_available_xecore23__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext304_SAMPLER_INPUT_AVAILABLE_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext305_SAMPLER_INPUT_AVAILABLE_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext305_SAMPLER_INPUT_AVAILABLE_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext305_SAMPLER_INPUT_AVAILABLE_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext305_SAMPLER_INPUT_AVAILABLE_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext305_SAMPLER_INPUT_AVAILABLE_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext305_SAMPLER_INPUT_AVAILABLE_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext305_SAMPLER_INPUT_AVAILABLE_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext305_SAMPLER_INPUT_AVAILABLE_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext305_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext305";
    metric_set->symbol_name = "Ext305";
    metric_set->hw_config_guid = "793a787c-6646-4e56-8bfa-acca313d86f5";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext305_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext305__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext305__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext305__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext305__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE24",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE24",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext305__sampler_input_available_xecore24__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext305_SAMPLER_INPUT_AVAILABLE_XECORE24_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE25",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE25",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext305__sampler_input_available_xecore25__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext305_SAMPLER_INPUT_AVAILABLE_XECORE25_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE26",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE26",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext305__sampler_input_available_xecore26__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext305_SAMPLER_INPUT_AVAILABLE_XECORE26_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE27",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE27",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext305__sampler_input_available_xecore27__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext305_SAMPLER_INPUT_AVAILABLE_XECORE27_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE28",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE28",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext305__sampler_input_available_xecore28__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext305_SAMPLER_INPUT_AVAILABLE_XECORE28_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE29",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE29",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext305__sampler_input_available_xecore29__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext305_SAMPLER_INPUT_AVAILABLE_XECORE29_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE30",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE30",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext305__sampler_input_available_xecore30__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext305_SAMPLER_INPUT_AVAILABLE_XECORE30_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE31",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE31",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext305__sampler_input_available_xecore31__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt3_ext305_SAMPLER_INPUT_AVAILABLE_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext306_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext306";
    metric_set->symbol_name = "Ext306";
    metric_set->hw_config_guid = "e7767971-3cb4-4a31-8467-0d83cbe7b292";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext306_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext306__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext306__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext306__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext306__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE0",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE0",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext306__sampler_texture_cache_access_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE0_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE1",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE1",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext306__sampler_texture_cache_access_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE1_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE10",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE10",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext306__sampler_texture_cache_access_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE10_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE11",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE11",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext306__sampler_texture_cache_access_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE11_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE12",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE12",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext306__sampler_texture_cache_access_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE12_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE13",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE13",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext306__sampler_texture_cache_access_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE13_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE14",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE14",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext306__sampler_texture_cache_access_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE14_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE15",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE15",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext306__sampler_texture_cache_access_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE15_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE2",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE2",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext306__sampler_texture_cache_access_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE2_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE3",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE3",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext306__sampler_texture_cache_access_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE3_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE4",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE4",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext306__sampler_texture_cache_access_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE4_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE5",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE5",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext306__sampler_texture_cache_access_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE5_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE6",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE6",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext306__sampler_texture_cache_access_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE6_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE7",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE7",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext306__sampler_texture_cache_access_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE7_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE8",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE8",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext306__sampler_texture_cache_access_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE8_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE9",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE9",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext306__sampler_texture_cache_access_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext306_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext307_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext307";
    metric_set->symbol_name = "Ext307";
    metric_set->hw_config_guid = "9375cccf-e4b4-44cc-b6af-ffc2f51c3bb1";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext307_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext307__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext307__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext307__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext307__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE16",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE16",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext307__sampler_texture_cache_access_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE16_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE17",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE17",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext307__sampler_texture_cache_access_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE17_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE18",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE18",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext307__sampler_texture_cache_access_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE18_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE19",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE19",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext307__sampler_texture_cache_access_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE19_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE20",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE20",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext307__sampler_texture_cache_access_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE20_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE21",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE21",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext307__sampler_texture_cache_access_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE21_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE22",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE22",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext307__sampler_texture_cache_access_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE22_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE23",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE23",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext307__sampler_texture_cache_access_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE23_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE24",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE24",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext307__sampler_texture_cache_access_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE24_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE25",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE25",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext307__sampler_texture_cache_access_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE25_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE26",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE26",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext307__sampler_texture_cache_access_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE26_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE27",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE27",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext307__sampler_texture_cache_access_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE27_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE28",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE28",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext307__sampler_texture_cache_access_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE28_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE29",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE29",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext307__sampler_texture_cache_access_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE29_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE30",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE30",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext307__sampler_texture_cache_access_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE30_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE31",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE31",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext307__sampler_texture_cache_access_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext307_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext308_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext308";
    metric_set->symbol_name = "Ext308";
    metric_set->hw_config_guid = "0218e76e-7c34-4c67-a967-205a817f2435";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext308_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext308__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext308__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext308__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext308__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE0",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE0",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext308__sampler_texture_cache_miss_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE0_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE1",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE1",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext308__sampler_texture_cache_miss_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE1_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE10",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE10",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext308__sampler_texture_cache_miss_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE10_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE11",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE11",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext308__sampler_texture_cache_miss_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE11_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE12",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE12",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext308__sampler_texture_cache_miss_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE12_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE13",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE13",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext308__sampler_texture_cache_miss_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE13_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE14",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE14",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext308__sampler_texture_cache_miss_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE14_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE15",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE15",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext308__sampler_texture_cache_miss_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE15_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE2",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE2",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext308__sampler_texture_cache_miss_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE2_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE3",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE3",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext308__sampler_texture_cache_miss_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE3_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE4",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE4",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext308__sampler_texture_cache_miss_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE4_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE5",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE5",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext308__sampler_texture_cache_miss_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE5_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE6",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE6",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext308__sampler_texture_cache_miss_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE6_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE7",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE7",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext308__sampler_texture_cache_miss_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE7_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE8",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE8",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext308__sampler_texture_cache_miss_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE8_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE9",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE9",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext308__sampler_texture_cache_miss_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext308_SAMPLER_TEXTURE_CACHE_MISS_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext309_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext309";
    metric_set->symbol_name = "Ext309";
    metric_set->hw_config_guid = "7a2ef8ea-0510-4066-b7de-0af99bf5b0b7";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext309_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext309__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext309__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext309__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext309__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE16",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE16",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext309__sampler_texture_cache_miss_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE16_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE17",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE17",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext309__sampler_texture_cache_miss_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE17_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE18",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE18",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext309__sampler_texture_cache_miss_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE18_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE19",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE19",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext309__sampler_texture_cache_miss_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE19_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE20",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE20",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext309__sampler_texture_cache_miss_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE20_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE21",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE21",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext309__sampler_texture_cache_miss_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE21_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE22",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE22",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext309__sampler_texture_cache_miss_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE22_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE23",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE23",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext309__sampler_texture_cache_miss_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE23_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE24",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE24",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext309__sampler_texture_cache_miss_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE24_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE25",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE25",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext309__sampler_texture_cache_miss_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE25_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE26",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE26",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext309__sampler_texture_cache_miss_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE26_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE27",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE27",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext309__sampler_texture_cache_miss_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE27_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE28",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE28",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext309__sampler_texture_cache_miss_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE28_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE29",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE29",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext309__sampler_texture_cache_miss_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE29_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE30",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE30",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext309__sampler_texture_cache_miss_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE30_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE31",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE31",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext309__sampler_texture_cache_miss_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt3_ext309_SAMPLER_TEXTURE_CACHE_MISS_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext310_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext310_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext310_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext310_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext310_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext310";
    metric_set->symbol_name = "Ext310";
    metric_set->hw_config_guid = "7f6f2cd5-235a-4479-9724-98bc76338071";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext310_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext310__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext310__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext310__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext310__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE0",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext310__xve_dataport_read_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext310_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE1",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext310__xve_dataport_read_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext310_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE2",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext310__xve_dataport_read_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext310_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE3",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext310__xve_dataport_read_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext310_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext311_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext311_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext311_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext311_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext311_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext311";
    metric_set->symbol_name = "Ext311";
    metric_set->hw_config_guid = "cd5aacba-f72a-44f7-8794-ce2bcf92ec1f";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext311_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext311__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext311__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext311__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext311__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE4",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext311__xve_dataport_read_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext311_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE5",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext311__xve_dataport_read_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext311_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE6",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext311__xve_dataport_read_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext311_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE7",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext311__xve_dataport_read_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext311_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext312_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext312_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext312_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext312_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext312_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext312";
    metric_set->symbol_name = "Ext312";
    metric_set->hw_config_guid = "a2f9ee62-175a-4c99-ad05-daa5dd83c268";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext312_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext312__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext312__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext312__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext312__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE10",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE10",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext312__xve_dataport_read_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext312_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE11",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE11",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext312__xve_dataport_read_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext312_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE11_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE8",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE8",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext312__xve_dataport_read_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext312_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE9",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE9",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext312__xve_dataport_read_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext312_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext313_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext313_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext313_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext313_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext313_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext313";
    metric_set->symbol_name = "Ext313";
    metric_set->hw_config_guid = "8cc89495-676d-46a3-aa5a-d5e50bd8b547";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext313_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext313__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext313__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext313__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext313__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE12",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE12",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext313__xve_dataport_read_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext313_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE13",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE13",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext313__xve_dataport_read_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext313_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE13_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE14",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE14",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext313__xve_dataport_read_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext313_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE15",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE15",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext313__xve_dataport_read_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext313_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext314_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext314_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext314_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext314_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext314_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext314";
    metric_set->symbol_name = "Ext314";
    metric_set->hw_config_guid = "6a9b6d4b-0ad5-410b-ab23-a755c2069502";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext314_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext314__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext314__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext314__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext314__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE16",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE16",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext314__xve_dataport_read_message_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext314_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE16_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE17",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE17",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext314__xve_dataport_read_message_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext314_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE17_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE18",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE18",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext314__xve_dataport_read_message_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext314_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE18_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE19",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE19",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext314__xve_dataport_read_message_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext314_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext315_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext315_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext315_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext315_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext315_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext315";
    metric_set->symbol_name = "Ext315";
    metric_set->hw_config_guid = "ff1b4077-1346-45a5-acae-d08e7651e126";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext315_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext315__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext315__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext315__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext315__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE20",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE20",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext315__xve_dataport_read_message_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext315_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE20_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE21",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE21",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext315__xve_dataport_read_message_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext315_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE21_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE22",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE22",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext315__xve_dataport_read_message_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext315_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE22_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE23",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE23",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext315__xve_dataport_read_message_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext315_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext316_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext316_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext316_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext316_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext316_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext316";
    metric_set->symbol_name = "Ext316";
    metric_set->hw_config_guid = "d4367f9e-ceaa-4751-91de-c80918a32d0e";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext316_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext316__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext316__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext316__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext316__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE24",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE24",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext316__xve_dataport_read_message_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext316_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE24_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE25",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE25",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext316__xve_dataport_read_message_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext316_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE25_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE26",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE26",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext316__xve_dataport_read_message_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext316_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE26_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE27",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE27",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext316__xve_dataport_read_message_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext316_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext317_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext317_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext317_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext317_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext317_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext317";
    metric_set->symbol_name = "Ext317";
    metric_set->hw_config_guid = "ea24cfe9-dca1-4520-b55a-78ac4b9c94b5";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext317_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext317__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext317__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext317__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext317__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE28",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE28",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext317__xve_dataport_read_message_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext317_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE28_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE29",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE29",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext317__xve_dataport_read_message_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext317_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE29_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE30",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE30",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext317__xve_dataport_read_message_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext317_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE30_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE31",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE31",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext317__xve_dataport_read_message_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext317_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext318_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext318_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext318_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext318_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext318_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext318";
    metric_set->symbol_name = "Ext318";
    metric_set->hw_config_guid = "570970cb-b1ae-499e-9113-73b1489bebe7";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext318_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext318__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext318__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext318__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext318__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE0",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext318__xve_dataport_write_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext318_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE1",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext318__xve_dataport_write_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext318_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE2",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext318__xve_dataport_write_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext318_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE3",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext318__xve_dataport_write_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext318_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext319_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext319_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext319_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext319_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext319_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext319";
    metric_set->symbol_name = "Ext319";
    metric_set->hw_config_guid = "a2b926df-458d-4580-99d9-731b9e9024b1";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext319_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext319__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext319__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext319__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext319__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE4",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext319__xve_dataport_write_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext319_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE5",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext319__xve_dataport_write_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext319_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE6",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext319__xve_dataport_write_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext319_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE7",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext319__xve_dataport_write_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext319_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext320_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext320_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext320_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext320_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext320_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext320";
    metric_set->symbol_name = "Ext320";
    metric_set->hw_config_guid = "b357c635-b799-46d2-8714-4f4fddffe2e9";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext320_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext320__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext320__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext320__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext320__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE10",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE10",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext320__xve_dataport_write_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext320_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE11",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE11",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext320__xve_dataport_write_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext320_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE11_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE8",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE8",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext320__xve_dataport_write_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext320_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE9",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE9",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext320__xve_dataport_write_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext320_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext321_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext321_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext321_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext321_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext321_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext321";
    metric_set->symbol_name = "Ext321";
    metric_set->hw_config_guid = "a8c3e950-b343-4f27-a434-a49ba7c87254";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext321_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext321__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext321__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext321__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext321__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE12",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE12",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext321__xve_dataport_write_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext321_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE13",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE13",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext321__xve_dataport_write_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext321_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE13_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE14",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE14",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext321__xve_dataport_write_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext321_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE15",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE15",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext321__xve_dataport_write_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext321_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext322_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext322_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext322_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext322_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext322_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext322";
    metric_set->symbol_name = "Ext322";
    metric_set->hw_config_guid = "be052c4e-a835-42da-9b67-3917052ada60";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext322_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext322__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext322__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext322__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext322__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE16",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE16",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext322__xve_dataport_write_message_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext322_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE16_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE17",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE17",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext322__xve_dataport_write_message_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext322_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE17_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE18",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE18",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext322__xve_dataport_write_message_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext322_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE18_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE19",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE19",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext322__xve_dataport_write_message_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext322_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext323_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext323_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext323_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext323_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext323_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext323";
    metric_set->symbol_name = "Ext323";
    metric_set->hw_config_guid = "d911722e-b0cd-4b54-92e5-d98dda5b6c90";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext323_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext323__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext323__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext323__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext323__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE20",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE20",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext323__xve_dataport_write_message_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext323_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE20_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE21",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE21",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext323__xve_dataport_write_message_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext323_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE21_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE22",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE22",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext323__xve_dataport_write_message_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext323_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE22_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE23",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE23",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext323__xve_dataport_write_message_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext323_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext324_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext324_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext324_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext324_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext324_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext324";
    metric_set->symbol_name = "Ext324";
    metric_set->hw_config_guid = "0bc72c8f-65c2-4ab7-acd8-c65a40a707ac";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext324_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext324__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext324__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext324__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext324__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE24",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE24",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext324__xve_dataport_write_message_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext324_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE24_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE25",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE25",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext324__xve_dataport_write_message_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext324_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE25_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE26",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE26",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext324__xve_dataport_write_message_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext324_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE26_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE27",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE27",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext324__xve_dataport_write_message_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext324_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext325_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext325_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext325_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext325_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext325_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext325";
    metric_set->symbol_name = "Ext325";
    metric_set->hw_config_guid = "86524707-6f59-4929-ac15-a293133850b0";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext325_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext325__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext325__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext325__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext325__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE28",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE28",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext325__xve_dataport_write_message_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext325_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE28_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE29",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE29",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext325__xve_dataport_write_message_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext325_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE29_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE30",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE30",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext325__xve_dataport_write_message_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext325_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE30_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE31",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE31",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext325__xve_dataport_write_message_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext325_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext326_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext326_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext326_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext326_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext326_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext326";
    metric_set->symbol_name = "Ext326";
    metric_set->hw_config_guid = "199027ff-3c22-42d5-a543-a9467be1422c";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext326_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext326__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext326__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext326__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext326__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE0",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext326__xve_dataport_atomic_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext326_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE1",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext326__xve_dataport_atomic_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext326_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE2",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext326__xve_dataport_atomic_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext326_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE3",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext326__xve_dataport_atomic_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext326_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext327_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext327_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext327_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext327_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext327_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext327";
    metric_set->symbol_name = "Ext327";
    metric_set->hw_config_guid = "38473fe1-ab75-4be0-9cef-c9d84a803787";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext327_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext327__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext327__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext327__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext327__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE4",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext327__xve_dataport_atomic_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext327_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE5",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext327__xve_dataport_atomic_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext327_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE6",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext327__xve_dataport_atomic_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext327_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE7",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext327__xve_dataport_atomic_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext327_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext328_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext328_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext328_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext328_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext328_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext328";
    metric_set->symbol_name = "Ext328";
    metric_set->hw_config_guid = "4500f1fd-d762-4a31-88fd-17ae40ee0727";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext328_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext328__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext328__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext328__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext328__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE10",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE10",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext328__xve_dataport_atomic_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext328_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE11",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE11",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext328__xve_dataport_atomic_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext328_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE11_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE8",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE8",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext328__xve_dataport_atomic_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext328_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE9",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE9",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext328__xve_dataport_atomic_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext328_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext329_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext329_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext329_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext329_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext329_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext329";
    metric_set->symbol_name = "Ext329";
    metric_set->hw_config_guid = "2458839a-476e-4804-ba6b-a3d06323b800";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext329_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext329__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext329__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext329__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext329__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE12",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE12",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext329__xve_dataport_atomic_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext329_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE13",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE13",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext329__xve_dataport_atomic_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext329_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE13_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE14",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE14",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext329__xve_dataport_atomic_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext329_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE15",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE15",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext329__xve_dataport_atomic_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext329_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext330_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext330_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext330_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext330_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext330_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext330";
    metric_set->symbol_name = "Ext330";
    metric_set->hw_config_guid = "9aa833d4-ba51-487b-a586-a0df6d462909";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext330_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext330__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext330__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext330__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext330__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE16",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE16",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext330__xve_dataport_atomic_message_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext330_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE16_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE17",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE17",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext330__xve_dataport_atomic_message_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext330_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE17_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE18",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE18",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext330__xve_dataport_atomic_message_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext330_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE18_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE19",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE19",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext330__xve_dataport_atomic_message_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext330_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext331_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext331_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext331_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext331_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext331_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext331";
    metric_set->symbol_name = "Ext331";
    metric_set->hw_config_guid = "1ca59138-4493-4e1e-bf2d-452da6a50597";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext331_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext331__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext331__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext331__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext331__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE20",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE20",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext331__xve_dataport_atomic_message_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext331_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE20_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE21",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE21",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext331__xve_dataport_atomic_message_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext331_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE21_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE22",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE22",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext331__xve_dataport_atomic_message_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext331_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE22_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE23",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE23",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext331__xve_dataport_atomic_message_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext331_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext332_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext332_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext332_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext332_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext332_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext332";
    metric_set->symbol_name = "Ext332";
    metric_set->hw_config_guid = "88514dd5-9e66-457e-9493-8ffc78893322";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext332_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext332__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext332__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext332__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext332__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE24",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE24",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext332__xve_dataport_atomic_message_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext332_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE24_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE25",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE25",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext332__xve_dataport_atomic_message_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext332_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE25_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE26",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE26",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext332__xve_dataport_atomic_message_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext332_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE26_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE27",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE27",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext332__xve_dataport_atomic_message_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext332_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext333_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext333_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext333_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext333_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext333_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext333";
    metric_set->symbol_name = "Ext333";
    metric_set->hw_config_guid = "38fcb336-fc63-4e5e-aa3e-a40f7feb693a";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext333_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext333__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext333__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext333__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext333__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE28",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE28",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext333__xve_dataport_atomic_message_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext333_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE28_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE29",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE29",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext333__xve_dataport_atomic_message_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext333_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE29_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE30",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE30",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext333__xve_dataport_atomic_message_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext333_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE30_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE31",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE31",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext333__xve_dataport_atomic_message_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext333_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext334_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext334";
    metric_set->symbol_name = "Ext334";
    metric_set->hw_config_guid = "b8a9ea64-362d-473b-b9d7-a2175179a0a0";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext334_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext334__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext334__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext334__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext334__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE0",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext334__xve_dataport_fence_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE1",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext334__xve_dataport_fence_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE10",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE10",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext334__xve_dataport_fence_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE11",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE11",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext334__xve_dataport_fence_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE11_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE12",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE12",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext334__xve_dataport_fence_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE13",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE13",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext334__xve_dataport_fence_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE13_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE14",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE14",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext334__xve_dataport_fence_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE15",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE15",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext334__xve_dataport_fence_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE15_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE2",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext334__xve_dataport_fence_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE3",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext334__xve_dataport_fence_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE3_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE4",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext334__xve_dataport_fence_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE5",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext334__xve_dataport_fence_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE6",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext334__xve_dataport_fence_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE7",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext334__xve_dataport_fence_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE7_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE8",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE8",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext334__xve_dataport_fence_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE9",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE9",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext334__xve_dataport_fence_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext334_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext335_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext335";
    metric_set->symbol_name = "Ext335";
    metric_set->hw_config_guid = "6771c5d0-cc06-41ec-b5c9-7d4a8d657bd2";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext335_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext335__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext335__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext335__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext335__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE16",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE16",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext335__xve_dataport_fence_message_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE16_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE17",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE17",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext335__xve_dataport_fence_message_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE17_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE18",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE18",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext335__xve_dataport_fence_message_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE18_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE19",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE19",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext335__xve_dataport_fence_message_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE19_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE20",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE20",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext335__xve_dataport_fence_message_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE20_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE21",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE21",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext335__xve_dataport_fence_message_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE21_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE22",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE22",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext335__xve_dataport_fence_message_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE22_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE23",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE23",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext335__xve_dataport_fence_message_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE23_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE24",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE24",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext335__xve_dataport_fence_message_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE24_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE25",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE25",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext335__xve_dataport_fence_message_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE25_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE26",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE26",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext335__xve_dataport_fence_message_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE26_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE27",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE27",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext335__xve_dataport_fence_message_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE27_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE28",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE28",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext335__xve_dataport_fence_message_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE28_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE29",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE29",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext335__xve_dataport_fence_message_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE29_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE30",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE30",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext335__xve_dataport_fence_message_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE30_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE31",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE31",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext335__xve_dataport_fence_message_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext335_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext342_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext342_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext342_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext342_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext342_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext342_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext342_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext342_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext342_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext342";
    metric_set->symbol_name = "Ext342";
    metric_set->hw_config_guid = "c99de5cb-2a05-4d95-ae63-7465a9fde881";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext342_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext342__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext342__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext342__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext342__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE0",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE0",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext342__xve_dataport_register_request_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext342_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE1",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE1",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext342__xve_dataport_register_request_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext342_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE2",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE2",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext342__xve_dataport_register_request_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext342_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE3",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE3",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext342__xve_dataport_register_request_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext342_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE3_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE4",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE4",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext342__xve_dataport_register_request_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext342_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE5",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE5",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext342__xve_dataport_register_request_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext342_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE6",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE6",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext342__xve_dataport_register_request_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext342_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE7",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE7",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext342__xve_dataport_register_request_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext342_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext343_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext343_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext343_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext343_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext343_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext343_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext343_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext343_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext343_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext343";
    metric_set->symbol_name = "Ext343";
    metric_set->hw_config_guid = "c83a1e77-4edb-4157-86d2-8ae073b76783";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext343_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext343__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext343__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext343__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext343__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE10",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE10",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext343__xve_dataport_register_request_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext343_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE11",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE11",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext343__xve_dataport_register_request_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext343_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE11_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE12",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE12",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext343__xve_dataport_register_request_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext343_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE13",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE13",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext343__xve_dataport_register_request_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext343_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE13_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE14",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE14",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext343__xve_dataport_register_request_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext343_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE15",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE15",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext343__xve_dataport_register_request_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext343_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE15_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE8",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE8",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext343__xve_dataport_register_request_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext343_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE9",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE9",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext343__xve_dataport_register_request_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext343_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext344_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext344_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext344_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext344_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext344_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext344_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext344_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext344_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext344_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext344";
    metric_set->symbol_name = "Ext344";
    metric_set->hw_config_guid = "7bdaf544-993e-4a5e-8040-9391d9be562d";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext344_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext344__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext344__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext344__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext344__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE16",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE16",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext344__xve_dataport_register_request_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext344_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE16_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE17",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE17",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext344__xve_dataport_register_request_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext344_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE17_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE18",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE18",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext344__xve_dataport_register_request_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext344_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE18_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE19",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE19",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext344__xve_dataport_register_request_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext344_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE19_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE20",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE20",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext344__xve_dataport_register_request_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext344_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE20_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE21",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE21",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext344__xve_dataport_register_request_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext344_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE21_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE22",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE22",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext344__xve_dataport_register_request_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext344_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE22_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE23",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE23",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext344__xve_dataport_register_request_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext344_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext345_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext345_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext345_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext345_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext345_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext345_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext345_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext345_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext345_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext345";
    metric_set->symbol_name = "Ext345";
    metric_set->hw_config_guid = "7e311c03-26ed-437c-9f60-28d92df03534";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext345_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext345__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext345__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext345__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext345__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE24",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE24",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext345__xve_dataport_register_request_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext345_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE24_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE25",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE25",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext345__xve_dataport_register_request_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext345_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE25_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE26",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE26",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext345__xve_dataport_register_request_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext345_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE26_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE27",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE27",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext345__xve_dataport_register_request_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext345_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE27_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE28",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE28",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext345__xve_dataport_register_request_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext345_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE28_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE29",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE29",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext345__xve_dataport_register_request_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext345_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE29_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE30",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE30",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext345__xve_dataport_register_request_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext345_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE30_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE31",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE31",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext345__xve_dataport_register_request_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext345_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext346_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext346_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext346_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext346";
    metric_set->symbol_name = "Ext346";
    metric_set->hw_config_guid = "e7738d4d-64e4-4a54-81a3-86702c6fdb47";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext346_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext346__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext346__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext346__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext346__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE0",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE0",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext346__xve_dataport_register_response_count_xecore0__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext346_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE1",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE1",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext346__xve_dataport_register_response_count_xecore1__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext346_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext347_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext347_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext347_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext347";
    metric_set->symbol_name = "Ext347";
    metric_set->hw_config_guid = "bc487d2d-a32a-48d7-bce8-96b19d7853ec";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext347_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext347__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext347__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext347__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext347__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE2",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE2",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext347__xve_dataport_register_response_count_xecore2__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext347_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE3",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE3",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext347__xve_dataport_register_response_count_xecore3__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext347_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext348_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext348_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext348_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext348";
    metric_set->symbol_name = "Ext348";
    metric_set->hw_config_guid = "434a0292-cb9f-46aa-acec-fb56af5aacec";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext348_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext348__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext348__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext348__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext348__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE4",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE4",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext348__xve_dataport_register_response_count_xecore4__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext348_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE5",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE5",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext348__xve_dataport_register_response_count_xecore5__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext348_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext349_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext349_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext349_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext349";
    metric_set->symbol_name = "Ext349";
    metric_set->hw_config_guid = "cf3716ea-68c0-470b-b2ed-07dcad433550";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext349_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext349__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext349__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext349__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext349__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE6",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE6",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext349__xve_dataport_register_response_count_xecore6__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext349_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE7",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE7",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext349__xve_dataport_register_response_count_xecore7__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext349_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext350_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext350_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext350_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext350";
    metric_set->symbol_name = "Ext350";
    metric_set->hw_config_guid = "0233f2f1-7ba2-4419-a8e8-90028db78f6b";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext350_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext350__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext350__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext350__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext350__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE8",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE8",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext350__xve_dataport_register_response_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext350_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE8_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE9",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE9",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext350__xve_dataport_register_response_count_xecore9__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext350_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext351_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext351_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext351_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext351";
    metric_set->symbol_name = "Ext351";
    metric_set->hw_config_guid = "86fb99a2-94a0-4830-bd6e-f22db96c9f9f";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext351_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext351__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext351__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext351__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext351__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE10",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE10",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext351__xve_dataport_register_response_count_xecore10__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext351_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE10_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE11",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE11",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext351__xve_dataport_register_response_count_xecore11__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext351_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext352_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext352_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext352_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext352";
    metric_set->symbol_name = "Ext352";
    metric_set->hw_config_guid = "f189613f-66ee-466c-8ede-7fe9319d4aa0";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext352_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext352__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext352__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext352__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext352__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE12",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE12",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext352__xve_dataport_register_response_count_xecore12__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext352_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE12_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE13",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE13",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext352__xve_dataport_register_response_count_xecore13__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext352_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext353_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext353_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext353_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext353";
    metric_set->symbol_name = "Ext353";
    metric_set->hw_config_guid = "0f278998-80a9-4e06-8f01-3d59e0bbfb4b";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext353_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext353__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext353__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext353__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext353__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE14",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE14",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext353__xve_dataport_register_response_count_xecore14__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext353_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE14_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE15",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE15",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext353__xve_dataport_register_response_count_xecore15__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext353_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext354_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext354_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext354_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext354";
    metric_set->symbol_name = "Ext354";
    metric_set->hw_config_guid = "9a3c0284-c012-4094-80ed-bfb46ab762a6";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext354_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext354__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext354__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext354__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext354__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE16",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE16",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext354__xve_dataport_register_response_count_xecore16__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext354_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE16_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE17",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE17",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext354__xve_dataport_register_response_count_xecore17__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext354_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE17_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext355_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext355_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext355_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext355";
    metric_set->symbol_name = "Ext355";
    metric_set->hw_config_guid = "21ebf724-d9a5-473d-a173-04923a9014fa";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext355_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext355__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext355__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext355__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext355__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE18",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE18",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext355__xve_dataport_register_response_count_xecore18__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext355_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE18_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE19",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE19",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext355__xve_dataport_register_response_count_xecore19__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext355_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext356_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext356_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext356_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext356";
    metric_set->symbol_name = "Ext356";
    metric_set->hw_config_guid = "44f5ade0-0120-4af2-9748-1bf550c3550e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext356_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext356__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext356__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext356__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext356__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE20",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE20",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext356__xve_dataport_register_response_count_xecore20__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext356_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE20_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE21",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE21",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext356__xve_dataport_register_response_count_xecore21__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext356_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE21_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext357_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext357_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext357_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext357";
    metric_set->symbol_name = "Ext357";
    metric_set->hw_config_guid = "feda9279-042d-4ad4-9d09-b08448fb71e2";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext357_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext357__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext357__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext357__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext357__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE22",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE22",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext357__xve_dataport_register_response_count_xecore22__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext357_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE22_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE23",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE23",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext357__xve_dataport_register_response_count_xecore23__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext357_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext358_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext358_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext358_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext358";
    metric_set->symbol_name = "Ext358";
    metric_set->hw_config_guid = "287a8880-aa97-4a61-bd9c-c4ea26cac685";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext358_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext358__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext358__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext358__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext358__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE24",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE24",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext358__xve_dataport_register_response_count_xecore24__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext358_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE24_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE25",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE25",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext358__xve_dataport_register_response_count_xecore25__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext358_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE25_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext359_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext359_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext359_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext359";
    metric_set->symbol_name = "Ext359";
    metric_set->hw_config_guid = "6ec0ccb7-2c59-4c56-a541-5cae1577ccef";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext359_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext359__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext359__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext359__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext359__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE26",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE26",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext359__xve_dataport_register_response_count_xecore26__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext359_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE26_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE27",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE27",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext359__xve_dataport_register_response_count_xecore27__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext359_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext360_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext360_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext360_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext360";
    metric_set->symbol_name = "Ext360";
    metric_set->hw_config_guid = "3c210e69-5238-4d7f-a875-5526e0d10784";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext360_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext360__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext360__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext360__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext360__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE28",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE28",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext360__xve_dataport_register_response_count_xecore28__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext360_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE28_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE29",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE29",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext360__xve_dataport_register_response_count_xecore29__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext360_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE29_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext361_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext361_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext361_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext361";
    metric_set->symbol_name = "Ext361";
    metric_set->hw_config_guid = "3c9d3497-fa1a-4120-86fd-3b5c6dce0608";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext361_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext361__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext361__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext361__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext361__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE30",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE30",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext361__xve_dataport_register_response_count_xecore30__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext361_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE30_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE31",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE31",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt3__ext361__xve_dataport_register_response_count_xecore31__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext361_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext362_DATAPORT_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext362_DATAPORT_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext362_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext362";
    metric_set->symbol_name = "Ext362";
    metric_set->hw_config_guid = "176224fc-33cb-480b-90b8-91225247a303";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext362_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext362__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext362__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE0",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext362__dataport_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext362_DATAPORT_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE1",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext362__dataport_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext362_DATAPORT_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext362__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext362__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext363_DATAPORT_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext363_DATAPORT_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext363_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext363";
    metric_set->symbol_name = "Ext363";
    metric_set->hw_config_guid = "496b0c36-4849-4398-aad8-131402b38b41";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext363_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext363__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext363__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE2",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext363__dataport_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext363_DATAPORT_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE3",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext363__dataport_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext363_DATAPORT_INPUT_AVAILABLE_XECORE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext363__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext363__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext364_DATAPORT_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext364_DATAPORT_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext364_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext364";
    metric_set->symbol_name = "Ext364";
    metric_set->hw_config_guid = "0a0b4d5c-4cc0-4f18-84b7-bca6fde241b4";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext364_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext364__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext364__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE4",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext364__dataport_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext364_DATAPORT_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE5",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext364__dataport_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext364_DATAPORT_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext364__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext364__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext365_DATAPORT_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext365_DATAPORT_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext365_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext365";
    metric_set->symbol_name = "Ext365";
    metric_set->hw_config_guid = "a726bcbf-febf-4840-8d84-d4e6ce3a7fb0";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext365_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext365__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext365__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE6",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext365__dataport_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext365_DATAPORT_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE7",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext365__dataport_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext365_DATAPORT_INPUT_AVAILABLE_XECORE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext365__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext365__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext366_DATAPORT_INPUT_AVAILABLE_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext366_DATAPORT_INPUT_AVAILABLE_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext366_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext366";
    metric_set->symbol_name = "Ext366";
    metric_set->hw_config_guid = "14001989-7d14-47a5-bd85-d1d2b11d15c1";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext366_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext366__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext366__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE8",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE8",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext366__dataport_input_available_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext366_DATAPORT_INPUT_AVAILABLE_XECORE8_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE9",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE9",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext366__dataport_input_available_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext366_DATAPORT_INPUT_AVAILABLE_XECORE9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext366__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext366__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext367_DATAPORT_INPUT_AVAILABLE_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext367_DATAPORT_INPUT_AVAILABLE_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext367_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext367";
    metric_set->symbol_name = "Ext367";
    metric_set->hw_config_guid = "421c3eb4-c4fc-4a3b-91b3-87a99603466e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext367_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext367__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext367__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE10",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE10",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext367__dataport_input_available_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext367_DATAPORT_INPUT_AVAILABLE_XECORE10_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE11",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE11",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext367__dataport_input_available_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext367_DATAPORT_INPUT_AVAILABLE_XECORE11_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext367__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext367__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext368_DATAPORT_INPUT_AVAILABLE_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext368_DATAPORT_INPUT_AVAILABLE_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext368_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext368";
    metric_set->symbol_name = "Ext368";
    metric_set->hw_config_guid = "854ec412-1ca6-4628-a51c-620c0c9297df";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext368_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext368__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext368__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE12",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE12",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext368__dataport_input_available_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext368_DATAPORT_INPUT_AVAILABLE_XECORE12_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE13",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE13",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext368__dataport_input_available_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext368_DATAPORT_INPUT_AVAILABLE_XECORE13_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext368__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext368__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext369_DATAPORT_INPUT_AVAILABLE_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext369_DATAPORT_INPUT_AVAILABLE_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext369_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext369";
    metric_set->symbol_name = "Ext369";
    metric_set->hw_config_guid = "02175256-9f81-41d6-97e1-ace9e4e4cd45";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext369_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext369__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext369__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE14",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE14",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext369__dataport_input_available_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext369_DATAPORT_INPUT_AVAILABLE_XECORE14_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE15",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE15",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext369__dataport_input_available_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext369_DATAPORT_INPUT_AVAILABLE_XECORE15_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext369__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext369__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext370_DATAPORT_INPUT_AVAILABLE_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext370_DATAPORT_INPUT_AVAILABLE_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext370_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext370";
    metric_set->symbol_name = "Ext370";
    metric_set->hw_config_guid = "5a99d803-48ba-4b76-b689-58bf406ceaa5";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext370_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext370__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext370__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE16",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE16",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext370__dataport_input_available_xecore16__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext370_DATAPORT_INPUT_AVAILABLE_XECORE16_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE17",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE17",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext370__dataport_input_available_xecore17__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext370_DATAPORT_INPUT_AVAILABLE_XECORE17_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext370__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext370__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext371_DATAPORT_INPUT_AVAILABLE_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext371_DATAPORT_INPUT_AVAILABLE_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext371_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext371";
    metric_set->symbol_name = "Ext371";
    metric_set->hw_config_guid = "64b5963c-65cc-4216-8f23-d96e4268dca8";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext371_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext371__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext371__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE18",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE18",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext371__dataport_input_available_xecore18__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext371_DATAPORT_INPUT_AVAILABLE_XECORE18_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE19",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE19",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext371__dataport_input_available_xecore19__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext371_DATAPORT_INPUT_AVAILABLE_XECORE19_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext371__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext371__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext372_DATAPORT_INPUT_AVAILABLE_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext372_DATAPORT_INPUT_AVAILABLE_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext372_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext372";
    metric_set->symbol_name = "Ext372";
    metric_set->hw_config_guid = "7cf2bd19-9c7c-48df-8080-04b324c1a205";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext372_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext372__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext372__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE20",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE20",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext372__dataport_input_available_xecore20__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext372_DATAPORT_INPUT_AVAILABLE_XECORE20_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE21",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE21",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext372__dataport_input_available_xecore21__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext372_DATAPORT_INPUT_AVAILABLE_XECORE21_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext372__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext372__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext373_DATAPORT_INPUT_AVAILABLE_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext373_DATAPORT_INPUT_AVAILABLE_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext373_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext373";
    metric_set->symbol_name = "Ext373";
    metric_set->hw_config_guid = "2ac3ef91-7515-4519-a5bd-743564e52e46";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext373_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext373__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext373__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE22",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE22",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext373__dataport_input_available_xecore22__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext373_DATAPORT_INPUT_AVAILABLE_XECORE22_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE23",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE23",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext373__dataport_input_available_xecore23__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext373_DATAPORT_INPUT_AVAILABLE_XECORE23_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext373__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext373__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext374_DATAPORT_INPUT_AVAILABLE_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext374_DATAPORT_INPUT_AVAILABLE_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext374_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext374";
    metric_set->symbol_name = "Ext374";
    metric_set->hw_config_guid = "1bd48e5e-2efa-4f4c-b8c1-7600113347ce";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext374_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext374__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext374__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE24",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE24",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext374__dataport_input_available_xecore24__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext374_DATAPORT_INPUT_AVAILABLE_XECORE24_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE25",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE25",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext374__dataport_input_available_xecore25__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext374_DATAPORT_INPUT_AVAILABLE_XECORE25_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext374__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext374__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext375_DATAPORT_INPUT_AVAILABLE_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext375_DATAPORT_INPUT_AVAILABLE_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext375_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext375";
    metric_set->symbol_name = "Ext375";
    metric_set->hw_config_guid = "e3e63d50-a2dd-4880-899b-fc676a87853d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext375_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext375__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext375__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE26",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE26",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext375__dataport_input_available_xecore26__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext375_DATAPORT_INPUT_AVAILABLE_XECORE26_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE27",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE27",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext375__dataport_input_available_xecore27__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext375_DATAPORT_INPUT_AVAILABLE_XECORE27_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext375__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext375__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext376_DATAPORT_INPUT_AVAILABLE_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext376_DATAPORT_INPUT_AVAILABLE_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext376_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext376";
    metric_set->symbol_name = "Ext376";
    metric_set->hw_config_guid = "eb0b8725-7fc3-481c-b4ce-c53f32c8e828";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext376_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext376__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext376__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE28",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE28",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext376__dataport_input_available_xecore28__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext376_DATAPORT_INPUT_AVAILABLE_XECORE28_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE29",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE29",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext376__dataport_input_available_xecore29__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext376_DATAPORT_INPUT_AVAILABLE_XECORE29_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext376__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext376__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext377_DATAPORT_INPUT_AVAILABLE_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext377_DATAPORT_INPUT_AVAILABLE_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext377_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext377";
    metric_set->symbol_name = "Ext377";
    metric_set->hw_config_guid = "dcb8bd26-ed68-483d-b0c9-41a81b3717dd";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext377_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext377__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext377__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE30",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE30",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext377__dataport_input_available_xecore30__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext377_DATAPORT_INPUT_AVAILABLE_XECORE30_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE31",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE31",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext377__dataport_input_available_xecore31__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext377_DATAPORT_INPUT_AVAILABLE_XECORE31_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext377__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext377__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext378_DATAPORT_OUTPUT_READY_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext378_DATAPORT_OUTPUT_READY_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext378_DATAPORT_OUTPUT_READY_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext378_DATAPORT_OUTPUT_READY_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext378_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext378";
    metric_set->symbol_name = "Ext378";
    metric_set->hw_config_guid = "2e0b9ef7-89fc-4a49-b8e9-53f2c4c17e1b";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext378_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext378__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext378__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE0",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE0",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext378__dataport_output_ready_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext378_DATAPORT_OUTPUT_READY_XECORE0_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE1",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE1",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext378__dataport_output_ready_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext378_DATAPORT_OUTPUT_READY_XECORE1_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE2",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE2",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext378__dataport_output_ready_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext378_DATAPORT_OUTPUT_READY_XECORE2_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE3",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE3",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext378__dataport_output_ready_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext378_DATAPORT_OUTPUT_READY_XECORE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext378__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext378__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext379_DATAPORT_OUTPUT_READY_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext379_DATAPORT_OUTPUT_READY_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext379_DATAPORT_OUTPUT_READY_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext379_DATAPORT_OUTPUT_READY_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext379_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext379";
    metric_set->symbol_name = "Ext379";
    metric_set->hw_config_guid = "08199543-f47a-47ac-ae63-c384083ef85d";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext379_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext379__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext379__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE4",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE4",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext379__dataport_output_ready_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext379_DATAPORT_OUTPUT_READY_XECORE4_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE5",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE5",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext379__dataport_output_ready_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext379_DATAPORT_OUTPUT_READY_XECORE5_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE6",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE6",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext379__dataport_output_ready_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext379_DATAPORT_OUTPUT_READY_XECORE6_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE7",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE7",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext379__dataport_output_ready_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext379_DATAPORT_OUTPUT_READY_XECORE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext379__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext379__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext380_DATAPORT_OUTPUT_READY_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext380_DATAPORT_OUTPUT_READY_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext380_DATAPORT_OUTPUT_READY_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext380_DATAPORT_OUTPUT_READY_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext380_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext380";
    metric_set->symbol_name = "Ext380";
    metric_set->hw_config_guid = "7f7a14d6-3e61-478e-a4a1-8c6cfe0eb323";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext380_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext380__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext380__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE10",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE10",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext380__dataport_output_ready_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext380_DATAPORT_OUTPUT_READY_XECORE10_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE11",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE11",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext380__dataport_output_ready_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext380_DATAPORT_OUTPUT_READY_XECORE11_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE8",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE8",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext380__dataport_output_ready_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext380_DATAPORT_OUTPUT_READY_XECORE8_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE9",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE9",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext380__dataport_output_ready_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext380_DATAPORT_OUTPUT_READY_XECORE9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext380__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext380__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext381_DATAPORT_OUTPUT_READY_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext381_DATAPORT_OUTPUT_READY_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext381_DATAPORT_OUTPUT_READY_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext381_DATAPORT_OUTPUT_READY_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext381_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext381";
    metric_set->symbol_name = "Ext381";
    metric_set->hw_config_guid = "cbcdedd3-06c0-452a-80bc-2657fd042c53";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext381_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext381__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext381__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE12",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE12",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext381__dataport_output_ready_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext381_DATAPORT_OUTPUT_READY_XECORE12_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE13",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE13",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext381__dataport_output_ready_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext381_DATAPORT_OUTPUT_READY_XECORE13_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE14",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE14",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext381__dataport_output_ready_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext381_DATAPORT_OUTPUT_READY_XECORE14_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE15",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE15",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext381__dataport_output_ready_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext381_DATAPORT_OUTPUT_READY_XECORE15_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext381__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext381__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext382_DATAPORT_OUTPUT_READY_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext382_DATAPORT_OUTPUT_READY_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext382_DATAPORT_OUTPUT_READY_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext382_DATAPORT_OUTPUT_READY_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext382_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext382";
    metric_set->symbol_name = "Ext382";
    metric_set->hw_config_guid = "a43eac54-7cf5-4d96-8496-514979ca4c9a";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext382_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext382__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext382__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE16",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE16",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext382__dataport_output_ready_xecore16__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext382_DATAPORT_OUTPUT_READY_XECORE16_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE17",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE17",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext382__dataport_output_ready_xecore17__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext382_DATAPORT_OUTPUT_READY_XECORE17_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE18",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE18",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext382__dataport_output_ready_xecore18__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext382_DATAPORT_OUTPUT_READY_XECORE18_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE19",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE19",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext382__dataport_output_ready_xecore19__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext382_DATAPORT_OUTPUT_READY_XECORE19_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext382__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext382__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext383_DATAPORT_OUTPUT_READY_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext383_DATAPORT_OUTPUT_READY_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext383_DATAPORT_OUTPUT_READY_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext383_DATAPORT_OUTPUT_READY_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext383_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext383";
    metric_set->symbol_name = "Ext383";
    metric_set->hw_config_guid = "ca5db39c-f550-4965-8402-553fbf5e7920";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext383_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext383__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext383__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE20",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE20",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext383__dataport_output_ready_xecore20__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext383_DATAPORT_OUTPUT_READY_XECORE20_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE21",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE21",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext383__dataport_output_ready_xecore21__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext383_DATAPORT_OUTPUT_READY_XECORE21_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE22",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE22",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext383__dataport_output_ready_xecore22__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext383_DATAPORT_OUTPUT_READY_XECORE22_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE23",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE23",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext383__dataport_output_ready_xecore23__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext383_DATAPORT_OUTPUT_READY_XECORE23_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext383__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext383__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext384_DATAPORT_OUTPUT_READY_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext384_DATAPORT_OUTPUT_READY_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext384_DATAPORT_OUTPUT_READY_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext384_DATAPORT_OUTPUT_READY_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext384_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext384";
    metric_set->symbol_name = "Ext384";
    metric_set->hw_config_guid = "45be76fb-6be9-4028-b98d-5cff32f7a51e";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext384_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext384__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext384__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE24",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE24",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext384__dataport_output_ready_xecore24__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext384_DATAPORT_OUTPUT_READY_XECORE24_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE25",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE25",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext384__dataport_output_ready_xecore25__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext384_DATAPORT_OUTPUT_READY_XECORE25_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE26",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE26",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext384__dataport_output_ready_xecore26__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext384_DATAPORT_OUTPUT_READY_XECORE26_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE27",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE27",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext384__dataport_output_ready_xecore27__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext384_DATAPORT_OUTPUT_READY_XECORE27_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext384__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext384__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext385_DATAPORT_OUTPUT_READY_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext385_DATAPORT_OUTPUT_READY_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext385_DATAPORT_OUTPUT_READY_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext385_DATAPORT_OUTPUT_READY_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext385_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext385";
    metric_set->symbol_name = "Ext385";
    metric_set->hw_config_guid = "840b7ed8-e148-4503-9f1b-2df3a551c5c3";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext385_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext385__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext385__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE28",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE28",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext385__dataport_output_ready_xecore28__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext385_DATAPORT_OUTPUT_READY_XECORE28_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE29",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE29",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext385__dataport_output_ready_xecore29__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext385_DATAPORT_OUTPUT_READY_XECORE29_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE30",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE30",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext385__dataport_output_ready_xecore30__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext385_DATAPORT_OUTPUT_READY_XECORE30_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE31",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE31",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext385__dataport_output_ready_xecore31__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt3_ext385_DATAPORT_OUTPUT_READY_XECORE31_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext385__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext385__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext386_DATAPORT_BYTE_READ_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext386_DATAPORT_BYTE_READ_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext386_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext386";
    metric_set->symbol_name = "Ext386";
    metric_set->hw_config_guid = "5475ddd8-8385-4631-a009-45fe26c8658c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext386_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext386__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext386__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE0",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE0",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext386__dataport_byte_read_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext386_DATAPORT_BYTE_READ_XECORE0_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE1",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE1",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext386__dataport_byte_read_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext386_DATAPORT_BYTE_READ_XECORE1_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext386__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext386__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext387_DATAPORT_BYTE_READ_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext387_DATAPORT_BYTE_READ_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext387_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext387";
    metric_set->symbol_name = "Ext387";
    metric_set->hw_config_guid = "0906197a-4ac1-4af4-868f-8172f9b034ac";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext387_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext387__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext387__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE2",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE2",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext387__dataport_byte_read_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext387_DATAPORT_BYTE_READ_XECORE2_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE3",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE3",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext387__dataport_byte_read_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext387_DATAPORT_BYTE_READ_XECORE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext387__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext387__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext388_DATAPORT_BYTE_READ_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext388_DATAPORT_BYTE_READ_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext388_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext388";
    metric_set->symbol_name = "Ext388";
    metric_set->hw_config_guid = "ce2dc9cd-b9e9-4c74-934b-d1b3590b473c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext388_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext388__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext388__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE4",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE4",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext388__dataport_byte_read_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext388_DATAPORT_BYTE_READ_XECORE4_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE5",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE5",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext388__dataport_byte_read_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext388_DATAPORT_BYTE_READ_XECORE5_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext388__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext388__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext389_DATAPORT_BYTE_READ_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext389_DATAPORT_BYTE_READ_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext389_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext389";
    metric_set->symbol_name = "Ext389";
    metric_set->hw_config_guid = "d87d855d-5896-4c76-b0fe-4120c5ad1a63";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext389_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext389__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext389__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE6",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE6",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext389__dataport_byte_read_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext389_DATAPORT_BYTE_READ_XECORE6_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE7",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE7",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext389__dataport_byte_read_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext389_DATAPORT_BYTE_READ_XECORE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext389__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext389__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext390_DATAPORT_BYTE_READ_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext390_DATAPORT_BYTE_READ_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext390_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext390";
    metric_set->symbol_name = "Ext390";
    metric_set->hw_config_guid = "d8b0608d-4fe4-4762-8df3-429344ff1a10";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext390_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext390__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext390__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE8",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE8",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext390__dataport_byte_read_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext390_DATAPORT_BYTE_READ_XECORE8_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE9",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE9",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext390__dataport_byte_read_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext390_DATAPORT_BYTE_READ_XECORE9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext390__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext390__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext391_DATAPORT_BYTE_READ_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext391_DATAPORT_BYTE_READ_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext391_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext391";
    metric_set->symbol_name = "Ext391";
    metric_set->hw_config_guid = "1635ad22-5347-4911-a15c-0716a7fd55d0";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext391_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext391__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext391__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE10",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE10",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext391__dataport_byte_read_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext391_DATAPORT_BYTE_READ_XECORE10_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE11",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE11",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext391__dataport_byte_read_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext391_DATAPORT_BYTE_READ_XECORE11_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext391__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext391__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext392_DATAPORT_BYTE_READ_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext392_DATAPORT_BYTE_READ_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext392_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext392";
    metric_set->symbol_name = "Ext392";
    metric_set->hw_config_guid = "e001e26e-5522-4f0b-a437-e6d6c3144a8c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext392_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext392__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext392__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE12",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE12",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext392__dataport_byte_read_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext392_DATAPORT_BYTE_READ_XECORE12_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE13",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE13",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext392__dataport_byte_read_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext392_DATAPORT_BYTE_READ_XECORE13_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext392__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext392__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext393_DATAPORT_BYTE_READ_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext393_DATAPORT_BYTE_READ_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext393_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext393";
    metric_set->symbol_name = "Ext393";
    metric_set->hw_config_guid = "64ea4666-79c3-4e0a-a68e-5a65ed571a8d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext393_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext393__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext393__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE14",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE14",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext393__dataport_byte_read_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext393_DATAPORT_BYTE_READ_XECORE14_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE15",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE15",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext393__dataport_byte_read_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext393_DATAPORT_BYTE_READ_XECORE15_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext393__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext393__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext394_DATAPORT_BYTE_READ_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext394_DATAPORT_BYTE_READ_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext394_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext394";
    metric_set->symbol_name = "Ext394";
    metric_set->hw_config_guid = "437d1633-c275-49f0-9994-4e94672ac99c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext394_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext394__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext394__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE16",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE16",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext394__dataport_byte_read_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext394_DATAPORT_BYTE_READ_XECORE16_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE17",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE17",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext394__dataport_byte_read_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext394_DATAPORT_BYTE_READ_XECORE17_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext394__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext394__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext395_DATAPORT_BYTE_READ_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext395_DATAPORT_BYTE_READ_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext395_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext395";
    metric_set->symbol_name = "Ext395";
    metric_set->hw_config_guid = "ed6321f2-59be-4560-889b-5682128d1177";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext395_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext395__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext395__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE18",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE18",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext395__dataport_byte_read_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext395_DATAPORT_BYTE_READ_XECORE18_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE19",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE19",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext395__dataport_byte_read_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext395_DATAPORT_BYTE_READ_XECORE19_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext395__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext395__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext396_DATAPORT_BYTE_READ_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext396_DATAPORT_BYTE_READ_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext396_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext396";
    metric_set->symbol_name = "Ext396";
    metric_set->hw_config_guid = "c3a07e91-05fe-458d-a578-55b67eb8625a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext396_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext396__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext396__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE20",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE20",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext396__dataport_byte_read_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext396_DATAPORT_BYTE_READ_XECORE20_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE21",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE21",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext396__dataport_byte_read_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext396_DATAPORT_BYTE_READ_XECORE21_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext396__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext396__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext397_DATAPORT_BYTE_READ_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext397_DATAPORT_BYTE_READ_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext397_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext397";
    metric_set->symbol_name = "Ext397";
    metric_set->hw_config_guid = "25a1e5ce-835d-4659-896b-a7279e2df94e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext397_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext397__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext397__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE22",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE22",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext397__dataport_byte_read_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext397_DATAPORT_BYTE_READ_XECORE22_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE23",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE23",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext397__dataport_byte_read_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext397_DATAPORT_BYTE_READ_XECORE23_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext397__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext397__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext398_DATAPORT_BYTE_READ_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext398_DATAPORT_BYTE_READ_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext398_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext398";
    metric_set->symbol_name = "Ext398";
    metric_set->hw_config_guid = "13b89a1d-1377-41f5-ba3f-800afcfb86a7";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext398_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext398__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext398__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE24",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE24",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext398__dataport_byte_read_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext398_DATAPORT_BYTE_READ_XECORE24_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE25",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE25",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext398__dataport_byte_read_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext398_DATAPORT_BYTE_READ_XECORE25_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext398__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext398__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext399_DATAPORT_BYTE_READ_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext399_DATAPORT_BYTE_READ_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext399_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext399";
    metric_set->symbol_name = "Ext399";
    metric_set->hw_config_guid = "dea45968-7d62-4989-bb89-ff1ffcf44402";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext399_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext399__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext399__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE26",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE26",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext399__dataport_byte_read_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext399_DATAPORT_BYTE_READ_XECORE26_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE27",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE27",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext399__dataport_byte_read_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext399_DATAPORT_BYTE_READ_XECORE27_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext399__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext399__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext400_DATAPORT_BYTE_READ_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext400_DATAPORT_BYTE_READ_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext400_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext400";
    metric_set->symbol_name = "Ext400";
    metric_set->hw_config_guid = "5df56b7b-4cd0-4f36-b91b-44e4f47ab5da";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext400_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext400__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext400__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE28",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE28",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext400__dataport_byte_read_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext400_DATAPORT_BYTE_READ_XECORE28_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE29",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE29",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext400__dataport_byte_read_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext400_DATAPORT_BYTE_READ_XECORE29_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext400__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext400__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext401_DATAPORT_BYTE_READ_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext401_DATAPORT_BYTE_READ_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext401_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext401";
    metric_set->symbol_name = "Ext401";
    metric_set->hw_config_guid = "f48f4171-49a5-4a0e-bfcc-9f1f89569138";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext401_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext401__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext401__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE30",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE30",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext401__dataport_byte_read_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext401_DATAPORT_BYTE_READ_XECORE30_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE31",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE31",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext401__dataport_byte_read_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext401_DATAPORT_BYTE_READ_XECORE31_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext401__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext401__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext402_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext402";
    metric_set->symbol_name = "Ext402";
    metric_set->hw_config_guid = "bed2251c-d53e-402c-9100-2f27febc1672";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext402_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext402__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext402__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE0",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE0",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext402__dataport_byte_write_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE0_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE1",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE1",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext402__dataport_byte_write_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE1_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE10",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE10",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext402__dataport_byte_write_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE10_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE11",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE11",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext402__dataport_byte_write_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE11_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE12",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE12",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext402__dataport_byte_write_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE12_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE13",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE13",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext402__dataport_byte_write_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE13_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE14",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE14",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext402__dataport_byte_write_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE14_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE15",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE15",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext402__dataport_byte_write_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE15_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE2",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE2",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext402__dataport_byte_write_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE2_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE3",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE3",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext402__dataport_byte_write_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE3_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE4",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE4",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext402__dataport_byte_write_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE4_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE5",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE5",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext402__dataport_byte_write_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE5_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE6",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE6",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext402__dataport_byte_write_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE6_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE7",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE7",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext402__dataport_byte_write_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE7_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE8",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE8",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext402__dataport_byte_write_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE8_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE9",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE9",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext402__dataport_byte_write_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext402_DATAPORT_BYTE_WRITE_XECORE9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext402__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext402__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext403_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext403";
    metric_set->symbol_name = "Ext403";
    metric_set->hw_config_guid = "1894c9d9-8ba5-41df-97ba-6cadd89a8418";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext403_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext403__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext403__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE16",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE16",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext403__dataport_byte_write_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE16_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE17",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE17",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext403__dataport_byte_write_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE17_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE18",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE18",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext403__dataport_byte_write_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE18_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE19",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE19",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext403__dataport_byte_write_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE19_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE20",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE20",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext403__dataport_byte_write_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE20_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE21",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE21",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext403__dataport_byte_write_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE21_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE22",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE22",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext403__dataport_byte_write_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE22_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE23",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE23",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext403__dataport_byte_write_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE23_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE24",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE24",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext403__dataport_byte_write_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE24_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE25",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE25",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext403__dataport_byte_write_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE25_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE26",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE26",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext403__dataport_byte_write_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE26_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE27",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE27",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext403__dataport_byte_write_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE27_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE28",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE28",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext403__dataport_byte_write_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE28_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE29",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE29",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext403__dataport_byte_write_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE29_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE30",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE30",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext403__dataport_byte_write_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE30_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE31",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE31",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext403__dataport_byte_write_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext403_DATAPORT_BYTE_WRITE_XECORE31_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext403__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext403__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext404_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext404";
    metric_set->symbol_name = "Ext404";
    metric_set->hw_config_guid = "8712ea52-9c71-4036-a736-308b77af503a";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext404_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext404__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext404__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE0",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE0",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext404__dataport_texture_cache_access_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE0_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE1",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE1",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext404__dataport_texture_cache_access_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE1_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE10",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE10",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext404__dataport_texture_cache_access_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE10_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE11",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE11",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext404__dataport_texture_cache_access_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE11_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE12",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE12",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext404__dataport_texture_cache_access_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE12_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE13",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE13",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext404__dataport_texture_cache_access_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE13_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE14",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE14",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext404__dataport_texture_cache_access_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE14_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE15",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE15",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext404__dataport_texture_cache_access_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE15_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE2",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE2",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext404__dataport_texture_cache_access_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE2_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE3",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE3",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext404__dataport_texture_cache_access_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE3_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE4",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE4",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext404__dataport_texture_cache_access_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE4_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE5",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE5",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext404__dataport_texture_cache_access_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE5_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE6",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE6",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext404__dataport_texture_cache_access_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE6_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE7",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE7",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext404__dataport_texture_cache_access_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE7_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE8",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE8",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext404__dataport_texture_cache_access_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE8_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE9",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE9",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext404__dataport_texture_cache_access_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext404_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext404__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext404__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext405_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext405";
    metric_set->symbol_name = "Ext405";
    metric_set->hw_config_guid = "8e9ae82a-577e-4804-b314-de02d7206903";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext405_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext405__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext405__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE16",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE16",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext405__dataport_texture_cache_access_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE16_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE17",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE17",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext405__dataport_texture_cache_access_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE17_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE18",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE18",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext405__dataport_texture_cache_access_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE18_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE19",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE19",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext405__dataport_texture_cache_access_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE19_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE20",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE20",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext405__dataport_texture_cache_access_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE20_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE21",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE21",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext405__dataport_texture_cache_access_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE21_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE22",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE22",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext405__dataport_texture_cache_access_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE22_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE23",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE23",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext405__dataport_texture_cache_access_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE23_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE24",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE24",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext405__dataport_texture_cache_access_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE24_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE25",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE25",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext405__dataport_texture_cache_access_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE25_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE26",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE26",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext405__dataport_texture_cache_access_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE26_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE27",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE27",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext405__dataport_texture_cache_access_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE27_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE28",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE28",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext405__dataport_texture_cache_access_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE28_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE29",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE29",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext405__dataport_texture_cache_access_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE29_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE30",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE30",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext405__dataport_texture_cache_access_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE30_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE31",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE31",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext405__dataport_texture_cache_access_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext405_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE31_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext405__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext405__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext406_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext406";
    metric_set->symbol_name = "Ext406";
    metric_set->hw_config_guid = "654e925d-2c2a-49a9-bd44-3470039c6e86";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext406_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext406__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext406__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE0",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE0",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext406__dataport_texture_cache_hit_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE0_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE1",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE1",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext406__dataport_texture_cache_hit_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE1_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE10",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE10",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext406__dataport_texture_cache_hit_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE10_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE11",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE11",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext406__dataport_texture_cache_hit_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE11_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE12",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE12",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext406__dataport_texture_cache_hit_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE12_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE13",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE13",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext406__dataport_texture_cache_hit_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE13_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE14",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE14",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext406__dataport_texture_cache_hit_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE14_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE15",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE15",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext406__dataport_texture_cache_hit_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE15_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE2",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE2",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext406__dataport_texture_cache_hit_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE2_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE3",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE3",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext406__dataport_texture_cache_hit_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE3_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE4",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE4",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext406__dataport_texture_cache_hit_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE4_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE5",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE5",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext406__dataport_texture_cache_hit_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE5_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE6",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE6",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext406__dataport_texture_cache_hit_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE6_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE7",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE7",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext406__dataport_texture_cache_hit_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE7_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE8",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE8",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext406__dataport_texture_cache_hit_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE8_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE9",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE9",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext406__dataport_texture_cache_hit_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext406_DATAPORT_TEXTURE_CACHE_HIT_XECORE9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext406__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext406__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext407_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext407";
    metric_set->symbol_name = "Ext407";
    metric_set->hw_config_guid = "f9c431af-992b-4f6c-b068-4e89ca0b3538";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext407_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext407__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext407__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE16",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE16",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext407__dataport_texture_cache_hit_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE16_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE17",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE17",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext407__dataport_texture_cache_hit_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE17_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE18",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE18",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext407__dataport_texture_cache_hit_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE18_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE19",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE19",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext407__dataport_texture_cache_hit_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE19_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE20",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE20",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext407__dataport_texture_cache_hit_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE20_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE21",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE21",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext407__dataport_texture_cache_hit_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE21_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE22",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE22",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext407__dataport_texture_cache_hit_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE22_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE23",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE23",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext407__dataport_texture_cache_hit_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE23_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE24",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE24",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext407__dataport_texture_cache_hit_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE24_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE25",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE25",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext407__dataport_texture_cache_hit_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE25_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE26",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE26",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext407__dataport_texture_cache_hit_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE26_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE27",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE27",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext407__dataport_texture_cache_hit_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE27_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE28",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE28",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext407__dataport_texture_cache_hit_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE28_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE29",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE29",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext407__dataport_texture_cache_hit_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE29_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE30",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE30",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext407__dataport_texture_cache_hit_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE30_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE31",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE31",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext407__dataport_texture_cache_hit_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt3_ext407_DATAPORT_TEXTURE_CACHE_HIT_XECORE31_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext407__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext407__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext408_RT_INPUT_MESSAGE_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext408_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext408_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext408_RT_MESSAGE_STALL_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext408_RT_QUAD_TEST_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext408_RT_REQUEST_COLLISION_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext408_RT_TRANSFORM_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext408_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext408_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext408";
    metric_set->symbol_name = "Ext408";
    metric_set->hw_config_guid = "c7fe43dc-ae1a-45d9-b64d-60fac946a070";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext408_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext408__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext408__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext408__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext408__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE0",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE0",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext408__rt_input_message_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext408_RT_INPUT_MESSAGE_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE0",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext408__rt_load_store_cache_read_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext408_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE0",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE0",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext408__rt_load_store_cache_write_from_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext408_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE0",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE0",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext408__rt_message_stall_count_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext408_RT_MESSAGE_STALL_COUNT_XECORE0_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE0",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE0",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext408__rt_quad_test_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext408_RT_QUAD_TEST_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE0",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE0",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext408__rt_request_collision_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext408_RT_REQUEST_COLLISION_XECORE0_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE0",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE0",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext408__rt_transform_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext408_RT_TRANSFORM_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE0",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE0",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext408__rt_traversal_input_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext408_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext409_RT_INPUT_MESSAGE_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext409_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext409_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext409_RT_MESSAGE_STALL_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext409_RT_QUAD_TEST_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext409_RT_REQUEST_COLLISION_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext409_RT_TRANSFORM_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext409_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext409_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext409";
    metric_set->symbol_name = "Ext409";
    metric_set->hw_config_guid = "0b7c4602-76f0-4a2e-abe4-f0829f2f9b02";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext409_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext409__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext409__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext409__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext409__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE1",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE1",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext409__rt_input_message_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext409_RT_INPUT_MESSAGE_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE1",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext409__rt_load_store_cache_read_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext409_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE1",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE1",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext409__rt_load_store_cache_write_from_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext409_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE1",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE1",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext409__rt_message_stall_count_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext409_RT_MESSAGE_STALL_COUNT_XECORE1_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE1",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE1",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext409__rt_quad_test_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext409_RT_QUAD_TEST_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE1",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE1",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext409__rt_request_collision_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext409_RT_REQUEST_COLLISION_XECORE1_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE1",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE1",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext409__rt_transform_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext409_RT_TRANSFORM_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE1",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE1",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext409__rt_traversal_input_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext409_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext410_RT_INPUT_MESSAGE_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext410_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext410_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext410_RT_MESSAGE_STALL_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext410_RT_QUAD_TEST_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext410_RT_REQUEST_COLLISION_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext410_RT_TRANSFORM_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext410_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext410_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext410";
    metric_set->symbol_name = "Ext410";
    metric_set->hw_config_guid = "64a617b8-cae0-439e-b014-1e70e72ac75d";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext410_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext410__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext410__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext410__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext410__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE2",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE2",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext410__rt_input_message_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext410_RT_INPUT_MESSAGE_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE2",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext410__rt_load_store_cache_read_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext410_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE2",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE2",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext410__rt_load_store_cache_write_from_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext410_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE2",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE2",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext410__rt_message_stall_count_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext410_RT_MESSAGE_STALL_COUNT_XECORE2_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE2",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE2",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext410__rt_quad_test_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext410_RT_QUAD_TEST_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE2",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE2",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext410__rt_request_collision_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext410_RT_REQUEST_COLLISION_XECORE2_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE2",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE2",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext410__rt_transform_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext410_RT_TRANSFORM_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE2",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE2",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext410__rt_traversal_input_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext410_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext411_RT_INPUT_MESSAGE_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext411_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext411_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext411_RT_MESSAGE_STALL_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext411_RT_QUAD_TEST_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext411_RT_REQUEST_COLLISION_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext411_RT_TRANSFORM_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext411_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext411_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext411";
    metric_set->symbol_name = "Ext411";
    metric_set->hw_config_guid = "304aa1c9-59be-4f9d-ab68-2d607a9b90ee";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext411_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext411__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext411__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext411__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext411__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE3",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE3",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext411__rt_input_message_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext411_RT_INPUT_MESSAGE_RAY_COUNT_XECORE3_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE3",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE3",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext411__rt_load_store_cache_read_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext411_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE3_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE3",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE3",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext411__rt_load_store_cache_write_from_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext411_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE3_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE3",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE3",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext411__rt_message_stall_count_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext411_RT_MESSAGE_STALL_COUNT_XECORE3_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE3",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE3",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext411__rt_quad_test_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext411_RT_QUAD_TEST_RAY_COUNT_XECORE3_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE3",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE3",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext411__rt_request_collision_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext411_RT_REQUEST_COLLISION_XECORE3_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE3",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE3",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext411__rt_transform_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext411_RT_TRANSFORM_RAY_COUNT_XECORE3_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE3",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE3",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext411__rt_traversal_input_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext411_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext412_RT_INPUT_MESSAGE_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext412_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext412_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext412_RT_MESSAGE_STALL_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext412_RT_QUAD_TEST_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext412_RT_REQUEST_COLLISION_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext412_RT_TRANSFORM_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext412_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext412_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext412";
    metric_set->symbol_name = "Ext412";
    metric_set->hw_config_guid = "d9a3534a-4dca-4b28-b8e8-d447017b82a5";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext412_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext412__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext412__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext412__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext412__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE4",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE4",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext412__rt_input_message_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext412_RT_INPUT_MESSAGE_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE4",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext412__rt_load_store_cache_read_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext412_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE4",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE4",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext412__rt_load_store_cache_write_from_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext412_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE4",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE4",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext412__rt_message_stall_count_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext412_RT_MESSAGE_STALL_COUNT_XECORE4_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE4",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE4",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext412__rt_quad_test_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext412_RT_QUAD_TEST_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE4",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE4",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext412__rt_request_collision_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext412_RT_REQUEST_COLLISION_XECORE4_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE4",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE4",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext412__rt_transform_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext412_RT_TRANSFORM_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE4",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE4",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext412__rt_traversal_input_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext412_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext413_RT_INPUT_MESSAGE_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext413_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext413_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext413_RT_MESSAGE_STALL_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext413_RT_QUAD_TEST_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext413_RT_REQUEST_COLLISION_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext413_RT_TRANSFORM_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext413_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext413_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext413";
    metric_set->symbol_name = "Ext413";
    metric_set->hw_config_guid = "594a085e-c744-4544-b38b-196e9b52d1b0";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext413_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext413__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext413__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext413__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext413__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE5",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE5",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext413__rt_input_message_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext413_RT_INPUT_MESSAGE_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE5",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE5",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext413__rt_load_store_cache_read_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext413_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE5",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE5",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext413__rt_load_store_cache_write_from_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext413_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE5",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE5",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext413__rt_message_stall_count_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext413_RT_MESSAGE_STALL_COUNT_XECORE5_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE5",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE5",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext413__rt_quad_test_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext413_RT_QUAD_TEST_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE5",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE5",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext413__rt_request_collision_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext413_RT_REQUEST_COLLISION_XECORE5_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE5",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE5",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext413__rt_transform_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext413_RT_TRANSFORM_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE5",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE5",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext413__rt_traversal_input_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext413_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext414_RT_INPUT_MESSAGE_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext414_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext414_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext414_RT_MESSAGE_STALL_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext414_RT_QUAD_TEST_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext414_RT_REQUEST_COLLISION_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext414_RT_TRANSFORM_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext414_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext414_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext414";
    metric_set->symbol_name = "Ext414";
    metric_set->hw_config_guid = "99fd5805-5f5e-48ae-95d1-6cb7d5c09bfb";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext414_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext414__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext414__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext414__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext414__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE6",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE6",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext414__rt_input_message_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext414_RT_INPUT_MESSAGE_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE6",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext414__rt_load_store_cache_read_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext414_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE6",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE6",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext414__rt_load_store_cache_write_from_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext414_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE6",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE6",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext414__rt_message_stall_count_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext414_RT_MESSAGE_STALL_COUNT_XECORE6_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE6",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE6",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext414__rt_quad_test_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext414_RT_QUAD_TEST_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE6",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE6",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext414__rt_request_collision_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext414_RT_REQUEST_COLLISION_XECORE6_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE6",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE6",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext414__rt_transform_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext414_RT_TRANSFORM_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE6",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE6",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext414__rt_traversal_input_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext414_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext415_RT_INPUT_MESSAGE_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext415_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext415_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext415_RT_MESSAGE_STALL_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext415_RT_QUAD_TEST_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext415_RT_REQUEST_COLLISION_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext415_RT_TRANSFORM_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext415_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext415_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext415";
    metric_set->symbol_name = "Ext415";
    metric_set->hw_config_guid = "1be807ab-2f67-45bb-901f-9bb9d805d4a7";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext415_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext415__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext415__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext415__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext415__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE7",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE7",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext415__rt_input_message_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext415_RT_INPUT_MESSAGE_RAY_COUNT_XECORE7_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE7",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext415__rt_load_store_cache_read_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext415_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE7",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE7",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext415__rt_load_store_cache_write_from_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext415_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE7_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE7",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE7",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext415__rt_message_stall_count_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext415_RT_MESSAGE_STALL_COUNT_XECORE7_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE7",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE7",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext415__rt_quad_test_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext415_RT_QUAD_TEST_RAY_COUNT_XECORE7_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE7",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE7",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext415__rt_request_collision_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext415_RT_REQUEST_COLLISION_XECORE7_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE7",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE7",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext415__rt_transform_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext415_RT_TRANSFORM_RAY_COUNT_XECORE7_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE7",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE7",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext415__rt_traversal_input_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext415_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext416_RT_INPUT_MESSAGE_RAY_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext416_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext416_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext416_RT_MESSAGE_STALL_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext416_RT_QUAD_TEST_RAY_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext416_RT_REQUEST_COLLISION_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext416_RT_TRANSFORM_RAY_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext416_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext416_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext416";
    metric_set->symbol_name = "Ext416";
    metric_set->hw_config_guid = "8204f26d-37d5-458f-aac4-e1120b674145";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext416_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext416__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext416__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext416__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext416__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE8",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE8",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext416__rt_input_message_ray_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext416_RT_INPUT_MESSAGE_RAY_COUNT_XECORE8_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE8",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE8",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext416__rt_load_store_cache_read_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext416_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE8_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE8",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE8",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext416__rt_load_store_cache_write_from_message_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext416_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE8_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE8",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE8",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext416__rt_message_stall_count_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext416_RT_MESSAGE_STALL_COUNT_XECORE8_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE8",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE8",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext416__rt_quad_test_ray_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext416_RT_QUAD_TEST_RAY_COUNT_XECORE8_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE8",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE8",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext416__rt_request_collision_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext416_RT_REQUEST_COLLISION_XECORE8_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE8",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE8",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext416__rt_transform_ray_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext416_RT_TRANSFORM_RAY_COUNT_XECORE8_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE8",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE8",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext416__rt_traversal_input_ray_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext416_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE8_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext417_RT_INPUT_MESSAGE_RAY_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext417_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext417_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext417_RT_MESSAGE_STALL_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext417_RT_QUAD_TEST_RAY_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext417_RT_REQUEST_COLLISION_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext417_RT_TRANSFORM_RAY_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext417_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext417_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext417";
    metric_set->symbol_name = "Ext417";
    metric_set->hw_config_guid = "7f38c38f-0f80-4e50-9269-dfc0e08b0660";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext417_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext417__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext417__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext417__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext417__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE9",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE9",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext417__rt_input_message_ray_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext417_RT_INPUT_MESSAGE_RAY_COUNT_XECORE9_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE9",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE9",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext417__rt_load_store_cache_read_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext417_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE9_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE9",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE9",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext417__rt_load_store_cache_write_from_message_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext417_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE9_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE9",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE9",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext417__rt_message_stall_count_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext417_RT_MESSAGE_STALL_COUNT_XECORE9_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE9",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE9",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext417__rt_quad_test_ray_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext417_RT_QUAD_TEST_RAY_COUNT_XECORE9_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE9",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE9",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext417__rt_request_collision_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext417_RT_REQUEST_COLLISION_XECORE9_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE9",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE9",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext417__rt_transform_ray_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext417_RT_TRANSFORM_RAY_COUNT_XECORE9_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE9",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE9",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext417__rt_traversal_input_ray_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext417_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext418_RT_INPUT_MESSAGE_RAY_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext418_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext418_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext418_RT_MESSAGE_STALL_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext418_RT_QUAD_TEST_RAY_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext418_RT_REQUEST_COLLISION_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext418_RT_TRANSFORM_RAY_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext418_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext418_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext418";
    metric_set->symbol_name = "Ext418";
    metric_set->hw_config_guid = "2654399f-54e6-45ca-931d-1f01c9f8ca06";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext418_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext418__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext418__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext418__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext418__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE10",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE10",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext418__rt_input_message_ray_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext418_RT_INPUT_MESSAGE_RAY_COUNT_XECORE10_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE10",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE10",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext418__rt_load_store_cache_read_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext418_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE10_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE10",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE10",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext418__rt_load_store_cache_write_from_message_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext418_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE10_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE10",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE10",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext418__rt_message_stall_count_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext418_RT_MESSAGE_STALL_COUNT_XECORE10_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE10",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE10",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext418__rt_quad_test_ray_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext418_RT_QUAD_TEST_RAY_COUNT_XECORE10_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE10",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE10",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext418__rt_request_collision_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext418_RT_REQUEST_COLLISION_XECORE10_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE10",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE10",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext418__rt_transform_ray_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext418_RT_TRANSFORM_RAY_COUNT_XECORE10_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE10",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE10",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext418__rt_traversal_input_ray_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext418_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE10_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext419_RT_INPUT_MESSAGE_RAY_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext419_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext419_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext419_RT_MESSAGE_STALL_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext419_RT_QUAD_TEST_RAY_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext419_RT_REQUEST_COLLISION_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext419_RT_TRANSFORM_RAY_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext419_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext419_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext419";
    metric_set->symbol_name = "Ext419";
    metric_set->hw_config_guid = "8a2b3a4e-791f-4f5a-931d-78e3a6c673bb";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext419_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext419__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext419__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext419__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext419__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE11",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE11",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext419__rt_input_message_ray_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext419_RT_INPUT_MESSAGE_RAY_COUNT_XECORE11_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE11",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE11",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext419__rt_load_store_cache_read_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext419_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE11_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE11",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE11",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext419__rt_load_store_cache_write_from_message_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext419_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE11_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE11",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE11",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext419__rt_message_stall_count_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext419_RT_MESSAGE_STALL_COUNT_XECORE11_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE11",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE11",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext419__rt_quad_test_ray_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext419_RT_QUAD_TEST_RAY_COUNT_XECORE11_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE11",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE11",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext419__rt_request_collision_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext419_RT_REQUEST_COLLISION_XECORE11_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE11",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE11",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext419__rt_transform_ray_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext419_RT_TRANSFORM_RAY_COUNT_XECORE11_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE11",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE11",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext419__rt_traversal_input_ray_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext419_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext420_RT_INPUT_MESSAGE_RAY_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext420_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext420_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext420_RT_MESSAGE_STALL_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext420_RT_QUAD_TEST_RAY_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext420_RT_REQUEST_COLLISION_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext420_RT_TRANSFORM_RAY_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext420_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext420_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext420";
    metric_set->symbol_name = "Ext420";
    metric_set->hw_config_guid = "d5d2ec61-a953-487d-9e9f-9e15c80ad7ac";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext420_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext420__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext420__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext420__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext420__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE12",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE12",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext420__rt_input_message_ray_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext420_RT_INPUT_MESSAGE_RAY_COUNT_XECORE12_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE12",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE12",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext420__rt_load_store_cache_read_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext420_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE12_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE12",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE12",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext420__rt_load_store_cache_write_from_message_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext420_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE12_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE12",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE12",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext420__rt_message_stall_count_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext420_RT_MESSAGE_STALL_COUNT_XECORE12_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE12",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE12",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext420__rt_quad_test_ray_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext420_RT_QUAD_TEST_RAY_COUNT_XECORE12_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE12",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE12",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext420__rt_request_collision_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext420_RT_REQUEST_COLLISION_XECORE12_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE12",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE12",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext420__rt_transform_ray_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext420_RT_TRANSFORM_RAY_COUNT_XECORE12_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE12",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE12",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext420__rt_traversal_input_ray_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext420_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE12_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext421_RT_INPUT_MESSAGE_RAY_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext421_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext421_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext421_RT_MESSAGE_STALL_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext421_RT_QUAD_TEST_RAY_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext421_RT_REQUEST_COLLISION_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext421_RT_TRANSFORM_RAY_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext421_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext421_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext421";
    metric_set->symbol_name = "Ext421";
    metric_set->hw_config_guid = "581a1d88-3759-4cf4-ba59-4c25377cdece";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext421_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext421__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext421__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext421__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext421__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE13",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE13",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext421__rt_input_message_ray_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext421_RT_INPUT_MESSAGE_RAY_COUNT_XECORE13_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE13",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE13",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext421__rt_load_store_cache_read_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext421_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE13_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE13",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE13",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext421__rt_load_store_cache_write_from_message_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext421_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE13_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE13",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE13",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext421__rt_message_stall_count_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext421_RT_MESSAGE_STALL_COUNT_XECORE13_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE13",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE13",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext421__rt_quad_test_ray_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext421_RT_QUAD_TEST_RAY_COUNT_XECORE13_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE13",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE13",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext421__rt_request_collision_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext421_RT_REQUEST_COLLISION_XECORE13_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE13",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE13",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext421__rt_transform_ray_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext421_RT_TRANSFORM_RAY_COUNT_XECORE13_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE13",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE13",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext421__rt_traversal_input_ray_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext421_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext422_RT_INPUT_MESSAGE_RAY_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext422_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext422_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext422_RT_MESSAGE_STALL_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext422_RT_QUAD_TEST_RAY_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext422_RT_REQUEST_COLLISION_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext422_RT_TRANSFORM_RAY_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext422_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext422_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext422";
    metric_set->symbol_name = "Ext422";
    metric_set->hw_config_guid = "316fefa3-9d16-4eaa-9904-15b2203ec95c";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext422_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext422__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext422__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext422__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext422__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE14",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE14",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext422__rt_input_message_ray_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext422_RT_INPUT_MESSAGE_RAY_COUNT_XECORE14_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE14",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE14",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext422__rt_load_store_cache_read_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext422_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE14_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE14",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE14",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext422__rt_load_store_cache_write_from_message_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext422_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE14_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE14",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE14",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext422__rt_message_stall_count_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext422_RT_MESSAGE_STALL_COUNT_XECORE14_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE14",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE14",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext422__rt_quad_test_ray_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext422_RT_QUAD_TEST_RAY_COUNT_XECORE14_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE14",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE14",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext422__rt_request_collision_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext422_RT_REQUEST_COLLISION_XECORE14_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE14",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE14",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext422__rt_transform_ray_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext422_RT_TRANSFORM_RAY_COUNT_XECORE14_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE14",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE14",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext422__rt_traversal_input_ray_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext422_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE14_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext423_RT_INPUT_MESSAGE_RAY_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext423_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext423_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext423_RT_MESSAGE_STALL_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext423_RT_QUAD_TEST_RAY_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext423_RT_REQUEST_COLLISION_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext423_RT_TRANSFORM_RAY_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext423_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext423_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext423";
    metric_set->symbol_name = "Ext423";
    metric_set->hw_config_guid = "6e0a01cd-c537-45e1-aedd-3e181b7a7c01";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext423_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext423__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext423__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext423__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext423__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE15",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE15",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext423__rt_input_message_ray_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext423_RT_INPUT_MESSAGE_RAY_COUNT_XECORE15_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE15",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE15",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext423__rt_load_store_cache_read_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext423_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE15_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE15",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE15",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext423__rt_load_store_cache_write_from_message_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext423_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE15_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE15",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE15",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext423__rt_message_stall_count_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext423_RT_MESSAGE_STALL_COUNT_XECORE15_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE15",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE15",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext423__rt_quad_test_ray_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext423_RT_QUAD_TEST_RAY_COUNT_XECORE15_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE15",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE15",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext423__rt_request_collision_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext423_RT_REQUEST_COLLISION_XECORE15_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE15",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE15",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext423__rt_transform_ray_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext423_RT_TRANSFORM_RAY_COUNT_XECORE15_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE15",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE15",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext423__rt_traversal_input_ray_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext423_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext424_RT_INPUT_MESSAGE_RAY_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext424_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext424_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext424_RT_MESSAGE_STALL_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext424_RT_QUAD_TEST_RAY_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext424_RT_REQUEST_COLLISION_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext424_RT_TRANSFORM_RAY_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext424_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext424_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext424";
    metric_set->symbol_name = "Ext424";
    metric_set->hw_config_guid = "9141c2fe-b37b-4f53-a292-a09a3a54dbd4";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext424_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext424__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext424__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext424__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext424__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE16",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE16",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext424__rt_input_message_ray_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext424_RT_INPUT_MESSAGE_RAY_COUNT_XECORE16_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE16",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE16",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext424__rt_load_store_cache_read_message_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext424_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE16_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE16",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE16",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext424__rt_load_store_cache_write_from_message_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext424_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE16_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE16",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE16",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext424__rt_message_stall_count_xecore16__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext424_RT_MESSAGE_STALL_COUNT_XECORE16_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE16",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE16",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext424__rt_quad_test_ray_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext424_RT_QUAD_TEST_RAY_COUNT_XECORE16_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE16",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE16",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext424__rt_request_collision_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext424_RT_REQUEST_COLLISION_XECORE16_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE16",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE16",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext424__rt_transform_ray_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext424_RT_TRANSFORM_RAY_COUNT_XECORE16_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE16",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE16",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext424__rt_traversal_input_ray_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext424_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE16_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext425_RT_INPUT_MESSAGE_RAY_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext425_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext425_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext425_RT_MESSAGE_STALL_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext425_RT_QUAD_TEST_RAY_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext425_RT_REQUEST_COLLISION_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext425_RT_TRANSFORM_RAY_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext425_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext425_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext425";
    metric_set->symbol_name = "Ext425";
    metric_set->hw_config_guid = "b655bffc-0284-4ad5-847e-caf886a651bc";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext425_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext425__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext425__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext425__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext425__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE17",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE17",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext425__rt_input_message_ray_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext425_RT_INPUT_MESSAGE_RAY_COUNT_XECORE17_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE17",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE17",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext425__rt_load_store_cache_read_message_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext425_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE17_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE17",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE17",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext425__rt_load_store_cache_write_from_message_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext425_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE17_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE17",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE17",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext425__rt_message_stall_count_xecore17__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext425_RT_MESSAGE_STALL_COUNT_XECORE17_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE17",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE17",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext425__rt_quad_test_ray_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext425_RT_QUAD_TEST_RAY_COUNT_XECORE17_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE17",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE17",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext425__rt_request_collision_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext425_RT_REQUEST_COLLISION_XECORE17_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE17",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE17",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext425__rt_transform_ray_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext425_RT_TRANSFORM_RAY_COUNT_XECORE17_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE17",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE17",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext425__rt_traversal_input_ray_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext425_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE17_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext426_RT_INPUT_MESSAGE_RAY_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext426_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext426_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext426_RT_MESSAGE_STALL_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext426_RT_QUAD_TEST_RAY_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext426_RT_REQUEST_COLLISION_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext426_RT_TRANSFORM_RAY_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext426_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext426_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext426";
    metric_set->symbol_name = "Ext426";
    metric_set->hw_config_guid = "5aca86ba-4035-4c53-af84-25152bf169e3";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext426_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext426__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext426__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext426__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext426__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE18",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE18",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext426__rt_input_message_ray_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext426_RT_INPUT_MESSAGE_RAY_COUNT_XECORE18_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE18",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE18",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext426__rt_load_store_cache_read_message_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext426_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE18_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE18",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE18",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext426__rt_load_store_cache_write_from_message_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext426_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE18_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE18",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE18",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext426__rt_message_stall_count_xecore18__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext426_RT_MESSAGE_STALL_COUNT_XECORE18_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE18",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE18",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext426__rt_quad_test_ray_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext426_RT_QUAD_TEST_RAY_COUNT_XECORE18_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE18",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE18",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext426__rt_request_collision_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext426_RT_REQUEST_COLLISION_XECORE18_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE18",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE18",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext426__rt_transform_ray_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext426_RT_TRANSFORM_RAY_COUNT_XECORE18_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE18",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE18",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext426__rt_traversal_input_ray_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext426_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE18_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext427_RT_INPUT_MESSAGE_RAY_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext427_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext427_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext427_RT_MESSAGE_STALL_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext427_RT_QUAD_TEST_RAY_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext427_RT_REQUEST_COLLISION_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext427_RT_TRANSFORM_RAY_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext427_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext427_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext427";
    metric_set->symbol_name = "Ext427";
    metric_set->hw_config_guid = "0ab07bde-21c8-443c-b0b2-0ab740168d29";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext427_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext427__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext427__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext427__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext427__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE19",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE19",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext427__rt_input_message_ray_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext427_RT_INPUT_MESSAGE_RAY_COUNT_XECORE19_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE19",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE19",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext427__rt_load_store_cache_read_message_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext427_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE19_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE19",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE19",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext427__rt_load_store_cache_write_from_message_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext427_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE19_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE19",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE19",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext427__rt_message_stall_count_xecore19__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext427_RT_MESSAGE_STALL_COUNT_XECORE19_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE19",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE19",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext427__rt_quad_test_ray_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext427_RT_QUAD_TEST_RAY_COUNT_XECORE19_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE19",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE19",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext427__rt_request_collision_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext427_RT_REQUEST_COLLISION_XECORE19_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE19",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE19",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext427__rt_transform_ray_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext427_RT_TRANSFORM_RAY_COUNT_XECORE19_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE19",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE19",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext427__rt_traversal_input_ray_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext427_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext428_RT_INPUT_MESSAGE_RAY_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext428_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext428_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext428_RT_MESSAGE_STALL_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext428_RT_QUAD_TEST_RAY_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext428_RT_REQUEST_COLLISION_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext428_RT_TRANSFORM_RAY_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext428_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext428_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext428";
    metric_set->symbol_name = "Ext428";
    metric_set->hw_config_guid = "62a24a66-2325-40b3-a945-6ef37508674a";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext428_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext428__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext428__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext428__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext428__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE20",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE20",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext428__rt_input_message_ray_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext428_RT_INPUT_MESSAGE_RAY_COUNT_XECORE20_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE20",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE20",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext428__rt_load_store_cache_read_message_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext428_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE20_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE20",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE20",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext428__rt_load_store_cache_write_from_message_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext428_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE20_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE20",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE20",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext428__rt_message_stall_count_xecore20__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext428_RT_MESSAGE_STALL_COUNT_XECORE20_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE20",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE20",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext428__rt_quad_test_ray_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext428_RT_QUAD_TEST_RAY_COUNT_XECORE20_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE20",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE20",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext428__rt_request_collision_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext428_RT_REQUEST_COLLISION_XECORE20_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE20",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE20",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext428__rt_transform_ray_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext428_RT_TRANSFORM_RAY_COUNT_XECORE20_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE20",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE20",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext428__rt_traversal_input_ray_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext428_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE20_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext429_RT_INPUT_MESSAGE_RAY_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext429_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext429_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext429_RT_MESSAGE_STALL_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext429_RT_QUAD_TEST_RAY_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext429_RT_REQUEST_COLLISION_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext429_RT_TRANSFORM_RAY_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext429_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext429_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext429";
    metric_set->symbol_name = "Ext429";
    metric_set->hw_config_guid = "47acaafe-6b68-4d1d-a674-8d94ed118606";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext429_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext429__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext429__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext429__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext429__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE21",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE21",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext429__rt_input_message_ray_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext429_RT_INPUT_MESSAGE_RAY_COUNT_XECORE21_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE21",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE21",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext429__rt_load_store_cache_read_message_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext429_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE21_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE21",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE21",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext429__rt_load_store_cache_write_from_message_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext429_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE21_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE21",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE21",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext429__rt_message_stall_count_xecore21__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext429_RT_MESSAGE_STALL_COUNT_XECORE21_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE21",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE21",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext429__rt_quad_test_ray_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext429_RT_QUAD_TEST_RAY_COUNT_XECORE21_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE21",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE21",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext429__rt_request_collision_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext429_RT_REQUEST_COLLISION_XECORE21_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE21",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE21",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext429__rt_transform_ray_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext429_RT_TRANSFORM_RAY_COUNT_XECORE21_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE21",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE21",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext429__rt_traversal_input_ray_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext429_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE21_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext430_RT_INPUT_MESSAGE_RAY_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext430_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext430_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext430_RT_MESSAGE_STALL_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext430_RT_QUAD_TEST_RAY_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext430_RT_REQUEST_COLLISION_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext430_RT_TRANSFORM_RAY_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext430_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext430_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext430";
    metric_set->symbol_name = "Ext430";
    metric_set->hw_config_guid = "72cb7918-7248-437c-ad7f-a0b2b8815148";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext430_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext430__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext430__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext430__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext430__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE22",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE22",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext430__rt_input_message_ray_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext430_RT_INPUT_MESSAGE_RAY_COUNT_XECORE22_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE22",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE22",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext430__rt_load_store_cache_read_message_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext430_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE22_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE22",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE22",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext430__rt_load_store_cache_write_from_message_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext430_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE22_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE22",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE22",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext430__rt_message_stall_count_xecore22__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext430_RT_MESSAGE_STALL_COUNT_XECORE22_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE22",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE22",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext430__rt_quad_test_ray_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext430_RT_QUAD_TEST_RAY_COUNT_XECORE22_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE22",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE22",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext430__rt_request_collision_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext430_RT_REQUEST_COLLISION_XECORE22_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE22",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE22",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext430__rt_transform_ray_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext430_RT_TRANSFORM_RAY_COUNT_XECORE22_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE22",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE22",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext430__rt_traversal_input_ray_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext430_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE22_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext431_RT_INPUT_MESSAGE_RAY_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext431_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext431_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext431_RT_MESSAGE_STALL_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext431_RT_QUAD_TEST_RAY_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext431_RT_REQUEST_COLLISION_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext431_RT_TRANSFORM_RAY_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext431_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext431_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext431";
    metric_set->symbol_name = "Ext431";
    metric_set->hw_config_guid = "0ccfdef6-3cdb-485c-9aba-d3e0040e305e";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext431_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext431__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext431__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext431__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext431__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE23",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE23",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext431__rt_input_message_ray_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext431_RT_INPUT_MESSAGE_RAY_COUNT_XECORE23_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE23",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE23",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext431__rt_load_store_cache_read_message_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext431_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE23_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE23",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE23",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext431__rt_load_store_cache_write_from_message_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext431_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE23_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE23",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE23",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext431__rt_message_stall_count_xecore23__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext431_RT_MESSAGE_STALL_COUNT_XECORE23_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE23",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE23",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext431__rt_quad_test_ray_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext431_RT_QUAD_TEST_RAY_COUNT_XECORE23_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE23",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE23",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext431__rt_request_collision_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext431_RT_REQUEST_COLLISION_XECORE23_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE23",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE23",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext431__rt_transform_ray_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext431_RT_TRANSFORM_RAY_COUNT_XECORE23_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE23",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE23",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext431__rt_traversal_input_ray_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext431_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext432_RT_INPUT_MESSAGE_RAY_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext432_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext432_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext432_RT_MESSAGE_STALL_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext432_RT_QUAD_TEST_RAY_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext432_RT_REQUEST_COLLISION_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext432_RT_TRANSFORM_RAY_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext432_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext432_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext432";
    metric_set->symbol_name = "Ext432";
    metric_set->hw_config_guid = "e9b7707a-c96e-45dd-b513-fae7d7468ddb";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext432_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext432__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext432__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext432__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext432__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE24",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE24",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext432__rt_input_message_ray_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext432_RT_INPUT_MESSAGE_RAY_COUNT_XECORE24_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE24",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE24",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext432__rt_load_store_cache_read_message_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext432_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE24_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE24",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE24",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext432__rt_load_store_cache_write_from_message_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext432_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE24_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE24",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE24",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext432__rt_message_stall_count_xecore24__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext432_RT_MESSAGE_STALL_COUNT_XECORE24_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE24",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE24",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext432__rt_quad_test_ray_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext432_RT_QUAD_TEST_RAY_COUNT_XECORE24_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE24",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE24",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext432__rt_request_collision_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext432_RT_REQUEST_COLLISION_XECORE24_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE24",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE24",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext432__rt_transform_ray_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext432_RT_TRANSFORM_RAY_COUNT_XECORE24_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE24",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE24",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext432__rt_traversal_input_ray_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext432_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE24_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext433_RT_INPUT_MESSAGE_RAY_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext433_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext433_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext433_RT_MESSAGE_STALL_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext433_RT_QUAD_TEST_RAY_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext433_RT_REQUEST_COLLISION_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext433_RT_TRANSFORM_RAY_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext433_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext433_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext433";
    metric_set->symbol_name = "Ext433";
    metric_set->hw_config_guid = "4ecad344-9bda-4c3e-b310-284a9d249028";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext433_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext433__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext433__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext433__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext433__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE25",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE25",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext433__rt_input_message_ray_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext433_RT_INPUT_MESSAGE_RAY_COUNT_XECORE25_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE25",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE25",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext433__rt_load_store_cache_read_message_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext433_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE25_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE25",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE25",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext433__rt_load_store_cache_write_from_message_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext433_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE25_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE25",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE25",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext433__rt_message_stall_count_xecore25__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext433_RT_MESSAGE_STALL_COUNT_XECORE25_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE25",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE25",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext433__rt_quad_test_ray_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext433_RT_QUAD_TEST_RAY_COUNT_XECORE25_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE25",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE25",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext433__rt_request_collision_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext433_RT_REQUEST_COLLISION_XECORE25_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE25",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE25",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext433__rt_transform_ray_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext433_RT_TRANSFORM_RAY_COUNT_XECORE25_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE25",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE25",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext433__rt_traversal_input_ray_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext433_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE25_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext434_RT_INPUT_MESSAGE_RAY_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext434_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext434_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext434_RT_MESSAGE_STALL_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext434_RT_QUAD_TEST_RAY_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext434_RT_REQUEST_COLLISION_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext434_RT_TRANSFORM_RAY_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext434_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext434_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext434";
    metric_set->symbol_name = "Ext434";
    metric_set->hw_config_guid = "ddb99956-0871-42f4-8b6b-dbca21a726ee";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext434_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext434__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext434__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext434__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext434__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE26",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE26",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext434__rt_input_message_ray_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext434_RT_INPUT_MESSAGE_RAY_COUNT_XECORE26_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE26",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE26",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext434__rt_load_store_cache_read_message_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext434_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE26_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE26",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE26",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext434__rt_load_store_cache_write_from_message_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext434_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE26_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE26",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE26",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext434__rt_message_stall_count_xecore26__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext434_RT_MESSAGE_STALL_COUNT_XECORE26_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE26",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE26",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext434__rt_quad_test_ray_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext434_RT_QUAD_TEST_RAY_COUNT_XECORE26_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE26",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE26",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext434__rt_request_collision_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext434_RT_REQUEST_COLLISION_XECORE26_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE26",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE26",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext434__rt_transform_ray_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext434_RT_TRANSFORM_RAY_COUNT_XECORE26_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE26",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE26",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext434__rt_traversal_input_ray_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext434_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE26_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext435_RT_INPUT_MESSAGE_RAY_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext435_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext435_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext435_RT_MESSAGE_STALL_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext435_RT_QUAD_TEST_RAY_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext435_RT_REQUEST_COLLISION_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext435_RT_TRANSFORM_RAY_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext435_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext435_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext435";
    metric_set->symbol_name = "Ext435";
    metric_set->hw_config_guid = "a992c151-134d-4959-879e-2c5b8dc2b98a";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext435_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext435__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext435__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext435__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext435__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE27",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE27",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext435__rt_input_message_ray_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext435_RT_INPUT_MESSAGE_RAY_COUNT_XECORE27_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE27",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE27",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext435__rt_load_store_cache_read_message_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext435_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE27_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE27",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE27",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext435__rt_load_store_cache_write_from_message_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext435_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE27_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE27",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE27",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext435__rt_message_stall_count_xecore27__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext435_RT_MESSAGE_STALL_COUNT_XECORE27_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE27",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE27",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext435__rt_quad_test_ray_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext435_RT_QUAD_TEST_RAY_COUNT_XECORE27_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE27",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE27",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext435__rt_request_collision_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext435_RT_REQUEST_COLLISION_XECORE27_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE27",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE27",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext435__rt_transform_ray_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext435_RT_TRANSFORM_RAY_COUNT_XECORE27_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE27",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE27",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext435__rt_traversal_input_ray_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext435_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext436_RT_INPUT_MESSAGE_RAY_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext436_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext436_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext436_RT_MESSAGE_STALL_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext436_RT_QUAD_TEST_RAY_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext436_RT_REQUEST_COLLISION_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext436_RT_TRANSFORM_RAY_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext436_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext436_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext436";
    metric_set->symbol_name = "Ext436";
    metric_set->hw_config_guid = "05453f6f-3850-4412-9dc5-aacc57dc23ee";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext436_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext436__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext436__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext436__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext436__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE28",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE28",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext436__rt_input_message_ray_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext436_RT_INPUT_MESSAGE_RAY_COUNT_XECORE28_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE28",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE28",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext436__rt_load_store_cache_read_message_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext436_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE28_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE28",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE28",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext436__rt_load_store_cache_write_from_message_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext436_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE28_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE28",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE28",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext436__rt_message_stall_count_xecore28__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext436_RT_MESSAGE_STALL_COUNT_XECORE28_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE28",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE28",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext436__rt_quad_test_ray_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext436_RT_QUAD_TEST_RAY_COUNT_XECORE28_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE28",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE28",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext436__rt_request_collision_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext436_RT_REQUEST_COLLISION_XECORE28_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE28",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE28",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext436__rt_transform_ray_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext436_RT_TRANSFORM_RAY_COUNT_XECORE28_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE28",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE28",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext436__rt_traversal_input_ray_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext436_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE28_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext437_RT_INPUT_MESSAGE_RAY_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext437_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext437_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext437_RT_MESSAGE_STALL_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext437_RT_QUAD_TEST_RAY_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext437_RT_REQUEST_COLLISION_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext437_RT_TRANSFORM_RAY_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext437_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext437_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext437";
    metric_set->symbol_name = "Ext437";
    metric_set->hw_config_guid = "6a863ebb-4f0a-4a6f-81a0-979a0a972ce1";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext437_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext437__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext437__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext437__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext437__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE29",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE29",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext437__rt_input_message_ray_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext437_RT_INPUT_MESSAGE_RAY_COUNT_XECORE29_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE29",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE29",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext437__rt_load_store_cache_read_message_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext437_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE29_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE29",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE29",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext437__rt_load_store_cache_write_from_message_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext437_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE29_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE29",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE29",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext437__rt_message_stall_count_xecore29__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext437_RT_MESSAGE_STALL_COUNT_XECORE29_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE29",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE29",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext437__rt_quad_test_ray_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext437_RT_QUAD_TEST_RAY_COUNT_XECORE29_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE29",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE29",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext437__rt_request_collision_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext437_RT_REQUEST_COLLISION_XECORE29_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE29",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE29",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext437__rt_transform_ray_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext437_RT_TRANSFORM_RAY_COUNT_XECORE29_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE29",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE29",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext437__rt_traversal_input_ray_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext437_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE29_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext438_RT_INPUT_MESSAGE_RAY_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext438_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext438_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext438_RT_MESSAGE_STALL_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext438_RT_QUAD_TEST_RAY_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext438_RT_REQUEST_COLLISION_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext438_RT_TRANSFORM_RAY_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext438_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext438_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext438";
    metric_set->symbol_name = "Ext438";
    metric_set->hw_config_guid = "5b95cc2f-5942-4fe3-be28-8940db9b99bb";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext438_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext438__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext438__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext438__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext438__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE30",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE30",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext438__rt_input_message_ray_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext438_RT_INPUT_MESSAGE_RAY_COUNT_XECORE30_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE30",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE30",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext438__rt_load_store_cache_read_message_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext438_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE30_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE30",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE30",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext438__rt_load_store_cache_write_from_message_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext438_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE30_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE30",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE30",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext438__rt_message_stall_count_xecore30__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext438_RT_MESSAGE_STALL_COUNT_XECORE30_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE30",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE30",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext438__rt_quad_test_ray_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext438_RT_QUAD_TEST_RAY_COUNT_XECORE30_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE30",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE30",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext438__rt_request_collision_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext438_RT_REQUEST_COLLISION_XECORE30_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE30",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE30",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext438__rt_transform_ray_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext438_RT_TRANSFORM_RAY_COUNT_XECORE30_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE30",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE30",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext438__rt_traversal_input_ray_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext438_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE30_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext439_RT_INPUT_MESSAGE_RAY_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext439_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext439_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext439_RT_MESSAGE_STALL_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext439_RT_QUAD_TEST_RAY_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext439_RT_REQUEST_COLLISION_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext439_RT_TRANSFORM_RAY_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext439_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext439_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext439";
    metric_set->symbol_name = "Ext439";
    metric_set->hw_config_guid = "1474625b-322c-439d-90e3-53c245a07f97";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext439_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext439__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext439__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext439__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext439__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE31",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE31",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext439__rt_input_message_ray_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext439_RT_INPUT_MESSAGE_RAY_COUNT_XECORE31_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE31",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE31",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext439__rt_load_store_cache_read_message_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext439_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE31_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE31",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE31",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext439__rt_load_store_cache_write_from_message_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext439_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE31_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE31",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE31",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext439__rt_message_stall_count_xecore31__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext439_RT_MESSAGE_STALL_COUNT_XECORE31_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE31",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE31",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext439__rt_quad_test_ray_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext439_RT_QUAD_TEST_RAY_COUNT_XECORE31_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE31",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE31",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext439__rt_request_collision_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext439_RT_REQUEST_COLLISION_XECORE31_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE31",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE31",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext439__rt_transform_ray_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext439_RT_TRANSFORM_RAY_COUNT_XECORE31_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE31",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE31",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext439__rt_traversal_input_ray_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext439_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext440_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext440_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext440_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext440_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext440_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext440";
    metric_set->symbol_name = "Ext440";
    metric_set->hw_config_guid = "9112768a-99fd-4861-b1b2-ca7eb9a46228";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext440_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext440__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext440__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext440__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext440__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE0",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE0",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext440__rt_traversal_output_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext440_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE1",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE1",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext440__rt_traversal_output_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext440_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE2",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE2",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext440__rt_traversal_output_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext440_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE3",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE3",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext440__rt_traversal_output_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext440_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext441_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext441_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext441_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext441_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext441_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext441";
    metric_set->symbol_name = "Ext441";
    metric_set->hw_config_guid = "f2579b7f-2747-49fd-b5ed-ef10662ce62a";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext441_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext441__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext441__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext441__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext441__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE4",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE4",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext441__rt_traversal_output_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext441_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE5",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE5",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext441__rt_traversal_output_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext441_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE6",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE6",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext441__rt_traversal_output_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext441_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE7",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE7",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext441__rt_traversal_output_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext441_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext442_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext442_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext442_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext442_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext442_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext442";
    metric_set->symbol_name = "Ext442";
    metric_set->hw_config_guid = "f572f1c9-3f61-48e8-9bd1-d58a8cd60520";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext442_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext442__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext442__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext442__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext442__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE10",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE10",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext442__rt_traversal_output_ray_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext442_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE10_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE11",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE11",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext442__rt_traversal_output_ray_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext442_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE11_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE8",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE8",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext442__rt_traversal_output_ray_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext442_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE8_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE9",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE9",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext442__rt_traversal_output_ray_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext442_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext443_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext443_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext443_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext443_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext443_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext443";
    metric_set->symbol_name = "Ext443";
    metric_set->hw_config_guid = "4c923c96-134d-4802-a61f-9c3e50af7e9f";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext443_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext443__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext443__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext443__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext443__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE12",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE12",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext443__rt_traversal_output_ray_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext443_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE12_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE13",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE13",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext443__rt_traversal_output_ray_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext443_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE13_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE14",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE14",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext443__rt_traversal_output_ray_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext443_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE14_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE15",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE15",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext443__rt_traversal_output_ray_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext443_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext444_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext444_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext444_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext444_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext444_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext444";
    metric_set->symbol_name = "Ext444";
    metric_set->hw_config_guid = "c89197d6-8bce-4479-9961-2c50e8ffbcf7";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext444_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext444__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext444__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext444__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext444__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE16",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE16",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext444__rt_traversal_output_ray_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext444_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE16_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE17",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE17",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext444__rt_traversal_output_ray_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext444_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE17_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE18",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE18",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext444__rt_traversal_output_ray_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext444_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE18_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE19",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE19",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext444__rt_traversal_output_ray_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext444_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext445_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext445_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext445_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext445_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext445_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext445";
    metric_set->symbol_name = "Ext445";
    metric_set->hw_config_guid = "87885a48-5d45-47e8-81b3-176db423b454";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext445_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext445__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext445__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext445__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext445__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE20",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE20",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext445__rt_traversal_output_ray_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext445_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE20_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE21",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE21",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext445__rt_traversal_output_ray_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext445_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE21_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE22",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE22",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext445__rt_traversal_output_ray_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext445_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE22_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE23",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE23",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext445__rt_traversal_output_ray_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext445_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext446_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext446_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext446_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext446_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext446_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext446";
    metric_set->symbol_name = "Ext446";
    metric_set->hw_config_guid = "323e04f8-e194-4032-bd1f-159b0131f1bb";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext446_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext446__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext446__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext446__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext446__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE24",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE24",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext446__rt_traversal_output_ray_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext446_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE24_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE25",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE25",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext446__rt_traversal_output_ray_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext446_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE25_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE26",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE26",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext446__rt_traversal_output_ray_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext446_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE26_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE27",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE27",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext446__rt_traversal_output_ray_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext446_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext447_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext447_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext447_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext447_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext447_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext447";
    metric_set->symbol_name = "Ext447";
    metric_set->hw_config_guid = "1999b632-cd36-49ec-a888-0a458f9f5673";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext447_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext447__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext447__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext447__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext447__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE28",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE28",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext447__rt_traversal_output_ray_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext447_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE28_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE29",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE29",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext447__rt_traversal_output_ray_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext447_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE29_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE30",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE30",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext447__rt_traversal_output_ray_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext447_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE30_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE31",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE31",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext447__rt_traversal_output_ray_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext447_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext448_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext448_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext448_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext448_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext448_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext448";
    metric_set->symbol_name = "Ext448";
    metric_set->hw_config_guid = "71487a9a-9e3f-4bee-95b9-cd42969e4278";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext448_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext448__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext448__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext448__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext448__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE0",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE0",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext448__rt_any_hit_thread_ray_dispatch_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext448_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE0_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE1",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE1",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext448__rt_any_hit_thread_ray_dispatch_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext448_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE1_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE2",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE2",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext448__rt_any_hit_thread_ray_dispatch_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext448_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE2_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE3",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE3",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext448__rt_any_hit_thread_ray_dispatch_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext448_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext449_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext449_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext449_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext449_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext449_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext449";
    metric_set->symbol_name = "Ext449";
    metric_set->hw_config_guid = "299dff90-c563-48f4-b1b4-eacf678b6727";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext449_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext449__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext449__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext449__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext449__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE4",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE4",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext449__rt_any_hit_thread_ray_dispatch_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext449_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE4_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE5",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE5",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext449__rt_any_hit_thread_ray_dispatch_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext449_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE5_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE6",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE6",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext449__rt_any_hit_thread_ray_dispatch_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext449_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE6_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE7",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE7",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext449__rt_any_hit_thread_ray_dispatch_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext449_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext450_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext450_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext450_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext450_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext450_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext450";
    metric_set->symbol_name = "Ext450";
    metric_set->hw_config_guid = "85729a73-d105-4f88-9f85-833961661877";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext450_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext450__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext450__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext450__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext450__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE10",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE10",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext450__rt_any_hit_thread_ray_dispatch_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext450_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE10_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE11",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE11",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext450__rt_any_hit_thread_ray_dispatch_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext450_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE11_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE8",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE8",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext450__rt_any_hit_thread_ray_dispatch_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext450_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE8_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE9",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE9",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext450__rt_any_hit_thread_ray_dispatch_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext450_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext451_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext451_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext451_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext451_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext451_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext451";
    metric_set->symbol_name = "Ext451";
    metric_set->hw_config_guid = "74df82fd-abc3-4934-8cb5-cc71324c1816";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext451_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext451__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext451__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext451__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext451__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE12",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE12",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext451__rt_any_hit_thread_ray_dispatch_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext451_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE12_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE13",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE13",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext451__rt_any_hit_thread_ray_dispatch_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext451_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE13_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE14",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE14",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext451__rt_any_hit_thread_ray_dispatch_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext451_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE14_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE15",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE15",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext451__rt_any_hit_thread_ray_dispatch_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext451_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext452_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext452_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext452_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext452_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext452_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext452";
    metric_set->symbol_name = "Ext452";
    metric_set->hw_config_guid = "d1c28b9e-8ce0-4750-bf4b-ec446d4c3916";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext452_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext452__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext452__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext452__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext452__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE16",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE16",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext452__rt_any_hit_thread_ray_dispatch_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext452_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE16_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE17",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE17",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext452__rt_any_hit_thread_ray_dispatch_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext452_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE17_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE18",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE18",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext452__rt_any_hit_thread_ray_dispatch_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext452_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE18_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE19",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE19",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext452__rt_any_hit_thread_ray_dispatch_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext452_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext453_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext453_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext453_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext453_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext453_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext453";
    metric_set->symbol_name = "Ext453";
    metric_set->hw_config_guid = "56876ce8-6162-4812-a5ff-acdf8b896a9c";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext453_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext453__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext453__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext453__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext453__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE20",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE20",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext453__rt_any_hit_thread_ray_dispatch_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext453_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE20_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE21",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE21",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext453__rt_any_hit_thread_ray_dispatch_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext453_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE21_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE22",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE22",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext453__rt_any_hit_thread_ray_dispatch_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext453_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE22_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE23",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE23",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext453__rt_any_hit_thread_ray_dispatch_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext453_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext454_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext454_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext454_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext454_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext454_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext454";
    metric_set->symbol_name = "Ext454";
    metric_set->hw_config_guid = "4c84ebed-5683-417b-8b31-d60919bdf00e";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext454_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext454__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext454__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext454__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext454__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE24",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE24",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext454__rt_any_hit_thread_ray_dispatch_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext454_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE24_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE25",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE25",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext454__rt_any_hit_thread_ray_dispatch_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext454_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE25_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE26",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE26",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext454__rt_any_hit_thread_ray_dispatch_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext454_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE26_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE27",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE27",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext454__rt_any_hit_thread_ray_dispatch_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext454_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext455_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext455_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext455_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext455_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext455_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext455";
    metric_set->symbol_name = "Ext455";
    metric_set->hw_config_guid = "870f786b-e570-427d-868d-bdead22a485d";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext455_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext455__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext455__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext455__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext455__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE28",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE28",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext455__rt_any_hit_thread_ray_dispatch_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext455_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE28_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE29",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE29",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext455__rt_any_hit_thread_ray_dispatch_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext455_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE29_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE30",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE30",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext455__rt_any_hit_thread_ray_dispatch_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext455_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE30_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE31",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE31",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext455__rt_any_hit_thread_ray_dispatch_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext455_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext456_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext456_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext456_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext456_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext456_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext456";
    metric_set->symbol_name = "Ext456";
    metric_set->hw_config_guid = "7385d290-7061-4248-8b13-ac4abe1212d6";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext456_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext456__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext456__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext456__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext456__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE0",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE0",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext456__rt_callable_thread_ray_dispatch_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext456_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE0_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE1",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE1",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext456__rt_callable_thread_ray_dispatch_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext456_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE1_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE2",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE2",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext456__rt_callable_thread_ray_dispatch_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext456_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE2_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE3",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE3",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext456__rt_callable_thread_ray_dispatch_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext456_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext457_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext457_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext457_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext457_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext457_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext457";
    metric_set->symbol_name = "Ext457";
    metric_set->hw_config_guid = "e92a854c-ef93-44fe-a9c9-2e564fd57215";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext457_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext457__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext457__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext457__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext457__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE4",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE4",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext457__rt_callable_thread_ray_dispatch_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext457_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE4_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE5",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE5",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext457__rt_callable_thread_ray_dispatch_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext457_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE5_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE6",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE6",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext457__rt_callable_thread_ray_dispatch_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext457_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE6_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE7",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE7",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext457__rt_callable_thread_ray_dispatch_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext457_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext458_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext458_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext458_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext458_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext458_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext458";
    metric_set->symbol_name = "Ext458";
    metric_set->hw_config_guid = "0839f197-8c02-4ab5-adee-f26d39d57060";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext458_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext458__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext458__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext458__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext458__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE10",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE10",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext458__rt_callable_thread_ray_dispatch_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext458_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE10_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE11",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE11",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext458__rt_callable_thread_ray_dispatch_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext458_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE11_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE8",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE8",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext458__rt_callable_thread_ray_dispatch_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext458_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE8_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE9",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE9",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext458__rt_callable_thread_ray_dispatch_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext458_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext459_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext459_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext459_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext459_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext459_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext459";
    metric_set->symbol_name = "Ext459";
    metric_set->hw_config_guid = "b39c926c-557f-42d6-9ab8-3dc749774ca2";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext459_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext459__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext459__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext459__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext459__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE12",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE12",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext459__rt_callable_thread_ray_dispatch_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext459_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE12_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE13",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE13",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext459__rt_callable_thread_ray_dispatch_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext459_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE13_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE14",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE14",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext459__rt_callable_thread_ray_dispatch_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext459_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE14_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE15",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE15",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext459__rt_callable_thread_ray_dispatch_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext459_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext460_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext460_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext460_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext460_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext460_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext460";
    metric_set->symbol_name = "Ext460";
    metric_set->hw_config_guid = "9a7989c1-a520-4785-9aeb-f522bb692de6";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext460_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext460__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext460__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext460__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext460__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE16",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE16",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext460__rt_callable_thread_ray_dispatch_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext460_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE16_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE17",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE17",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext460__rt_callable_thread_ray_dispatch_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext460_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE17_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE18",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE18",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext460__rt_callable_thread_ray_dispatch_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext460_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE18_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE19",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE19",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext460__rt_callable_thread_ray_dispatch_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext460_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext461_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext461_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext461_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext461_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext461_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext461";
    metric_set->symbol_name = "Ext461";
    metric_set->hw_config_guid = "6eb94cf4-077d-4d52-89c6-272cb33fd9bc";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext461_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext461__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext461__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext461__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext461__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE20",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE20",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext461__rt_callable_thread_ray_dispatch_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext461_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE20_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE21",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE21",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext461__rt_callable_thread_ray_dispatch_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext461_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE21_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE22",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE22",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext461__rt_callable_thread_ray_dispatch_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext461_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE22_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE23",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE23",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext461__rt_callable_thread_ray_dispatch_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext461_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext462_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext462_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext462_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext462_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext462_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext462";
    metric_set->symbol_name = "Ext462";
    metric_set->hw_config_guid = "a50d2370-c6ff-4a53-a6dc-b9523562b371";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext462_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext462__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext462__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext462__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext462__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE24",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE24",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext462__rt_callable_thread_ray_dispatch_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext462_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE24_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE25",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE25",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext462__rt_callable_thread_ray_dispatch_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext462_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE25_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE26",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE26",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext462__rt_callable_thread_ray_dispatch_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext462_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE26_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE27",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE27",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext462__rt_callable_thread_ray_dispatch_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext462_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext463_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext463_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext463_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext463_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext463_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext463";
    metric_set->symbol_name = "Ext463";
    metric_set->hw_config_guid = "b737779b-4652-4892-be0b-aa8764d116ba";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext463_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext463__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext463__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext463__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext463__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE28",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE28",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext463__rt_callable_thread_ray_dispatch_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext463_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE28_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE29",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE29",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext463__rt_callable_thread_ray_dispatch_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext463_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE29_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE30",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE30",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext463__rt_callable_thread_ray_dispatch_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext463_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE30_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE31",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE31",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext463__rt_callable_thread_ray_dispatch_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext463_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext464_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext464_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext464_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext464_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext464_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext464";
    metric_set->symbol_name = "Ext464";
    metric_set->hw_config_guid = "447d463d-77e3-4bb4-9f02-7523eefa3549";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext464_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext464__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext464__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext464__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext464__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE0",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE0",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext464__rt_closest_hit_thread_ray_dispatch_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext464_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE0_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE1",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE1",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext464__rt_closest_hit_thread_ray_dispatch_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext464_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE1_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE2",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE2",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext464__rt_closest_hit_thread_ray_dispatch_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext464_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE2_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE3",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE3",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext464__rt_closest_hit_thread_ray_dispatch_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext464_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext465_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext465_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext465_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext465_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext465_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext465";
    metric_set->symbol_name = "Ext465";
    metric_set->hw_config_guid = "0b0dd8de-3217-4d32-9033-988a7a4a2f59";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext465_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext465__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext465__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext465__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext465__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE4",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE4",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext465__rt_closest_hit_thread_ray_dispatch_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext465_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE4_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE5",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE5",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext465__rt_closest_hit_thread_ray_dispatch_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext465_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE5_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE6",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE6",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext465__rt_closest_hit_thread_ray_dispatch_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext465_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE6_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE7",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE7",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext465__rt_closest_hit_thread_ray_dispatch_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext465_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext466_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext466_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext466_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext466_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext466_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext466";
    metric_set->symbol_name = "Ext466";
    metric_set->hw_config_guid = "46a09e7c-f9e1-4eba-ac1c-4151dc54d51f";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext466_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext466__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext466__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext466__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext466__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE10",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE10",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext466__rt_closest_hit_thread_ray_dispatch_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext466_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE10_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE11",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE11",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext466__rt_closest_hit_thread_ray_dispatch_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext466_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE11_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE8",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE8",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext466__rt_closest_hit_thread_ray_dispatch_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext466_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE8_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE9",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE9",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext466__rt_closest_hit_thread_ray_dispatch_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext466_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext467_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext467_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext467_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext467_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext467_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext467";
    metric_set->symbol_name = "Ext467";
    metric_set->hw_config_guid = "59c513fe-9984-455b-9b07-5b5f02c36e70";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext467_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext467__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext467__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext467__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext467__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE12",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE12",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext467__rt_closest_hit_thread_ray_dispatch_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext467_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE12_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE13",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE13",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext467__rt_closest_hit_thread_ray_dispatch_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext467_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE13_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE14",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE14",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext467__rt_closest_hit_thread_ray_dispatch_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext467_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE14_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE15",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE15",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext467__rt_closest_hit_thread_ray_dispatch_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext467_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext468_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext468_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext468_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext468_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext468_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext468";
    metric_set->symbol_name = "Ext468";
    metric_set->hw_config_guid = "aa729499-9f35-436d-91ad-7100098dfd47";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext468_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext468__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext468__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext468__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext468__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE16",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE16",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext468__rt_closest_hit_thread_ray_dispatch_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext468_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE16_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE17",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE17",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext468__rt_closest_hit_thread_ray_dispatch_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext468_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE17_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE18",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE18",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext468__rt_closest_hit_thread_ray_dispatch_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext468_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE18_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE19",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE19",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext468__rt_closest_hit_thread_ray_dispatch_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext468_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext469_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext469_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext469_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext469_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext469_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext469";
    metric_set->symbol_name = "Ext469";
    metric_set->hw_config_guid = "dea127d1-19d5-4298-b9d6-cf4a21be1563";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext469_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext469__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext469__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext469__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext469__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE20",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE20",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext469__rt_closest_hit_thread_ray_dispatch_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext469_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE20_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE21",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE21",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext469__rt_closest_hit_thread_ray_dispatch_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext469_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE21_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE22",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE22",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext469__rt_closest_hit_thread_ray_dispatch_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext469_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE22_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE23",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE23",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext469__rt_closest_hit_thread_ray_dispatch_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext469_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext470_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext470_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext470_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext470_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext470_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext470";
    metric_set->symbol_name = "Ext470";
    metric_set->hw_config_guid = "1dc79687-d7a2-4c2d-b810-0a6d5db141f6";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext470_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext470__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext470__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext470__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext470__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE24",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE24",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext470__rt_closest_hit_thread_ray_dispatch_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext470_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE24_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE25",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE25",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext470__rt_closest_hit_thread_ray_dispatch_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext470_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE25_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE26",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE26",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext470__rt_closest_hit_thread_ray_dispatch_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext470_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE26_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE27",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE27",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext470__rt_closest_hit_thread_ray_dispatch_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext470_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext471_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext471_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext471_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext471_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext471_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext471";
    metric_set->symbol_name = "Ext471";
    metric_set->hw_config_guid = "4487fcbd-dcf6-4f08-9512-1cadbd7f246b";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext471_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext471__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext471__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext471__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext471__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE28",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE28",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext471__rt_closest_hit_thread_ray_dispatch_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext471_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE28_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE29",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE29",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext471__rt_closest_hit_thread_ray_dispatch_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext471_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE29_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE30",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE30",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext471__rt_closest_hit_thread_ray_dispatch_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext471_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE30_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE31",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE31",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext471__rt_closest_hit_thread_ray_dispatch_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext471_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext472_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext472_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext472_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext472_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext472_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext472";
    metric_set->symbol_name = "Ext472";
    metric_set->hw_config_guid = "641f5e4b-0404-456f-9aca-03154415cd34";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext472_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext472__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext472__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext472__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext472__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE0",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE0",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext472__rt_intersection_thread_ray_dispatch_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext472_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE0_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE1",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE1",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext472__rt_intersection_thread_ray_dispatch_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext472_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE1_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE2",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE2",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext472__rt_intersection_thread_ray_dispatch_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext472_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE2_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE3",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE3",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext472__rt_intersection_thread_ray_dispatch_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext472_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext473_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext473_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext473_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext473_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext473_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext473";
    metric_set->symbol_name = "Ext473";
    metric_set->hw_config_guid = "2055dfa1-2b3c-4939-b905-dc3cfc8a5124";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext473_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext473__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext473__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext473__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext473__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE4",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE4",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext473__rt_intersection_thread_ray_dispatch_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext473_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE4_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE5",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE5",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext473__rt_intersection_thread_ray_dispatch_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext473_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE5_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE6",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE6",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext473__rt_intersection_thread_ray_dispatch_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext473_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE6_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE7",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE7",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext473__rt_intersection_thread_ray_dispatch_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext473_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext474_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext474_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext474_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext474_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext474_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext474";
    metric_set->symbol_name = "Ext474";
    metric_set->hw_config_guid = "c16b25d4-0460-43ca-a0c0-eb198877b615";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext474_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext474__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext474__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext474__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext474__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE10",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE10",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext474__rt_intersection_thread_ray_dispatch_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext474_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE10_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE11",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE11",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext474__rt_intersection_thread_ray_dispatch_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext474_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE11_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE8",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE8",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext474__rt_intersection_thread_ray_dispatch_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext474_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE8_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE9",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE9",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext474__rt_intersection_thread_ray_dispatch_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext474_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext475_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext475_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext475_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext475_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext475_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext475";
    metric_set->symbol_name = "Ext475";
    metric_set->hw_config_guid = "939bce80-8718-4d3d-99ff-7908d07f7ca5";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext475_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext475__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext475__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext475__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext475__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE12",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE12",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext475__rt_intersection_thread_ray_dispatch_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext475_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE12_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE13",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE13",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext475__rt_intersection_thread_ray_dispatch_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext475_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE13_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE14",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE14",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext475__rt_intersection_thread_ray_dispatch_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext475_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE14_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE15",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE15",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext475__rt_intersection_thread_ray_dispatch_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext475_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext476_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext476_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext476_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext476_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext476_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext476";
    metric_set->symbol_name = "Ext476";
    metric_set->hw_config_guid = "d7cce1dc-00c2-4548-a0cd-469134c446b5";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext476_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext476__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext476__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext476__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext476__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE16",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE16",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext476__rt_intersection_thread_ray_dispatch_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext476_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE16_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE17",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE17",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext476__rt_intersection_thread_ray_dispatch_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext476_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE17_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE18",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE18",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext476__rt_intersection_thread_ray_dispatch_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext476_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE18_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE19",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE19",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext476__rt_intersection_thread_ray_dispatch_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext476_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext477_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext477_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext477_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext477_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext477_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext477";
    metric_set->symbol_name = "Ext477";
    metric_set->hw_config_guid = "c939c362-8ff8-4c4c-857f-c429c61dbaee";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext477_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext477__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext477__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext477__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext477__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE20",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE20",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext477__rt_intersection_thread_ray_dispatch_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext477_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE20_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE21",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE21",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext477__rt_intersection_thread_ray_dispatch_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext477_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE21_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE22",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE22",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext477__rt_intersection_thread_ray_dispatch_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext477_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE22_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE23",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE23",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext477__rt_intersection_thread_ray_dispatch_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext477_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext478_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext478_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext478_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext478_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext478_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext478";
    metric_set->symbol_name = "Ext478";
    metric_set->hw_config_guid = "59ec69a0-17fb-4d3a-b303-8463a4631464";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext478_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext478__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext478__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext478__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext478__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE24",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE24",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext478__rt_intersection_thread_ray_dispatch_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext478_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE24_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE25",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE25",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext478__rt_intersection_thread_ray_dispatch_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext478_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE25_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE26",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE26",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext478__rt_intersection_thread_ray_dispatch_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext478_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE26_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE27",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE27",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext478__rt_intersection_thread_ray_dispatch_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext478_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext479_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext479_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext479_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext479_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext479_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext479";
    metric_set->symbol_name = "Ext479";
    metric_set->hw_config_guid = "8e1b82ed-be18-45ae-88e5-2e3dfe96935f";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext479_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext479__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext479__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext479__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext479__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE28",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE28",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext479__rt_intersection_thread_ray_dispatch_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext479_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE28_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE29",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE29",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext479__rt_intersection_thread_ray_dispatch_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext479_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE29_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE30",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE30",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext479__rt_intersection_thread_ray_dispatch_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext479_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE30_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE31",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE31",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext479__rt_intersection_thread_ray_dispatch_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext479_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext480_RT_MISS_THREAD_RAY_DISPATCH_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext480_RT_MISS_THREAD_RAY_DISPATCH_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext480_RT_MISS_THREAD_RAY_DISPATCH_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext480_RT_MISS_THREAD_RAY_DISPATCH_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext480_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext480";
    metric_set->symbol_name = "Ext480";
    metric_set->hw_config_guid = "c4e0c25a-5e43-4238-a7c9-6cca88251495";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext480_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext480__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext480__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext480__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext480__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE0",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE0",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext480__rt_miss_thread_ray_dispatch_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext480_RT_MISS_THREAD_RAY_DISPATCH_XECORE0_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE1",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE1",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext480__rt_miss_thread_ray_dispatch_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext480_RT_MISS_THREAD_RAY_DISPATCH_XECORE1_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE2",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE2",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext480__rt_miss_thread_ray_dispatch_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext480_RT_MISS_THREAD_RAY_DISPATCH_XECORE2_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE3",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE3",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext480__rt_miss_thread_ray_dispatch_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext480_RT_MISS_THREAD_RAY_DISPATCH_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext481_RT_MISS_THREAD_RAY_DISPATCH_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext481_RT_MISS_THREAD_RAY_DISPATCH_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext481_RT_MISS_THREAD_RAY_DISPATCH_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext481_RT_MISS_THREAD_RAY_DISPATCH_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext481_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext481";
    metric_set->symbol_name = "Ext481";
    metric_set->hw_config_guid = "d70cd6f5-4ec0-4645-9654-c619926928d3";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext481_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext481__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext481__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext481__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext481__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE4",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE4",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext481__rt_miss_thread_ray_dispatch_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext481_RT_MISS_THREAD_RAY_DISPATCH_XECORE4_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE5",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE5",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext481__rt_miss_thread_ray_dispatch_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext481_RT_MISS_THREAD_RAY_DISPATCH_XECORE5_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE6",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE6",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext481__rt_miss_thread_ray_dispatch_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext481_RT_MISS_THREAD_RAY_DISPATCH_XECORE6_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE7",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE7",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext481__rt_miss_thread_ray_dispatch_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext481_RT_MISS_THREAD_RAY_DISPATCH_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext482_RT_MISS_THREAD_RAY_DISPATCH_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext482_RT_MISS_THREAD_RAY_DISPATCH_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext482_RT_MISS_THREAD_RAY_DISPATCH_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext482_RT_MISS_THREAD_RAY_DISPATCH_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext482_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext482";
    metric_set->symbol_name = "Ext482";
    metric_set->hw_config_guid = "d7028d09-39d0-4009-996f-a4b193ee726a";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext482_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext482__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext482__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext482__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext482__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE10",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE10",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext482__rt_miss_thread_ray_dispatch_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext482_RT_MISS_THREAD_RAY_DISPATCH_XECORE10_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE11",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE11",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext482__rt_miss_thread_ray_dispatch_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext482_RT_MISS_THREAD_RAY_DISPATCH_XECORE11_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE8",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE8",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext482__rt_miss_thread_ray_dispatch_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext482_RT_MISS_THREAD_RAY_DISPATCH_XECORE8_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE9",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE9",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext482__rt_miss_thread_ray_dispatch_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext482_RT_MISS_THREAD_RAY_DISPATCH_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext483_RT_MISS_THREAD_RAY_DISPATCH_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext483_RT_MISS_THREAD_RAY_DISPATCH_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext483_RT_MISS_THREAD_RAY_DISPATCH_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext483_RT_MISS_THREAD_RAY_DISPATCH_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext483_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext483";
    metric_set->symbol_name = "Ext483";
    metric_set->hw_config_guid = "096dd150-0f36-4af1-a2e3-2a309d19ff11";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext483_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext483__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext483__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext483__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext483__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE12",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE12",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext483__rt_miss_thread_ray_dispatch_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext483_RT_MISS_THREAD_RAY_DISPATCH_XECORE12_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE13",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE13",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext483__rt_miss_thread_ray_dispatch_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext483_RT_MISS_THREAD_RAY_DISPATCH_XECORE13_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE14",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE14",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext483__rt_miss_thread_ray_dispatch_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext483_RT_MISS_THREAD_RAY_DISPATCH_XECORE14_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE15",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE15",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext483__rt_miss_thread_ray_dispatch_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext483_RT_MISS_THREAD_RAY_DISPATCH_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext484_RT_MISS_THREAD_RAY_DISPATCH_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext484_RT_MISS_THREAD_RAY_DISPATCH_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext484_RT_MISS_THREAD_RAY_DISPATCH_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext484_RT_MISS_THREAD_RAY_DISPATCH_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext484_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext484";
    metric_set->symbol_name = "Ext484";
    metric_set->hw_config_guid = "a3d45e15-66d1-44f4-8e1d-a0c131cf0c20";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext484_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext484__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext484__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext484__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext484__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE16",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE16",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext484__rt_miss_thread_ray_dispatch_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext484_RT_MISS_THREAD_RAY_DISPATCH_XECORE16_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE17",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE17",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext484__rt_miss_thread_ray_dispatch_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext484_RT_MISS_THREAD_RAY_DISPATCH_XECORE17_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE18",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE18",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext484__rt_miss_thread_ray_dispatch_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext484_RT_MISS_THREAD_RAY_DISPATCH_XECORE18_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE19",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE19",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext484__rt_miss_thread_ray_dispatch_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext484_RT_MISS_THREAD_RAY_DISPATCH_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext485_RT_MISS_THREAD_RAY_DISPATCH_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext485_RT_MISS_THREAD_RAY_DISPATCH_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext485_RT_MISS_THREAD_RAY_DISPATCH_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext485_RT_MISS_THREAD_RAY_DISPATCH_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext485_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext485";
    metric_set->symbol_name = "Ext485";
    metric_set->hw_config_guid = "26fe4473-14e3-4ec4-825b-edec00c9c60e";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext485_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext485__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext485__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext485__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext485__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE20",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE20",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext485__rt_miss_thread_ray_dispatch_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext485_RT_MISS_THREAD_RAY_DISPATCH_XECORE20_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE21",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE21",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext485__rt_miss_thread_ray_dispatch_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext485_RT_MISS_THREAD_RAY_DISPATCH_XECORE21_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE22",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE22",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext485__rt_miss_thread_ray_dispatch_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext485_RT_MISS_THREAD_RAY_DISPATCH_XECORE22_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE23",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE23",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext485__rt_miss_thread_ray_dispatch_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext485_RT_MISS_THREAD_RAY_DISPATCH_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext486_RT_MISS_THREAD_RAY_DISPATCH_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext486_RT_MISS_THREAD_RAY_DISPATCH_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext486_RT_MISS_THREAD_RAY_DISPATCH_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext486_RT_MISS_THREAD_RAY_DISPATCH_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext486_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext486";
    metric_set->symbol_name = "Ext486";
    metric_set->hw_config_guid = "5743595a-ce3d-4942-b5e1-60f90bfe6d15";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext486_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext486__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext486__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext486__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext486__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE24",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE24",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext486__rt_miss_thread_ray_dispatch_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext486_RT_MISS_THREAD_RAY_DISPATCH_XECORE24_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE25",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE25",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext486__rt_miss_thread_ray_dispatch_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext486_RT_MISS_THREAD_RAY_DISPATCH_XECORE25_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE26",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE26",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext486__rt_miss_thread_ray_dispatch_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext486_RT_MISS_THREAD_RAY_DISPATCH_XECORE26_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE27",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE27",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext486__rt_miss_thread_ray_dispatch_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext486_RT_MISS_THREAD_RAY_DISPATCH_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext487_RT_MISS_THREAD_RAY_DISPATCH_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext487_RT_MISS_THREAD_RAY_DISPATCH_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext487_RT_MISS_THREAD_RAY_DISPATCH_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext487_RT_MISS_THREAD_RAY_DISPATCH_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext487_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext487";
    metric_set->symbol_name = "Ext487";
    metric_set->hw_config_guid = "bcce765d-4327-4ce9-8dc4-beae0d4c8738";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext487_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext487__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext487__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext487__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext487__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE28",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE28",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext487__rt_miss_thread_ray_dispatch_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext487_RT_MISS_THREAD_RAY_DISPATCH_XECORE28_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE29",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE29",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext487__rt_miss_thread_ray_dispatch_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext487_RT_MISS_THREAD_RAY_DISPATCH_XECORE29_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE30",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE30",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext487__rt_miss_thread_ray_dispatch_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext487_RT_MISS_THREAD_RAY_DISPATCH_XECORE30_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE31",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE31",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext487__rt_miss_thread_ray_dispatch_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext487_RT_MISS_THREAD_RAY_DISPATCH_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext488_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext488_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext488_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext488";
    metric_set->symbol_name = "Ext488";
    metric_set->hw_config_guid = "075a4845-117c-4d77-b2b2-b7184a875516";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext488_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext488__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext488__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE0",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE0",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext488__early_depth_stencil_test_fail_np_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext488_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE0_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE0",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE0",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext488__early_depth_stencil_test_fail_p_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext488_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE0_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext488__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext488__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext489_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext489_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext489_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext489";
    metric_set->symbol_name = "Ext489";
    metric_set->hw_config_guid = "4a9f4ce9-4ca3-4bbe-ac73-5f4299841575";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext489_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext489__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext489__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE1",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE1",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext489__early_depth_stencil_test_fail_np_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext489_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE1_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE1",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE1",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext489__early_depth_stencil_test_fail_p_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext489_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE1_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext489__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext489__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext490_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext490_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext490_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext490";
    metric_set->symbol_name = "Ext490";
    metric_set->hw_config_guid = "f24a588d-b6e3-411c-a4ba-7fe5ce65bb18";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext490_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext490__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext490__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE2",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE2",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext490__early_depth_stencil_test_fail_np_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext490_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE2_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE2",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE2",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext490__early_depth_stencil_test_fail_p_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext490_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE2_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext490__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext490__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext491_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext491_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext491_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext491";
    metric_set->symbol_name = "Ext491";
    metric_set->hw_config_guid = "70b12fa6-060d-4c67-971b-1c5c6b4fd058";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext491_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext491__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext491__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE3",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE3",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext491__early_depth_stencil_test_fail_np_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext491_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE3_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE3",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE3",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext491__early_depth_stencil_test_fail_p_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext491_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext491__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext491__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext492_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext492_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext492_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext492";
    metric_set->symbol_name = "Ext492";
    metric_set->hw_config_guid = "0a0b3e8f-9f83-4a85-a594-dd6fb87dc2ff";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext492_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext492__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext492__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE4",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE4",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext492__early_depth_stencil_test_fail_np_zpipe4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext492_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE4_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE4",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE4",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext492__early_depth_stencil_test_fail_p_zpipe4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext492_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE4_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext492__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext492__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext493_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext493_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext493_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext493";
    metric_set->symbol_name = "Ext493";
    metric_set->hw_config_guid = "413ee32f-ea00-431f-b325-39bb65fa8a82";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext493_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext493__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext493__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE5",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE5",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext493__early_depth_stencil_test_fail_np_zpipe5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext493_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE5_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE5",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE5",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext493__early_depth_stencil_test_fail_p_zpipe5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext493_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE5_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext493__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext493__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext494_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext494_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext494_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext494";
    metric_set->symbol_name = "Ext494";
    metric_set->hw_config_guid = "7a411505-9241-4b5e-b609-5c4788bbcb6c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext494_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext494__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext494__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE6",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE6",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext494__early_depth_stencil_test_fail_np_zpipe6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext494_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE6_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE6",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE6",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext494__early_depth_stencil_test_fail_p_zpipe6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext494_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE6_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext494__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext494__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext495_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext495_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext495_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext495";
    metric_set->symbol_name = "Ext495";
    metric_set->hw_config_guid = "6db60455-95d8-4fe1-8205-194b741b7f9f";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext495_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext495__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext495__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE7",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE7",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext495__early_depth_stencil_test_fail_np_zpipe7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext495_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE7_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE7",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE7",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext495__early_depth_stencil_test_fail_p_zpipe7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext495_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext495__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext495__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext496_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext496_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext496_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext496";
    metric_set->symbol_name = "Ext496";
    metric_set->hw_config_guid = "2b445bfb-5e26-4638-9831-6d3108343565";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext496_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext496__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext496__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE8",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE8",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext496__early_depth_stencil_test_fail_np_zpipe8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext496_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE8_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE8",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE8",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext496__early_depth_stencil_test_fail_p_zpipe8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext496_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE8_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext496__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext496__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext497_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext497_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext497_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext497";
    metric_set->symbol_name = "Ext497";
    metric_set->hw_config_guid = "5f3eb4c5-fc54-471b-9f82-54de40bcbc96";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext497_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext497__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext497__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE9",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE9",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext497__early_depth_stencil_test_fail_np_zpipe9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext497_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE9_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE9",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE9",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext497__early_depth_stencil_test_fail_p_zpipe9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext497_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext497__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext497__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext498_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext498_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext498_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext498";
    metric_set->symbol_name = "Ext498";
    metric_set->hw_config_guid = "8ab9e563-9c33-4b0f-adde-029bd2cd484c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext498_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext498__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext498__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE10",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE10",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext498__early_depth_stencil_test_fail_np_zpipe10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext498_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE10_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE10",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE10",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext498__early_depth_stencil_test_fail_p_zpipe10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext498_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE10_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext498__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext498__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext499_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext499_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext499_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext499";
    metric_set->symbol_name = "Ext499";
    metric_set->hw_config_guid = "2d96310e-89ce-4f66-b558-0b253531b58f";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext499_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext499__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext499__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE11",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE11",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext499__early_depth_stencil_test_fail_np_zpipe11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext499_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE11_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE11",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE11",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext499__early_depth_stencil_test_fail_p_zpipe11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext499_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE11_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext499__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext499__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext500_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext500_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext500_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext500";
    metric_set->symbol_name = "Ext500";
    metric_set->hw_config_guid = "a9c29325-cfab-4d4b-be96-75c69b8ce57f";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext500_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext500__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext500__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE12",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE12",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext500__early_depth_stencil_test_fail_np_zpipe12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext500_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE12_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE12",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE12",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext500__early_depth_stencil_test_fail_p_zpipe12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext500_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE12_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext500__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext500__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext501_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext501_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext501_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext501";
    metric_set->symbol_name = "Ext501";
    metric_set->hw_config_guid = "262f0b30-997e-4ee1-85e6-6d6647a17611";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext501_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext501__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext501__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE13",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE13",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext501__early_depth_stencil_test_fail_np_zpipe13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext501_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE13_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE13",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE13",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext501__early_depth_stencil_test_fail_p_zpipe13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext501_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE13_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext501__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext501__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext502_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext502_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext502_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext502";
    metric_set->symbol_name = "Ext502";
    metric_set->hw_config_guid = "07b710c4-da24-46fa-bd26-5e761066024a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext502_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext502__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext502__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE14",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE14",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext502__early_depth_stencil_test_fail_np_zpipe14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext502_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE14_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE14",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE14",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext502__early_depth_stencil_test_fail_p_zpipe14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext502_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE14_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext502__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext502__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext503_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext503_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext503_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext503";
    metric_set->symbol_name = "Ext503";
    metric_set->hw_config_guid = "0b727214-7830-4c26-a3e4-7dd5c446083f";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext503_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext503__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext503__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE15",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE15",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext503__early_depth_stencil_test_fail_np_zpipe15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext503_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE15_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE15",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE15",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext503__early_depth_stencil_test_fail_p_zpipe15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext503_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE15_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext503__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext503__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext504_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext504_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext504";
    metric_set->symbol_name = "Ext504";
    metric_set->hw_config_guid = "1864f248-2169-4ae4-aae4-a16c2ddd0a86";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext504_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext504__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext504__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext504__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext504__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE0",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE0",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext504__hiz_depth_test_ambig_np_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext504_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext505_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext505_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext505";
    metric_set->symbol_name = "Ext505";
    metric_set->hw_config_guid = "8e644770-9bee-40ab-8a9b-359bf441e5d5";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext505_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext505__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext505__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext505__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext505__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE1",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE1",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext505__hiz_depth_test_ambig_np_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext505_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext506_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext506_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext506";
    metric_set->symbol_name = "Ext506";
    metric_set->hw_config_guid = "2c979a9c-11b5-4d43-bf6b-6f89a4e93dd6";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext506_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext506__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext506__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext506__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext506__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE2",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE2",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext506__hiz_depth_test_ambig_np_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext506_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext507_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext507_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext507";
    metric_set->symbol_name = "Ext507";
    metric_set->hw_config_guid = "2f346753-30a5-4c6c-b6bb-5b5605a42cb1";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext507_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext507__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext507__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext507__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext507__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE3",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE3",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext507__hiz_depth_test_ambig_np_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext507_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext508_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext508_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext508";
    metric_set->symbol_name = "Ext508";
    metric_set->hw_config_guid = "4e07923a-091a-49c7-b823-b63e43c6fa19";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext508_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext508__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext508__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext508__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext508__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE4",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE4",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext508__hiz_depth_test_ambig_np_zpipe4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext508_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext509_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext509_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext509";
    metric_set->symbol_name = "Ext509";
    metric_set->hw_config_guid = "58350136-7dcd-4d4a-84eb-98cf90542527";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext509_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext509__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext509__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext509__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext509__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE5",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE5",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext509__hiz_depth_test_ambig_np_zpipe5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext509_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext510_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext510_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext510";
    metric_set->symbol_name = "Ext510";
    metric_set->hw_config_guid = "8048a7fc-5649-47d1-a5d6-eec5249fe69b";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext510_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext510__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext510__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext510__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext510__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE6",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE6",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext510__hiz_depth_test_ambig_np_zpipe6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext510_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext511_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext511_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext511";
    metric_set->symbol_name = "Ext511";
    metric_set->hw_config_guid = "a9829627-0ebb-4f96-b62c-66c235fb73b5";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext511_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext511__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext511__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext511__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext511__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE7",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE7",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext511__hiz_depth_test_ambig_np_zpipe7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext511_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext512_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext512_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext512";
    metric_set->symbol_name = "Ext512";
    metric_set->hw_config_guid = "602d5bcc-18e2-4679-a253-b8447ae2934c";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext512_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext512__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext512__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext512__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext512__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE8",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE8",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext512__hiz_depth_test_ambig_np_zpipe8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext512_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE8_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext513_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext513_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext513";
    metric_set->symbol_name = "Ext513";
    metric_set->hw_config_guid = "019ce184-cf6d-4457-aa35-e2b78d84b46f";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext513_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext513__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext513__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext513__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext513__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE9",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE9",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext513__hiz_depth_test_ambig_np_zpipe9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext513_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext514_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext514_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext514";
    metric_set->symbol_name = "Ext514";
    metric_set->hw_config_guid = "207d4da9-9398-48d6-8853-c1f6c2162ff8";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext514_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext514__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext514__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext514__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext514__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE10",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE10",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext514__hiz_depth_test_ambig_np_zpipe10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext514_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE10_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext515_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext515_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext515";
    metric_set->symbol_name = "Ext515";
    metric_set->hw_config_guid = "17dee536-5513-4419-9551-d4f5dc3bae81";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext515_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext515__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext515__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext515__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext515__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE11",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE11",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext515__hiz_depth_test_ambig_np_zpipe11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext515_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext516_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext516_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext516";
    metric_set->symbol_name = "Ext516";
    metric_set->hw_config_guid = "59061d86-24fc-4b93-baa8-c1955328ef28";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext516_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext516__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext516__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext516__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext516__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE12",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE12",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext516__hiz_depth_test_ambig_np_zpipe12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext516_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE12_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext517_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext517_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext517";
    metric_set->symbol_name = "Ext517";
    metric_set->hw_config_guid = "e626d1fe-ab2c-4728-a8d8-3be5dd359551";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext517_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext517__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext517__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext517__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext517__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE13",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE13",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext517__hiz_depth_test_ambig_np_zpipe13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext517_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext518_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext518_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext518";
    metric_set->symbol_name = "Ext518";
    metric_set->hw_config_guid = "10a8e59b-ad36-4def-a007-068dd782a72f";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext518_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext518__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext518__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext518__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext518__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE14",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE14",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext518__hiz_depth_test_ambig_np_zpipe14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext518_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE14_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext519_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext519_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext519";
    metric_set->symbol_name = "Ext519";
    metric_set->hw_config_guid = "e433e93a-0a7c-445c-957d-ed4ee1fc2f80";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext519_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext519__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext519__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext519__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext519__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE15",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE15",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext519__hiz_depth_test_ambig_np_zpipe15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext519_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext520_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext520_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext520";
    metric_set->symbol_name = "Ext520";
    metric_set->hw_config_guid = "19225cc5-e529-4943-a909-3cc9f147129c";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext520_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext520__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext520__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext520__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext520__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE0",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE0",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext520__hiz_depth_test_ambig_p_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext520_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext521_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext521_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext521";
    metric_set->symbol_name = "Ext521";
    metric_set->hw_config_guid = "b3add843-8502-41a9-a341-95f077741e80";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext521_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext521__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext521__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext521__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext521__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE1",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE1",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext521__hiz_depth_test_ambig_p_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext521_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext522_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext522_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext522";
    metric_set->symbol_name = "Ext522";
    metric_set->hw_config_guid = "24c9f0f5-1452-4c1b-9c37-5d5820da5723";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext522_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext522__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext522__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext522__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext522__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE2",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE2",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext522__hiz_depth_test_ambig_p_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext522_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext523_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext523_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext523";
    metric_set->symbol_name = "Ext523";
    metric_set->hw_config_guid = "8a3fad35-8f48-492c-a3c0-71d60b35cc9f";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext523_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext523__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext523__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext523__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext523__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE3",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE3",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext523__hiz_depth_test_ambig_p_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext523_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext524_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext524_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext524";
    metric_set->symbol_name = "Ext524";
    metric_set->hw_config_guid = "d78e5523-29e2-486c-bb2c-f850c02f0538";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext524_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext524__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext524__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext524__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext524__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE4",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE4",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext524__hiz_depth_test_ambig_p_zpipe4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext524_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext525_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext525_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext525";
    metric_set->symbol_name = "Ext525";
    metric_set->hw_config_guid = "f9a891a4-ce16-4f09-9d87-4b9462537ac8";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext525_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext525__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext525__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext525__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext525__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE5",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE5",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext525__hiz_depth_test_ambig_p_zpipe5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext525_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext526_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext526_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext526";
    metric_set->symbol_name = "Ext526";
    metric_set->hw_config_guid = "d09595c4-1c94-406c-94f5-9eaa44a56b63";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext526_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext526__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext526__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext526__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext526__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE6",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE6",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext526__hiz_depth_test_ambig_p_zpipe6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext526_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext527_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext527_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext527";
    metric_set->symbol_name = "Ext527";
    metric_set->hw_config_guid = "e1bc7df6-3d10-4f45-881c-398cd9e3e037";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext527_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext527__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext527__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext527__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext527__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE7",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE7",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext527__hiz_depth_test_ambig_p_zpipe7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext527_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext528_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext528_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext528";
    metric_set->symbol_name = "Ext528";
    metric_set->hw_config_guid = "2c30a5a4-7ceb-437d-83df-7d9a507060a8";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext528_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext528__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext528__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext528__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext528__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE8",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE8",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext528__hiz_depth_test_ambig_p_zpipe8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext528_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE8_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext529_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext529_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext529";
    metric_set->symbol_name = "Ext529";
    metric_set->hw_config_guid = "a87f8d10-83c9-400c-8e56-286b233c8570";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext529_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext529__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext529__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext529__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext529__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE9",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE9",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext529__hiz_depth_test_ambig_p_zpipe9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext529_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext530_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext530_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext530";
    metric_set->symbol_name = "Ext530";
    metric_set->hw_config_guid = "08cbf4ca-3da9-45a2-897c-1d817e4dfdc1";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext530_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext530__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext530__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext530__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext530__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE10",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE10",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext530__hiz_depth_test_ambig_p_zpipe10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext530_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE10_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext531_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext531_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext531";
    metric_set->symbol_name = "Ext531";
    metric_set->hw_config_guid = "8f8bfee8-6aa3-4862-bf42-c2b988bde49d";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext531_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext531__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext531__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext531__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext531__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE11",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE11",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext531__hiz_depth_test_ambig_p_zpipe11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext531_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext532_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext532_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext532";
    metric_set->symbol_name = "Ext532";
    metric_set->hw_config_guid = "4373c554-04d3-4e15-abf9-c6cbe7dcd17a";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext532_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext532__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext532__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext532__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext532__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE12",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE12",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext532__hiz_depth_test_ambig_p_zpipe12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext532_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE12_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext533_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext533_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext533";
    metric_set->symbol_name = "Ext533";
    metric_set->hw_config_guid = "b0a3dc10-4fd1-4f5a-92bc-14c53adbd1d9";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext533_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext533__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext533__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext533__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext533__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE13",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE13",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext533__hiz_depth_test_ambig_p_zpipe13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext533_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext534_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext534_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext534";
    metric_set->symbol_name = "Ext534";
    metric_set->hw_config_guid = "ddd0d949-f0ff-4a4f-a36d-a465d5ff0040";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext534_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext534__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext534__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext534__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext534__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE14",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE14",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext534__hiz_depth_test_ambig_p_zpipe14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext534_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE14_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext535_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext535_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext535";
    metric_set->symbol_name = "Ext535";
    metric_set->hw_config_guid = "79d88e98-4d0e-4aa7-bbe4-05039857e623";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext535_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext535__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext535__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext535__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext535__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE15",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE15",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext535__hiz_depth_test_ambig_p_zpipe15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext535_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext536_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext536_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext536";
    metric_set->symbol_name = "Ext536";
    metric_set->hw_config_guid = "8dcba9b0-7604-491f-811d-ff80bf4e2a6f";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext536_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext536__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext536__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext536__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext536__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE0",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE0",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext536__hiz_depth_test_fail_np_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext536_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext537_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext537_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext537";
    metric_set->symbol_name = "Ext537";
    metric_set->hw_config_guid = "c0619436-6cce-4029-95ac-f6761b5afdb1";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext537_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext537__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext537__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext537__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext537__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE1",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE1",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext537__hiz_depth_test_fail_np_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext537_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext538_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext538_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext538";
    metric_set->symbol_name = "Ext538";
    metric_set->hw_config_guid = "f24aba41-66e9-4a6e-8d78-a7ddd46d3d49";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext538_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext538__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext538__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext538__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext538__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE2",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE2",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext538__hiz_depth_test_fail_np_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext538_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext539_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext539_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext539";
    metric_set->symbol_name = "Ext539";
    metric_set->hw_config_guid = "0e79879a-074e-4ea7-b942-92cdc63855cd";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext539_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext539__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext539__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext539__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext539__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE3",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE3",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext539__hiz_depth_test_fail_np_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext539_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext540_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext540_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext540";
    metric_set->symbol_name = "Ext540";
    metric_set->hw_config_guid = "b3d690ba-d58e-4cc9-9faf-0b51c5ba958e";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext540_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext540__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext540__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext540__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext540__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE4",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE4",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext540__hiz_depth_test_fail_np_zpipe4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext540_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext541_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext541_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext541";
    metric_set->symbol_name = "Ext541";
    metric_set->hw_config_guid = "b0065120-ac7f-42fe-8ccf-88b32df3e4cf";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext541_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext541__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext541__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext541__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext541__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE5",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE5",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext541__hiz_depth_test_fail_np_zpipe5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext541_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext542_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext542_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext542";
    metric_set->symbol_name = "Ext542";
    metric_set->hw_config_guid = "ebbb6680-4931-4719-ac03-fba60301a688";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext542_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext542__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext542__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext542__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext542__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE6",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE6",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext542__hiz_depth_test_fail_np_zpipe6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext542_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext543_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext543_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext543";
    metric_set->symbol_name = "Ext543";
    metric_set->hw_config_guid = "672eba96-2c76-4056-a7fa-4e73a9d25627";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext543_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext543__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext543__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext543__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext543__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE7",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE7",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext543__hiz_depth_test_fail_np_zpipe7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext543_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext544_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext544_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext544";
    metric_set->symbol_name = "Ext544";
    metric_set->hw_config_guid = "de044605-80ac-43b0-b512-5f629a51ebec";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext544_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext544__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext544__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext544__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext544__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE8",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE8",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext544__hiz_depth_test_fail_np_zpipe8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext544_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE8_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext545_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext545_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext545";
    metric_set->symbol_name = "Ext545";
    metric_set->hw_config_guid = "720b8b78-896f-4056-88fa-9074d5127dd7";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext545_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext545__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext545__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext545__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext545__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE9",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE9",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext545__hiz_depth_test_fail_np_zpipe9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext545_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext546_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext546_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext546";
    metric_set->symbol_name = "Ext546";
    metric_set->hw_config_guid = "ee7f867c-816e-449f-a330-1b9622b33ae6";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext546_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext546__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext546__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext546__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext546__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE10",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE10",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext546__hiz_depth_test_fail_np_zpipe10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext546_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE10_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext547_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext547_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext547";
    metric_set->symbol_name = "Ext547";
    metric_set->hw_config_guid = "671d65a6-32c0-4983-9204-96e9eb7ff8fa";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext547_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext547__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext547__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext547__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext547__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE11",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE11",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext547__hiz_depth_test_fail_np_zpipe11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext547_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext548_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext548_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext548";
    metric_set->symbol_name = "Ext548";
    metric_set->hw_config_guid = "e23b228a-c5ac-4f11-8cb0-bf2353dfffde";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext548_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext548__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext548__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext548__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext548__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE12",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE12",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext548__hiz_depth_test_fail_np_zpipe12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext548_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE12_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext549_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext549_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext549";
    metric_set->symbol_name = "Ext549";
    metric_set->hw_config_guid = "3b521dba-b087-4c2a-bfbe-f043967881b6";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext549_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext549__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext549__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext549__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext549__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE13",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE13",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext549__hiz_depth_test_fail_np_zpipe13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext549_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext550_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext550_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext550";
    metric_set->symbol_name = "Ext550";
    metric_set->hw_config_guid = "b359e8f4-73ed-4da2-9471-2999a6d5473f";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext550_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext550__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext550__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext550__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext550__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE14",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE14",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext550__hiz_depth_test_fail_np_zpipe14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext550_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE14_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext551_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext551_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext551";
    metric_set->symbol_name = "Ext551";
    metric_set->hw_config_guid = "4bbd08e1-85c4-4de2-8ff6-9e5342bd0267";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext551_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext551__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext551__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext551__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext551__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE15",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE15",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext551__hiz_depth_test_fail_np_zpipe15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext551_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext552_HIZ_DEPTH_TEST_FAIL_P_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext552_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext552";
    metric_set->symbol_name = "Ext552";
    metric_set->hw_config_guid = "a0320c5d-dcd3-49ca-ba92-c19c068a69c8";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext552_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext552__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext552__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext552__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext552__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE0",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE0",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext552__hiz_depth_test_fail_p_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext552_HIZ_DEPTH_TEST_FAIL_P_ZPIPE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext553_HIZ_DEPTH_TEST_FAIL_P_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext553_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext553";
    metric_set->symbol_name = "Ext553";
    metric_set->hw_config_guid = "5a2dc84d-c4a8-4b4e-af0d-b14a04ffb79e";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext553_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext553__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext553__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext553__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext553__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE1",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE1",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext553__hiz_depth_test_fail_p_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext553_HIZ_DEPTH_TEST_FAIL_P_ZPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext554_HIZ_DEPTH_TEST_FAIL_P_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext554_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext554";
    metric_set->symbol_name = "Ext554";
    metric_set->hw_config_guid = "82287cfa-dddc-4b40-a0ba-feae2d42d826";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext554_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext554__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext554__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext554__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext554__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE2",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE2",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext554__hiz_depth_test_fail_p_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext554_HIZ_DEPTH_TEST_FAIL_P_ZPIPE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext555_HIZ_DEPTH_TEST_FAIL_P_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext555_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext555";
    metric_set->symbol_name = "Ext555";
    metric_set->hw_config_guid = "0a00e087-e302-497d-b832-d04cd048054f";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext555_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext555__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext555__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext555__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext555__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE3",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE3",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext555__hiz_depth_test_fail_p_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext555_HIZ_DEPTH_TEST_FAIL_P_ZPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext556_HIZ_DEPTH_TEST_FAIL_P_ZPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext556_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext556";
    metric_set->symbol_name = "Ext556";
    metric_set->hw_config_guid = "204f7d1a-1063-4e39-9c93-d3fe68a48e93";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext556_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext556__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext556__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext556__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext556__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE4",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE4",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext556__hiz_depth_test_fail_p_zpipe4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext556_HIZ_DEPTH_TEST_FAIL_P_ZPIPE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext557_HIZ_DEPTH_TEST_FAIL_P_ZPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext557_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext557";
    metric_set->symbol_name = "Ext557";
    metric_set->hw_config_guid = "67278ee9-56da-4f70-a405-85e27e8922ec";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext557_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext557__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext557__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext557__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext557__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE5",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE5",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext557__hiz_depth_test_fail_p_zpipe5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext557_HIZ_DEPTH_TEST_FAIL_P_ZPIPE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext558_HIZ_DEPTH_TEST_FAIL_P_ZPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext558_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext558";
    metric_set->symbol_name = "Ext558";
    metric_set->hw_config_guid = "b8723d61-732a-4c2f-8765-7e7aba97d348";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext558_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext558__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext558__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext558__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext558__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE6",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE6",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext558__hiz_depth_test_fail_p_zpipe6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext558_HIZ_DEPTH_TEST_FAIL_P_ZPIPE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext559_HIZ_DEPTH_TEST_FAIL_P_ZPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext559_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext559";
    metric_set->symbol_name = "Ext559";
    metric_set->hw_config_guid = "d8091fdb-460b-481e-b36f-4bc4c05c542f";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext559_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext559__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext559__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext559__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext559__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE7",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE7",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext559__hiz_depth_test_fail_p_zpipe7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext559_HIZ_DEPTH_TEST_FAIL_P_ZPIPE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext560_HIZ_DEPTH_TEST_FAIL_P_ZPIPE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext560_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext560";
    metric_set->symbol_name = "Ext560";
    metric_set->hw_config_guid = "a6c44052-b731-461d-8333-da99eeb8d5de";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext560_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext560__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext560__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext560__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext560__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE8",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE8",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext560__hiz_depth_test_fail_p_zpipe8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext560_HIZ_DEPTH_TEST_FAIL_P_ZPIPE8_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext561_HIZ_DEPTH_TEST_FAIL_P_ZPIPE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext561_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext561";
    metric_set->symbol_name = "Ext561";
    metric_set->hw_config_guid = "f2be6d7c-336b-46dc-8167-fb6e22106fe0";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext561_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext561__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext561__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext561__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext561__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE9",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE9",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext561__hiz_depth_test_fail_p_zpipe9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext561_HIZ_DEPTH_TEST_FAIL_P_ZPIPE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext562_HIZ_DEPTH_TEST_FAIL_P_ZPIPE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext562_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext562";
    metric_set->symbol_name = "Ext562";
    metric_set->hw_config_guid = "14cbc671-bc91-461f-b36c-11cac04a4368";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext562_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext562__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext562__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext562__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext562__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE10",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE10",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext562__hiz_depth_test_fail_p_zpipe10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext562_HIZ_DEPTH_TEST_FAIL_P_ZPIPE10_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext563_HIZ_DEPTH_TEST_FAIL_P_ZPIPE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext563_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext563";
    metric_set->symbol_name = "Ext563";
    metric_set->hw_config_guid = "e2422880-ab04-429a-9c59-83e7d129cc06";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext563_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext563__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext563__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext563__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext563__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE11",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE11",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext563__hiz_depth_test_fail_p_zpipe11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext563_HIZ_DEPTH_TEST_FAIL_P_ZPIPE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext564_HIZ_DEPTH_TEST_FAIL_P_ZPIPE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext564_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext564";
    metric_set->symbol_name = "Ext564";
    metric_set->hw_config_guid = "665be155-1110-4a9a-9281-7c3005cdb3ae";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext564_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext564__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext564__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext564__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext564__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE12",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE12",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext564__hiz_depth_test_fail_p_zpipe12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext564_HIZ_DEPTH_TEST_FAIL_P_ZPIPE12_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext565_HIZ_DEPTH_TEST_FAIL_P_ZPIPE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext565_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext565";
    metric_set->symbol_name = "Ext565";
    metric_set->hw_config_guid = "65bfe375-5cb3-4677-81fe-be5cde04a66f";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext565_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext565__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext565__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext565__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext565__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE13",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE13",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext565__hiz_depth_test_fail_p_zpipe13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext565_HIZ_DEPTH_TEST_FAIL_P_ZPIPE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext566_HIZ_DEPTH_TEST_FAIL_P_ZPIPE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext566_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext566";
    metric_set->symbol_name = "Ext566";
    metric_set->hw_config_guid = "a039f0c8-1641-47d8-8e59-6df51100da38";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext566_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext566__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext566__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext566__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext566__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE14",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE14",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext566__hiz_depth_test_fail_p_zpipe14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext566_HIZ_DEPTH_TEST_FAIL_P_ZPIPE14_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext567_HIZ_DEPTH_TEST_FAIL_P_ZPIPE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext567_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext567";
    metric_set->symbol_name = "Ext567";
    metric_set->hw_config_guid = "87c6ccd6-4f63-4f59-b3bc-54af974bf7c4";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext567_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext567__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext567__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext567__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext567__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE15",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE15",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext567__hiz_depth_test_fail_p_zpipe15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext567_HIZ_DEPTH_TEST_FAIL_P_ZPIPE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext568_HIZ_DEPTH_TEST_PASS_P_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext568_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext568";
    metric_set->symbol_name = "Ext568";
    metric_set->hw_config_guid = "fe0cbe07-d685-40d8-ba09-4a5a8fb45b99";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext568_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext568__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext568__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext568__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext568__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE0",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE0",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext568__hiz_depth_test_pass_p_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext568_HIZ_DEPTH_TEST_PASS_P_ZPIPE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext569_HIZ_DEPTH_TEST_PASS_P_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext569_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext569";
    metric_set->symbol_name = "Ext569";
    metric_set->hw_config_guid = "05da3d04-5cf9-4ecf-ac16-65cd2c06269c";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext569_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext569__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext569__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext569__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext569__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE1",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE1",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext569__hiz_depth_test_pass_p_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext569_HIZ_DEPTH_TEST_PASS_P_ZPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext570_HIZ_DEPTH_TEST_PASS_P_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext570_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext570";
    metric_set->symbol_name = "Ext570";
    metric_set->hw_config_guid = "e4576efb-543e-4a05-8ce4-9b8cf86d0d65";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext570_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext570__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext570__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext570__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext570__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE2",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE2",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext570__hiz_depth_test_pass_p_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext570_HIZ_DEPTH_TEST_PASS_P_ZPIPE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext571_HIZ_DEPTH_TEST_PASS_P_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext571_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext571";
    metric_set->symbol_name = "Ext571";
    metric_set->hw_config_guid = "07dc1b67-a2ad-45a5-941c-a4f294dc5426";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext571_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext571__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext571__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext571__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext571__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE3",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE3",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext571__hiz_depth_test_pass_p_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext571_HIZ_DEPTH_TEST_PASS_P_ZPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext572_HIZ_DEPTH_TEST_PASS_P_ZPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext572_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext572";
    metric_set->symbol_name = "Ext572";
    metric_set->hw_config_guid = "8c1361cf-3383-4b12-9865-d041c3c7ef80";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext572_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext572__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext572__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext572__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext572__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE4",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE4",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext572__hiz_depth_test_pass_p_zpipe4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext572_HIZ_DEPTH_TEST_PASS_P_ZPIPE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext573_HIZ_DEPTH_TEST_PASS_P_ZPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext573_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext573";
    metric_set->symbol_name = "Ext573";
    metric_set->hw_config_guid = "7b800152-513a-4d41-bcc9-f79e175f66c7";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext573_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext573__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext573__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext573__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext573__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE5",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE5",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext573__hiz_depth_test_pass_p_zpipe5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext573_HIZ_DEPTH_TEST_PASS_P_ZPIPE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext574_HIZ_DEPTH_TEST_PASS_P_ZPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext574_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext574";
    metric_set->symbol_name = "Ext574";
    metric_set->hw_config_guid = "089c60d7-18f0-447a-98c9-abaf82aba70b";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext574_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext574__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext574__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext574__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext574__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE6",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE6",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext574__hiz_depth_test_pass_p_zpipe6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext574_HIZ_DEPTH_TEST_PASS_P_ZPIPE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext575_HIZ_DEPTH_TEST_PASS_P_ZPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext575_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext575";
    metric_set->symbol_name = "Ext575";
    metric_set->hw_config_guid = "00101c81-f560-4e07-9ac8-7e276798feda";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext575_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext575__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext575__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext575__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext575__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE7",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE7",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext575__hiz_depth_test_pass_p_zpipe7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext575_HIZ_DEPTH_TEST_PASS_P_ZPIPE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext576_HIZ_DEPTH_TEST_PASS_P_ZPIPE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext576_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext576";
    metric_set->symbol_name = "Ext576";
    metric_set->hw_config_guid = "bf4a340e-056c-42cc-b1a6-66ace5b2e385";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext576_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext576__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext576__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext576__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext576__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE8",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE8",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext576__hiz_depth_test_pass_p_zpipe8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext576_HIZ_DEPTH_TEST_PASS_P_ZPIPE8_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext577_HIZ_DEPTH_TEST_PASS_P_ZPIPE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext577_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext577";
    metric_set->symbol_name = "Ext577";
    metric_set->hw_config_guid = "67b34202-9016-4aea-a1f0-5978b11c8636";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext577_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext577__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext577__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext577__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext577__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE9",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE9",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext577__hiz_depth_test_pass_p_zpipe9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext577_HIZ_DEPTH_TEST_PASS_P_ZPIPE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext578_HIZ_DEPTH_TEST_PASS_P_ZPIPE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext578_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext578";
    metric_set->symbol_name = "Ext578";
    metric_set->hw_config_guid = "fafe97c9-e42c-443c-aa3b-bd18dcc6903c";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext578_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext578__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext578__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext578__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext578__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE10",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE10",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext578__hiz_depth_test_pass_p_zpipe10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext578_HIZ_DEPTH_TEST_PASS_P_ZPIPE10_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext579_HIZ_DEPTH_TEST_PASS_P_ZPIPE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext579_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext579";
    metric_set->symbol_name = "Ext579";
    metric_set->hw_config_guid = "2d7f6b11-59c1-468a-bcef-131d2cb62a28";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext579_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext579__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext579__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext579__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext579__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE11",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE11",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext579__hiz_depth_test_pass_p_zpipe11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext579_HIZ_DEPTH_TEST_PASS_P_ZPIPE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext580_HIZ_DEPTH_TEST_PASS_P_ZPIPE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext580_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext580";
    metric_set->symbol_name = "Ext580";
    metric_set->hw_config_guid = "dee1277c-09d1-49f7-9035-039420ce8f55";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext580_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext580__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext580__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext580__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext580__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE12",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE12",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext580__hiz_depth_test_pass_p_zpipe12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext580_HIZ_DEPTH_TEST_PASS_P_ZPIPE12_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext581_HIZ_DEPTH_TEST_PASS_P_ZPIPE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext581_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext581";
    metric_set->symbol_name = "Ext581";
    metric_set->hw_config_guid = "97733423-59b0-4de6-9909-39bbe2e5f0b7";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext581_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext581__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext581__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext581__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext581__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE13",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE13",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext581__hiz_depth_test_pass_p_zpipe13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext581_HIZ_DEPTH_TEST_PASS_P_ZPIPE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext582_HIZ_DEPTH_TEST_PASS_P_ZPIPE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext582_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext582";
    metric_set->symbol_name = "Ext582";
    metric_set->hw_config_guid = "14f60fa0-1209-44d4-8618-c8dd54b8965d";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext582_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext582__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext582__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext582__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext582__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE14",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE14",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext582__hiz_depth_test_pass_p_zpipe14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext582_HIZ_DEPTH_TEST_PASS_P_ZPIPE14_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext583_HIZ_DEPTH_TEST_PASS_P_ZPIPE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext583_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext583";
    metric_set->symbol_name = "Ext583";
    metric_set->hw_config_guid = "6297276e-f7c6-4ac7-bc7b-4e1fb4c606a1";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext583_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext583__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext583__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext583__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext583__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE15",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE15",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext583__hiz_depth_test_pass_p_zpipe15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt3_ext583_HIZ_DEPTH_TEST_PASS_P_ZPIPE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext584_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext584";
    metric_set->symbol_name = "Ext584";
    metric_set->hw_config_guid = "812c0cf8-1163-454e-a6ff-36c6b3866b1f";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext584_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext584__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext584__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext584__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext584__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "IZ OUTPUT READY ZPIPE0",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE0",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext584__iz_output_ready_zpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE0_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE1",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE1",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext584__iz_output_ready_zpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE1_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE10",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE10",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext584__iz_output_ready_zpipe10__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE10_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE11",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE11",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext584__iz_output_ready_zpipe11__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE11_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE12",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE12",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext584__iz_output_ready_zpipe12__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE12_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE13",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE13",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext584__iz_output_ready_zpipe13__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE13_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE14",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE14",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext584__iz_output_ready_zpipe14__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE14_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE15",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE15",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext584__iz_output_ready_zpipe15__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE15_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE2",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE2",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext584__iz_output_ready_zpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE2_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE3",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE3",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext584__iz_output_ready_zpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE3_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE4",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE4",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext584__iz_output_ready_zpipe4__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE4_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE5",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE5",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext584__iz_output_ready_zpipe5__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE5_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE6",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE6",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext584__iz_output_ready_zpipe6__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE6_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE7",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE7",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext584__iz_output_ready_zpipe7__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE7_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE8",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE8",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext584__iz_output_ready_zpipe8__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE8_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE9",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE9",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext584__iz_output_ready_zpipe9__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext584_IZ_OUTPUT_READY_ZPIPE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext585_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext585";
    metric_set->symbol_name = "Ext585";
    metric_set->hw_config_guid = "2921d39b-5490-416a-bc1f-61d1782819fc";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext585_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext585__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext585__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext585__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext585__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE0",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE1",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE10",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE10",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe10__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE10_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE11",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE11",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe11__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE11_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE12",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE12",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe12__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE12_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE13",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE13",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe13__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE13_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE14",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE14",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe14__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE14_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE15",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE15",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe15__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE15_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE2",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE3",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE4",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE4",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe4__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE4_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE5",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE5",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe5__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE5_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE6",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE6",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe6__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE6_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE7",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE7",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe7__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE7_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE8",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE8",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe8__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE8_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE9",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE9",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe9__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext585_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext586_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext586";
    metric_set->symbol_name = "Ext586";
    metric_set->hw_config_guid = "340dd552-3f57-4f94-b8c5-2d7d96c4bbdf";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext586_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext586__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext586__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext586__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext586__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE0",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext586__iz_subspan_latency_fifofull_zpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE1",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext586__iz_subspan_latency_fifofull_zpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE10",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE10",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext586__iz_subspan_latency_fifofull_zpipe10__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE10_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE11",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE11",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext586__iz_subspan_latency_fifofull_zpipe11__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE11_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE12",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE12",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext586__iz_subspan_latency_fifofull_zpipe12__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE12_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE13",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE13",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext586__iz_subspan_latency_fifofull_zpipe13__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE13_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE14",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE14",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext586__iz_subspan_latency_fifofull_zpipe14__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE14_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE15",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE15",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext586__iz_subspan_latency_fifofull_zpipe15__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE15_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE2",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext586__iz_subspan_latency_fifofull_zpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE3",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext586__iz_subspan_latency_fifofull_zpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE4",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE4",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext586__iz_subspan_latency_fifofull_zpipe4__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE4_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE5",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE5",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext586__iz_subspan_latency_fifofull_zpipe5__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE5_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE6",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE6",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext586__iz_subspan_latency_fifofull_zpipe6__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE6_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE7",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE7",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext586__iz_subspan_latency_fifofull_zpipe7__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE7_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE8",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE8",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext586__iz_subspan_latency_fifofull_zpipe8__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE8_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE9",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE9",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext586__iz_subspan_latency_fifofull_zpipe9__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt3_ext586_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext587_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext587";
    metric_set->symbol_name = "Ext587";
    metric_set->hw_config_guid = "09a795b1-15ba-4f83-a662-18804b4eda96";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext587_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext587__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext587__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE0",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE0",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE0_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE1",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE1",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE1_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE10",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE10",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe10__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE10_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE11",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE11",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe11__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE11_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE12",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE12",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe12__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE12_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE13",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE13",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe13__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE13_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE14",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE14",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe14__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE14_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE15",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE15",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe15__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE15_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE2",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE2",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE2_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE3",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE3",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE3_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE4",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE4",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe4__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE4_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE5",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE5",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe5__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE5_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE6",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE6",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe6__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE6_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE7",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE7",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe7__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE7_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE8",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE8",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe8__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE8_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE9",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE9",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe9__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext587_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext587__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext587__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext588_PS_OUTPUT_AVAILABLE_CPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext588_PS_OUTPUT_AVAILABLE_CPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext588_PS_OUTPUT_AVAILABLE_CPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext588_PS_OUTPUT_AVAILABLE_CPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext588_PS_OUTPUT_AVAILABLE_CPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext588_PS_OUTPUT_AVAILABLE_CPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext588_PS_OUTPUT_AVAILABLE_CPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext588_PS_OUTPUT_AVAILABLE_CPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext588_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext588";
    metric_set->symbol_name = "Ext588";
    metric_set->hw_config_guid = "91a7be1d-3a4d-488f-999a-fd2b9564714e";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext588_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext588__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext588__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext588__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext588__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE0",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE0",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext588__ps_output_available_cpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext588_PS_OUTPUT_AVAILABLE_CPIPE0_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE1",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE1",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext588__ps_output_available_cpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext588_PS_OUTPUT_AVAILABLE_CPIPE1_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE2",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE2",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext588__ps_output_available_cpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext588_PS_OUTPUT_AVAILABLE_CPIPE2_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE3",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE3",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext588__ps_output_available_cpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext588_PS_OUTPUT_AVAILABLE_CPIPE3_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE4",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE4",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext588__ps_output_available_cpipe4__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext588_PS_OUTPUT_AVAILABLE_CPIPE4_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE5",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE5",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext588__ps_output_available_cpipe5__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext588_PS_OUTPUT_AVAILABLE_CPIPE5_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE6",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE6",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext588__ps_output_available_cpipe6__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext588_PS_OUTPUT_AVAILABLE_CPIPE6_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE7",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE7",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext588__ps_output_available_cpipe7__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext588_PS_OUTPUT_AVAILABLE_CPIPE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext589_PS_OUTPUT_AVAILABLE_CPIPE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext589_PS_OUTPUT_AVAILABLE_CPIPE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext589_PS_OUTPUT_AVAILABLE_CPIPE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext589_PS_OUTPUT_AVAILABLE_CPIPE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext589_PS_OUTPUT_AVAILABLE_CPIPE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext589_PS_OUTPUT_AVAILABLE_CPIPE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext589_PS_OUTPUT_AVAILABLE_CPIPE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext589_PS_OUTPUT_AVAILABLE_CPIPE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext589_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext589";
    metric_set->symbol_name = "Ext589";
    metric_set->hw_config_guid = "702f4f48-255f-4a82-94b9-2149053fa6c5";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext589_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext589__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext589__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext589__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext589__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE10",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE10",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext589__ps_output_available_cpipe10__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext589_PS_OUTPUT_AVAILABLE_CPIPE10_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE11",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE11",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext589__ps_output_available_cpipe11__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext589_PS_OUTPUT_AVAILABLE_CPIPE11_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE12",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE12",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext589__ps_output_available_cpipe12__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext589_PS_OUTPUT_AVAILABLE_CPIPE12_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE13",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE13",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext589__ps_output_available_cpipe13__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext589_PS_OUTPUT_AVAILABLE_CPIPE13_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE14",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE14",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext589__ps_output_available_cpipe14__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext589_PS_OUTPUT_AVAILABLE_CPIPE14_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE15",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE15",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext589__ps_output_available_cpipe15__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext589_PS_OUTPUT_AVAILABLE_CPIPE15_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE8",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE8",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext589__ps_output_available_cpipe8__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext589_PS_OUTPUT_AVAILABLE_CPIPE8_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE9",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE9",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext589__ps_output_available_cpipe9__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext589_PS_OUTPUT_AVAILABLE_CPIPE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext590_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext590";
    metric_set->symbol_name = "Ext590";
    metric_set->hw_config_guid = "21788d5b-810d-4982-b915-0048962b86e7";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext590_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext590__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext590__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext590__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext590__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE0",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE0",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext590__pixel_post_process_output_ready_cpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE0_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE1",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE1",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext590__pixel_post_process_output_ready_cpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE1_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE10",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE10",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext590__pixel_post_process_output_ready_cpipe10__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE10_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE11",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE11",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext590__pixel_post_process_output_ready_cpipe11__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE11_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE12",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE12",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext590__pixel_post_process_output_ready_cpipe12__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE12_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE13",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE13",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext590__pixel_post_process_output_ready_cpipe13__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE13_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE14",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE14",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext590__pixel_post_process_output_ready_cpipe14__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE14_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE15",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE15",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext590__pixel_post_process_output_ready_cpipe15__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE15_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE2",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE2",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext590__pixel_post_process_output_ready_cpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE2_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE3",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE3",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext590__pixel_post_process_output_ready_cpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE3_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE4",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE4",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext590__pixel_post_process_output_ready_cpipe4__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE4_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE5",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE5",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext590__pixel_post_process_output_ready_cpipe5__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE5_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE6",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE6",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext590__pixel_post_process_output_ready_cpipe6__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE6_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE7",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE7",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext590__pixel_post_process_output_ready_cpipe7__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE7_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE8",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE8",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext590__pixel_post_process_output_ready_cpipe8__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE8_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE9",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE9",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext590__pixel_post_process_output_ready_cpipe9__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext590_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext591_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext591_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext591_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext591";
    metric_set->symbol_name = "Ext591";
    metric_set->hw_config_guid = "d3416b56-6640-4b2a-b81d-295287c90a22";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext591_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext591__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext591__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext591__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext591__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE0",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE0",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext591__pixel_post_process_input_available_cpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext591_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE0_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE1",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE1",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext591__pixel_post_process_input_available_cpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext591_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext592_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext592_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext592_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext592";
    metric_set->symbol_name = "Ext592";
    metric_set->hw_config_guid = "0d6485c1-7bfb-4f49-98a4-6247c0597e31";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext592_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext592__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext592__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext592__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext592__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE2",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE2",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext592__pixel_post_process_input_available_cpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext592_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE2_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE3",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE3",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext592__pixel_post_process_input_available_cpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext592_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext593_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext593_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext593_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext593";
    metric_set->symbol_name = "Ext593";
    metric_set->hw_config_guid = "7b4adfcb-b4fe-4e2b-803c-b9cfa2b2cd17";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext593_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext593__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext593__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext593__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext593__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE4",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE4",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext593__pixel_post_process_input_available_cpipe4__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext593_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE4_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE5",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE5",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext593__pixel_post_process_input_available_cpipe5__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext593_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext594_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext594_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext594_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext594";
    metric_set->symbol_name = "Ext594";
    metric_set->hw_config_guid = "35040db3-1214-41dc-b856-f26d3b553905";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext594_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext594__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext594__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext594__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext594__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE6",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE6",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext594__pixel_post_process_input_available_cpipe6__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext594_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE6_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE7",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE7",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext594__pixel_post_process_input_available_cpipe7__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext594_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext595_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext595_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext595_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext595";
    metric_set->symbol_name = "Ext595";
    metric_set->hw_config_guid = "3279a141-6b9b-4f1b-a38d-2bd7386c46dc";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext595_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext595__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext595__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext595__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext595__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE8",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE8",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext595__pixel_post_process_input_available_cpipe8__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext595_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE8_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE9",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE9",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext595__pixel_post_process_input_available_cpipe9__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext595_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext596_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext596_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext596_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext596";
    metric_set->symbol_name = "Ext596";
    metric_set->hw_config_guid = "2a08b276-0fb8-4c89-bbed-57892a7c9542";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext596_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext596__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext596__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext596__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext596__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE10",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE10",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext596__pixel_post_process_input_available_cpipe10__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext596_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE10_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE11",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE11",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext596__pixel_post_process_input_available_cpipe11__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext596_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext597_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext597_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext597_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext597";
    metric_set->symbol_name = "Ext597";
    metric_set->hw_config_guid = "2628efb2-4b7c-4d88-8a03-620235fd1014";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext597_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext597__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext597__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext597__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext597__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE12",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE12",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext597__pixel_post_process_input_available_cpipe12__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext597_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE12_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE13",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE13",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext597__pixel_post_process_input_available_cpipe13__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext597_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext598_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext598_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext598_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext598";
    metric_set->symbol_name = "Ext598";
    metric_set->hw_config_guid = "b45e047d-88d6-4234-89f1-2b3763e2ec7c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext598_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext598__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext598__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext598__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext598__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE14",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE14",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext598__pixel_post_process_input_available_cpipe14__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext598_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE14_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE15",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE15",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext598__pixel_post_process_input_available_cpipe15__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext598_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext599_AMFS_CACHE_HIT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext599_AMFS_CACHE_MISS_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext599_AMFS_STALL_ALL_INPUT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext599_AMFS_STALL_ANY_INPUT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext599_RENDER_CACHE_HIT_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext599_RENDER_CACHE_INPUT_AVAILABLE_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext599_RENDER_CACHE_OUTPUT_READY_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext599_RENDER_CACHE_READ_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext599_RENDER_CACHE_WRITE_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext599_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext599";
    metric_set->symbol_name = "Ext599";
    metric_set->hw_config_guid = "8f41dd6c-778f-4060-b8ab-13e66e76d4ff";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext599_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS CACHE HIT SLICE0",
                .symbol_name = "AMFS_CACHE_HIT_SLICE0",
                .desc = "Number of hits in the AMFS cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext599__amfs_cache_hit_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext599_AMFS_CACHE_HIT_SLICE0_availability,
            },

            {
                .name = "AMFS CACHE MISS SLICE0",
                .symbol_name = "AMFS_CACHE_MISS_SLICE0",
                .desc = "Number of cache misses in AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext599__amfs_cache_miss_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext599_AMFS_CACHE_MISS_SLICE0_availability,
            },

            {
                .name = "AMFS STALL ALL INPUT SLICE0",
                .symbol_name = "AMFS_STALL_ALL_INPUT_SLICE0",
                .desc = "Percentage of time in which AMFS stalls at both of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext599__amfs_stall_all_input_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt3_ext599_AMFS_STALL_ALL_INPUT_SLICE0_availability,
            },

            {
                .name = "AMFS STALL ANY INPUT SLICE0",
                .symbol_name = "AMFS_STALL_ANY_INPUT_SLICE0",
                .desc = "Percentage of time in which AMFS stalls at any of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext599__amfs_stall_any_input_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt3_ext599_AMFS_STALL_ANY_INPUT_SLICE0_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext599__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext599__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext599__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext599__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RENDER CACHE HIT L3NODE0",
                .symbol_name = "RENDER_CACHE_HIT_L3NODE0",
                .desc = "Number of Render Cache hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext599__render_cache_hit_l3_node0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext599_RENDER_CACHE_HIT_L3NODE0_availability,
            },

            {
                .name = "RENDER_CACHE_INPUT_AVAILABLE _L3NODE0",
                .symbol_name = "RENDER_CACHE_INPUT_AVAILABLE_L3NODE0",
                .desc = "Percentage of time when render cache input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext599__render_cache_input_available_l3_node0__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext599_RENDER_CACHE_INPUT_AVAILABLE_L3NODE0_availability,
            },

            {
                .name = "RENDER_CACHE_OUTPUT_READY _L3NODE0",
                .symbol_name = "RENDER_CACHE_OUTPUT_READY_L3NODE0",
                .desc = "Percentage of time when render cache output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext599__render_cache_output_ready_l3_node0__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext599_RENDER_CACHE_OUTPUT_READY_L3NODE0_availability,
            },

            {
                .name = "RENDER CACHE READ L3NODE0",
                .symbol_name = "RENDER_CACHE_READ_L3NODE0",
                .desc = "Number of Render Cache reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext599__render_cache_read_l3_node0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext599_RENDER_CACHE_READ_L3NODE0_availability,
            },

            {
                .name = "RENDER CACHE WRITE L3NODE0",
                .symbol_name = "RENDER_CACHE_WRITE_L3NODE0",
                .desc = "Number of Render Cache writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext599__render_cache_write_l3_node0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext599_RENDER_CACHE_WRITE_L3NODE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt3_ext600_AMFS_CACHE_HIT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext600_AMFS_CACHE_MISS_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext600_AMFS_STALL_ALL_INPUT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext600_AMFS_STALL_ANY_INPUT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext600_RENDER_CACHE_HIT_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext600_RENDER_CACHE_INPUT_AVAILABLE_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext600_RENDER_CACHE_OUTPUT_READY_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext600_RENDER_CACHE_READ_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext600_RENDER_CACHE_WRITE_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext600_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext600";
    metric_set->symbol_name = "Ext600";
    metric_set->hw_config_guid = "c0cc46d1-0475-478d-ad6f-cbef207c1ccb";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext600_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS CACHE HIT SLICE1",
                .symbol_name = "AMFS_CACHE_HIT_SLICE1",
                .desc = "Number of hits in the AMFS cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext600__amfs_cache_hit_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext600_AMFS_CACHE_HIT_SLICE1_availability,
            },

            {
                .name = "AMFS CACHE MISS SLICE1",
                .symbol_name = "AMFS_CACHE_MISS_SLICE1",
                .desc = "Number of cache misses in AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext600__amfs_cache_miss_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext600_AMFS_CACHE_MISS_SLICE1_availability,
            },

            {
                .name = "AMFS STALL ALL INPUT SLICE1",
                .symbol_name = "AMFS_STALL_ALL_INPUT_SLICE1",
                .desc = "Percentage of time in which AMFS stalls at both of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext600__amfs_stall_all_input_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt3_ext600_AMFS_STALL_ALL_INPUT_SLICE1_availability,
            },

            {
                .name = "AMFS STALL ANY INPUT SLICE1",
                .symbol_name = "AMFS_STALL_ANY_INPUT_SLICE1",
                .desc = "Percentage of time in which AMFS stalls at any of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext600__amfs_stall_any_input_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt3_ext600_AMFS_STALL_ANY_INPUT_SLICE1_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext600__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext600__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext600__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext600__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RENDER CACHE HIT L3NODE1",
                .symbol_name = "RENDER_CACHE_HIT_L3NODE1",
                .desc = "Number of Render Cache hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext600__render_cache_hit_l3_node1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext600_RENDER_CACHE_HIT_L3NODE1_availability,
            },

            {
                .name = "RENDER_CACHE_INPUT_AVAILABLE _L3NODE1",
                .symbol_name = "RENDER_CACHE_INPUT_AVAILABLE_L3NODE1",
                .desc = "Percentage of time when render cache input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext600__render_cache_input_available_l3_node1__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext600_RENDER_CACHE_INPUT_AVAILABLE_L3NODE1_availability,
            },

            {
                .name = "RENDER_CACHE_OUTPUT_READY _L3NODE1",
                .symbol_name = "RENDER_CACHE_OUTPUT_READY_L3NODE1",
                .desc = "Percentage of time when render cache output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext600__render_cache_output_ready_l3_node1__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext600_RENDER_CACHE_OUTPUT_READY_L3NODE1_availability,
            },

            {
                .name = "RENDER CACHE READ L3NODE1",
                .symbol_name = "RENDER_CACHE_READ_L3NODE1",
                .desc = "Number of Render Cache reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext600__render_cache_read_l3_node1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext600_RENDER_CACHE_READ_L3NODE1_availability,
            },

            {
                .name = "RENDER CACHE WRITE L3NODE1",
                .symbol_name = "RENDER_CACHE_WRITE_L3NODE1",
                .desc = "Number of Render Cache writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext600__render_cache_write_l3_node1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext600_RENDER_CACHE_WRITE_L3NODE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt3_ext601_AMFS_CACHE_HIT_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext601_AMFS_CACHE_MISS_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext601_AMFS_STALL_ALL_INPUT_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext601_AMFS_STALL_ANY_INPUT_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext601_RENDER_CACHE_HIT_L3NODE2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext601_RENDER_CACHE_INPUT_AVAILABLE_L3NODE2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext601_RENDER_CACHE_OUTPUT_READY_L3NODE2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext601_RENDER_CACHE_READ_L3NODE2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext601_RENDER_CACHE_WRITE_L3NODE2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext601_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext601";
    metric_set->symbol_name = "Ext601";
    metric_set->hw_config_guid = "11c7bdc4-a63a-46cb-a967-33ded50ecd42";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext601_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS CACHE HIT SLICE2",
                .symbol_name = "AMFS_CACHE_HIT_SLICE2",
                .desc = "Number of hits in the AMFS cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext601__amfs_cache_hit_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext601_AMFS_CACHE_HIT_SLICE2_availability,
            },

            {
                .name = "AMFS CACHE MISS SLICE2",
                .symbol_name = "AMFS_CACHE_MISS_SLICE2",
                .desc = "Number of cache misses in AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext601__amfs_cache_miss_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext601_AMFS_CACHE_MISS_SLICE2_availability,
            },

            {
                .name = "AMFS STALL ALL INPUT SLICE2",
                .symbol_name = "AMFS_STALL_ALL_INPUT_SLICE2",
                .desc = "Percentage of time in which AMFS stalls at both of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext601__amfs_stall_all_input_slice2__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt3_ext601_AMFS_STALL_ALL_INPUT_SLICE2_availability,
            },

            {
                .name = "AMFS STALL ANY INPUT SLICE2",
                .symbol_name = "AMFS_STALL_ANY_INPUT_SLICE2",
                .desc = "Percentage of time in which AMFS stalls at any of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext601__amfs_stall_any_input_slice2__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt3_ext601_AMFS_STALL_ANY_INPUT_SLICE2_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext601__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext601__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext601__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext601__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RENDER CACHE HIT L3NODE2",
                .symbol_name = "RENDER_CACHE_HIT_L3NODE2",
                .desc = "Number of Render Cache hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext601__render_cache_hit_l3_node2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext601_RENDER_CACHE_HIT_L3NODE2_availability,
            },

            {
                .name = "RENDER_CACHE_INPUT_AVAILABLE _L3NODE2",
                .symbol_name = "RENDER_CACHE_INPUT_AVAILABLE_L3NODE2",
                .desc = "Percentage of time when render cache input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext601__render_cache_input_available_l3_node2__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext601_RENDER_CACHE_INPUT_AVAILABLE_L3NODE2_availability,
            },

            {
                .name = "RENDER_CACHE_OUTPUT_READY _L3NODE2",
                .symbol_name = "RENDER_CACHE_OUTPUT_READY_L3NODE2",
                .desc = "Percentage of time when render cache output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext601__render_cache_output_ready_l3_node2__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext601_RENDER_CACHE_OUTPUT_READY_L3NODE2_availability,
            },

            {
                .name = "RENDER CACHE READ L3NODE2",
                .symbol_name = "RENDER_CACHE_READ_L3NODE2",
                .desc = "Number of Render Cache reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext601__render_cache_read_l3_node2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext601_RENDER_CACHE_READ_L3NODE2_availability,
            },

            {
                .name = "RENDER CACHE WRITE L3NODE2",
                .symbol_name = "RENDER_CACHE_WRITE_L3NODE2",
                .desc = "Number of Render Cache writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext601__render_cache_write_l3_node2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext601_RENDER_CACHE_WRITE_L3NODE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt3_ext602_AMFS_CACHE_HIT_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext602_AMFS_CACHE_MISS_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext602_AMFS_STALL_ALL_INPUT_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext602_AMFS_STALL_ANY_INPUT_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext602_RENDER_CACHE_HIT_L3NODE3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext602_RENDER_CACHE_INPUT_AVAILABLE_L3NODE3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext602_RENDER_CACHE_OUTPUT_READY_L3NODE3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext602_RENDER_CACHE_READ_L3NODE3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext602_RENDER_CACHE_WRITE_L3NODE3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext602_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext602";
    metric_set->symbol_name = "Ext602";
    metric_set->hw_config_guid = "d7899495-d4d2-4235-8670-dd0ee48cc477";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext602_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS CACHE HIT SLICE3",
                .symbol_name = "AMFS_CACHE_HIT_SLICE3",
                .desc = "Number of hits in the AMFS cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext602__amfs_cache_hit_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext602_AMFS_CACHE_HIT_SLICE3_availability,
            },

            {
                .name = "AMFS CACHE MISS SLICE3",
                .symbol_name = "AMFS_CACHE_MISS_SLICE3",
                .desc = "Number of cache misses in AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext602__amfs_cache_miss_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext602_AMFS_CACHE_MISS_SLICE3_availability,
            },

            {
                .name = "AMFS STALL ALL INPUT SLICE3",
                .symbol_name = "AMFS_STALL_ALL_INPUT_SLICE3",
                .desc = "Percentage of time in which AMFS stalls at both of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext602__amfs_stall_all_input_slice3__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt3_ext602_AMFS_STALL_ALL_INPUT_SLICE3_availability,
            },

            {
                .name = "AMFS STALL ANY INPUT SLICE3",
                .symbol_name = "AMFS_STALL_ANY_INPUT_SLICE3",
                .desc = "Percentage of time in which AMFS stalls at any of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext602__amfs_stall_any_input_slice3__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt3_ext602_AMFS_STALL_ANY_INPUT_SLICE3_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext602__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext602__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext602__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext602__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RENDER CACHE HIT L3NODE3",
                .symbol_name = "RENDER_CACHE_HIT_L3NODE3",
                .desc = "Number of Render Cache hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext602__render_cache_hit_l3_node3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext602_RENDER_CACHE_HIT_L3NODE3_availability,
            },

            {
                .name = "RENDER_CACHE_INPUT_AVAILABLE _L3NODE3",
                .symbol_name = "RENDER_CACHE_INPUT_AVAILABLE_L3NODE3",
                .desc = "Percentage of time when render cache input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext602__render_cache_input_available_l3_node3__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext602_RENDER_CACHE_INPUT_AVAILABLE_L3NODE3_availability,
            },

            {
                .name = "RENDER_CACHE_OUTPUT_READY _L3NODE3",
                .symbol_name = "RENDER_CACHE_OUTPUT_READY_L3NODE3",
                .desc = "Percentage of time when render cache output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext602__render_cache_output_ready_l3_node3__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext602_RENDER_CACHE_OUTPUT_READY_L3NODE3_availability,
            },

            {
                .name = "RENDER CACHE READ L3NODE3",
                .symbol_name = "RENDER_CACHE_READ_L3NODE3",
                .desc = "Number of Render Cache reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext602__render_cache_read_l3_node3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext602_RENDER_CACHE_READ_L3NODE3_availability,
            },

            {
                .name = "RENDER CACHE WRITE L3NODE3",
                .symbol_name = "RENDER_CACHE_WRITE_L3NODE3",
                .desc = "Number of Render Cache writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext602__render_cache_write_l3_node3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext602_RENDER_CACHE_WRITE_L3NODE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt3_ext603_AMFS_CACHE_HIT_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext603_AMFS_CACHE_MISS_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext603_AMFS_STALL_ALL_INPUT_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext603_AMFS_STALL_ANY_INPUT_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext603_RENDER_CACHE_HIT_L3NODE4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext603_RENDER_CACHE_INPUT_AVAILABLE_L3NODE4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext603_RENDER_CACHE_OUTPUT_READY_L3NODE4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext603_RENDER_CACHE_READ_L3NODE4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext603_RENDER_CACHE_WRITE_L3NODE4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext603_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext603";
    metric_set->symbol_name = "Ext603";
    metric_set->hw_config_guid = "b58e27fd-3505-4a89-a83f-0767b2f949fd";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext603_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS CACHE HIT SLICE4",
                .symbol_name = "AMFS_CACHE_HIT_SLICE4",
                .desc = "Number of hits in the AMFS cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext603__amfs_cache_hit_slice4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext603_AMFS_CACHE_HIT_SLICE4_availability,
            },

            {
                .name = "AMFS CACHE MISS SLICE4",
                .symbol_name = "AMFS_CACHE_MISS_SLICE4",
                .desc = "Number of cache misses in AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext603__amfs_cache_miss_slice4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext603_AMFS_CACHE_MISS_SLICE4_availability,
            },

            {
                .name = "AMFS STALL ALL INPUT SLICE4",
                .symbol_name = "AMFS_STALL_ALL_INPUT_SLICE4",
                .desc = "Percentage of time in which AMFS stalls at both of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext603__amfs_stall_all_input_slice4__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt3_ext603_AMFS_STALL_ALL_INPUT_SLICE4_availability,
            },

            {
                .name = "AMFS STALL ANY INPUT SLICE4",
                .symbol_name = "AMFS_STALL_ANY_INPUT_SLICE4",
                .desc = "Percentage of time in which AMFS stalls at any of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext603__amfs_stall_any_input_slice4__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt3_ext603_AMFS_STALL_ANY_INPUT_SLICE4_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext603__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext603__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext603__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext603__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RENDER CACHE HIT L3NODE4",
                .symbol_name = "RENDER_CACHE_HIT_L3NODE4",
                .desc = "Number of Render Cache hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext603__render_cache_hit_l3_node4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext603_RENDER_CACHE_HIT_L3NODE4_availability,
            },

            {
                .name = "RENDER_CACHE_INPUT_AVAILABLE _L3NODE4",
                .symbol_name = "RENDER_CACHE_INPUT_AVAILABLE_L3NODE4",
                .desc = "Percentage of time when render cache input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext603__render_cache_input_available_l3_node4__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext603_RENDER_CACHE_INPUT_AVAILABLE_L3NODE4_availability,
            },

            {
                .name = "RENDER_CACHE_OUTPUT_READY _L3NODE4",
                .symbol_name = "RENDER_CACHE_OUTPUT_READY_L3NODE4",
                .desc = "Percentage of time when render cache output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext603__render_cache_output_ready_l3_node4__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext603_RENDER_CACHE_OUTPUT_READY_L3NODE4_availability,
            },

            {
                .name = "RENDER CACHE READ L3NODE4",
                .symbol_name = "RENDER_CACHE_READ_L3NODE4",
                .desc = "Number of Render Cache reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext603__render_cache_read_l3_node4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext603_RENDER_CACHE_READ_L3NODE4_availability,
            },

            {
                .name = "RENDER CACHE WRITE L3NODE4",
                .symbol_name = "RENDER_CACHE_WRITE_L3NODE4",
                .desc = "Number of Render Cache writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext603__render_cache_write_l3_node4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext603_RENDER_CACHE_WRITE_L3NODE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt3_ext604_AMFS_CACHE_HIT_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext604_AMFS_CACHE_MISS_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext604_AMFS_STALL_ALL_INPUT_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext604_AMFS_STALL_ANY_INPUT_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext604_RENDER_CACHE_HIT_L3NODE5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext604_RENDER_CACHE_INPUT_AVAILABLE_L3NODE5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext604_RENDER_CACHE_OUTPUT_READY_L3NODE5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext604_RENDER_CACHE_READ_L3NODE5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext604_RENDER_CACHE_WRITE_L3NODE5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext604_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext604";
    metric_set->symbol_name = "Ext604";
    metric_set->hw_config_guid = "abf8d7f4-395b-4c43-aaf7-e327cb5a3dc6";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext604_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS CACHE HIT SLICE5",
                .symbol_name = "AMFS_CACHE_HIT_SLICE5",
                .desc = "Number of hits in the AMFS cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext604__amfs_cache_hit_slice5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext604_AMFS_CACHE_HIT_SLICE5_availability,
            },

            {
                .name = "AMFS CACHE MISS SLICE5",
                .symbol_name = "AMFS_CACHE_MISS_SLICE5",
                .desc = "Number of cache misses in AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext604__amfs_cache_miss_slice5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext604_AMFS_CACHE_MISS_SLICE5_availability,
            },

            {
                .name = "AMFS STALL ALL INPUT SLICE5",
                .symbol_name = "AMFS_STALL_ALL_INPUT_SLICE5",
                .desc = "Percentage of time in which AMFS stalls at both of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext604__amfs_stall_all_input_slice5__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt3_ext604_AMFS_STALL_ALL_INPUT_SLICE5_availability,
            },

            {
                .name = "AMFS STALL ANY INPUT SLICE5",
                .symbol_name = "AMFS_STALL_ANY_INPUT_SLICE5",
                .desc = "Percentage of time in which AMFS stalls at any of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext604__amfs_stall_any_input_slice5__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt3_ext604_AMFS_STALL_ANY_INPUT_SLICE5_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext604__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext604__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext604__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext604__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RENDER CACHE HIT L3NODE5",
                .symbol_name = "RENDER_CACHE_HIT_L3NODE5",
                .desc = "Number of Render Cache hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext604__render_cache_hit_l3_node5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext604_RENDER_CACHE_HIT_L3NODE5_availability,
            },

            {
                .name = "RENDER_CACHE_INPUT_AVAILABLE _L3NODE5",
                .symbol_name = "RENDER_CACHE_INPUT_AVAILABLE_L3NODE5",
                .desc = "Percentage of time when render cache input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext604__render_cache_input_available_l3_node5__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext604_RENDER_CACHE_INPUT_AVAILABLE_L3NODE5_availability,
            },

            {
                .name = "RENDER_CACHE_OUTPUT_READY _L3NODE5",
                .symbol_name = "RENDER_CACHE_OUTPUT_READY_L3NODE5",
                .desc = "Percentage of time when render cache output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext604__render_cache_output_ready_l3_node5__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext604_RENDER_CACHE_OUTPUT_READY_L3NODE5_availability,
            },

            {
                .name = "RENDER CACHE READ L3NODE5",
                .symbol_name = "RENDER_CACHE_READ_L3NODE5",
                .desc = "Number of Render Cache reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext604__render_cache_read_l3_node5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext604_RENDER_CACHE_READ_L3NODE5_availability,
            },

            {
                .name = "RENDER CACHE WRITE L3NODE5",
                .symbol_name = "RENDER_CACHE_WRITE_L3NODE5",
                .desc = "Number of Render Cache writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext604__render_cache_write_l3_node5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext604_RENDER_CACHE_WRITE_L3NODE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt3_ext605_AMFS_CACHE_HIT_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext605_AMFS_CACHE_MISS_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext605_AMFS_STALL_ALL_INPUT_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext605_AMFS_STALL_ANY_INPUT_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext605_RENDER_CACHE_HIT_L3NODE6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext605_RENDER_CACHE_INPUT_AVAILABLE_L3NODE6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext605_RENDER_CACHE_OUTPUT_READY_L3NODE6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext605_RENDER_CACHE_READ_L3NODE6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext605_RENDER_CACHE_WRITE_L3NODE6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext605_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext605";
    metric_set->symbol_name = "Ext605";
    metric_set->hw_config_guid = "44fa1922-0aca-4a6b-8adc-78e764982068";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext605_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS CACHE HIT SLICE6",
                .symbol_name = "AMFS_CACHE_HIT_SLICE6",
                .desc = "Number of hits in the AMFS cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext605__amfs_cache_hit_slice6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext605_AMFS_CACHE_HIT_SLICE6_availability,
            },

            {
                .name = "AMFS CACHE MISS SLICE6",
                .symbol_name = "AMFS_CACHE_MISS_SLICE6",
                .desc = "Number of cache misses in AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext605__amfs_cache_miss_slice6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext605_AMFS_CACHE_MISS_SLICE6_availability,
            },

            {
                .name = "AMFS STALL ALL INPUT SLICE6",
                .symbol_name = "AMFS_STALL_ALL_INPUT_SLICE6",
                .desc = "Percentage of time in which AMFS stalls at both of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext605__amfs_stall_all_input_slice6__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt3_ext605_AMFS_STALL_ALL_INPUT_SLICE6_availability,
            },

            {
                .name = "AMFS STALL ANY INPUT SLICE6",
                .symbol_name = "AMFS_STALL_ANY_INPUT_SLICE6",
                .desc = "Percentage of time in which AMFS stalls at any of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext605__amfs_stall_any_input_slice6__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt3_ext605_AMFS_STALL_ANY_INPUT_SLICE6_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext605__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext605__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext605__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext605__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RENDER CACHE HIT L3NODE6",
                .symbol_name = "RENDER_CACHE_HIT_L3NODE6",
                .desc = "Number of Render Cache hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext605__render_cache_hit_l3_node6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext605_RENDER_CACHE_HIT_L3NODE6_availability,
            },

            {
                .name = "RENDER_CACHE_INPUT_AVAILABLE _L3NODE6",
                .symbol_name = "RENDER_CACHE_INPUT_AVAILABLE_L3NODE6",
                .desc = "Percentage of time when render cache input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext605__render_cache_input_available_l3_node6__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext605_RENDER_CACHE_INPUT_AVAILABLE_L3NODE6_availability,
            },

            {
                .name = "RENDER_CACHE_OUTPUT_READY _L3NODE6",
                .symbol_name = "RENDER_CACHE_OUTPUT_READY_L3NODE6",
                .desc = "Percentage of time when render cache output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext605__render_cache_output_ready_l3_node6__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext605_RENDER_CACHE_OUTPUT_READY_L3NODE6_availability,
            },

            {
                .name = "RENDER CACHE READ L3NODE6",
                .symbol_name = "RENDER_CACHE_READ_L3NODE6",
                .desc = "Number of Render Cache reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext605__render_cache_read_l3_node6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext605_RENDER_CACHE_READ_L3NODE6_availability,
            },

            {
                .name = "RENDER CACHE WRITE L3NODE6",
                .symbol_name = "RENDER_CACHE_WRITE_L3NODE6",
                .desc = "Number of Render Cache writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext605__render_cache_write_l3_node6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext605_RENDER_CACHE_WRITE_L3NODE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt3_ext606_AMFS_CACHE_HIT_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext606_AMFS_CACHE_MISS_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext606_AMFS_STALL_ALL_INPUT_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext606_AMFS_STALL_ANY_INPUT_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext606_RENDER_CACHE_HIT_L3NODE7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext606_RENDER_CACHE_INPUT_AVAILABLE_L3NODE7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext606_RENDER_CACHE_OUTPUT_READY_L3NODE7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext606_RENDER_CACHE_READ_L3NODE7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext606_RENDER_CACHE_WRITE_L3NODE7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext606_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext606";
    metric_set->symbol_name = "Ext606";
    metric_set->hw_config_guid = "1d5881b6-188f-4dfd-9a06-08df383da728";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext606_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS CACHE HIT SLICE7",
                .symbol_name = "AMFS_CACHE_HIT_SLICE7",
                .desc = "Number of hits in the AMFS cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext606__amfs_cache_hit_slice7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext606_AMFS_CACHE_HIT_SLICE7_availability,
            },

            {
                .name = "AMFS CACHE MISS SLICE7",
                .symbol_name = "AMFS_CACHE_MISS_SLICE7",
                .desc = "Number of cache misses in AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext606__amfs_cache_miss_slice7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext606_AMFS_CACHE_MISS_SLICE7_availability,
            },

            {
                .name = "AMFS STALL ALL INPUT SLICE7",
                .symbol_name = "AMFS_STALL_ALL_INPUT_SLICE7",
                .desc = "Percentage of time in which AMFS stalls at both of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext606__amfs_stall_all_input_slice7__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt3_ext606_AMFS_STALL_ALL_INPUT_SLICE7_availability,
            },

            {
                .name = "AMFS STALL ANY INPUT SLICE7",
                .symbol_name = "AMFS_STALL_ANY_INPUT_SLICE7",
                .desc = "Percentage of time in which AMFS stalls at any of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext606__amfs_stall_any_input_slice7__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt3_ext606_AMFS_STALL_ANY_INPUT_SLICE7_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext606__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext606__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext606__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext606__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RENDER CACHE HIT L3NODE7",
                .symbol_name = "RENDER_CACHE_HIT_L3NODE7",
                .desc = "Number of Render Cache hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext606__render_cache_hit_l3_node7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext606_RENDER_CACHE_HIT_L3NODE7_availability,
            },

            {
                .name = "RENDER_CACHE_INPUT_AVAILABLE _L3NODE7",
                .symbol_name = "RENDER_CACHE_INPUT_AVAILABLE_L3NODE7",
                .desc = "Percentage of time when render cache input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext606__render_cache_input_available_l3_node7__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext606_RENDER_CACHE_INPUT_AVAILABLE_L3NODE7_availability,
            },

            {
                .name = "RENDER_CACHE_OUTPUT_READY _L3NODE7",
                .symbol_name = "RENDER_CACHE_OUTPUT_READY_L3NODE7",
                .desc = "Percentage of time when render cache output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext606__render_cache_output_ready_l3_node7__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt3_ext606_RENDER_CACHE_OUTPUT_READY_L3NODE7_availability,
            },

            {
                .name = "RENDER CACHE READ L3NODE7",
                .symbol_name = "RENDER_CACHE_READ_L3NODE7",
                .desc = "Number of Render Cache reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext606__render_cache_read_l3_node7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext606_RENDER_CACHE_READ_L3NODE7_availability,
            },

            {
                .name = "RENDER CACHE WRITE L3NODE7",
                .symbol_name = "RENDER_CACHE_WRITE_L3NODE7",
                .desc = "Number of Render Cache writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext606__render_cache_write_l3_node7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext606_RENDER_CACHE_WRITE_L3NODE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt3_ext607_AMFS_4X4_SHADING_REQUEST_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext607_AMFS_4X4_SHADING_REQUEST_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext607_AMFS_4X4_SHADING_REQUEST_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext607_AMFS_4X4_SHADING_REQUEST_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext607_AMFS_4X4_SHADING_REQUEST_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext607_AMFS_4X4_SHADING_REQUEST_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext607_AMFS_4X4_SHADING_REQUEST_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext607_AMFS_4X4_SHADING_REQUEST_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext607_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext607";
    metric_set->symbol_name = "Ext607";
    metric_set->hw_config_guid = "4542bc83-0786-4a99-977c-52a7f0418de1";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext607_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS 4X4 SHADING REQUEST SLICE0",
                .symbol_name = "AMFS_4X4_SHADING_REQUEST_SLICE0",
                .desc = "Number of Shading Request (evaluate) messages processed by AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext607__amfs_4_x4_shading_request_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext607_AMFS_4X4_SHADING_REQUEST_SLICE0_availability,
            },

            {
                .name = "AMFS 4X4 SHADING REQUEST SLICE1",
                .symbol_name = "AMFS_4X4_SHADING_REQUEST_SLICE1",
                .desc = "Number of Shading Request (evaluate) messages processed by AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext607__amfs_4_x4_shading_request_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext607_AMFS_4X4_SHADING_REQUEST_SLICE1_availability,
            },

            {
                .name = "AMFS 4X4 SHADING REQUEST SLICE2",
                .symbol_name = "AMFS_4X4_SHADING_REQUEST_SLICE2",
                .desc = "Number of Shading Request (evaluate) messages processed by AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext607__amfs_4_x4_shading_request_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext607_AMFS_4X4_SHADING_REQUEST_SLICE2_availability,
            },

            {
                .name = "AMFS 4X4 SHADING REQUEST SLICE3",
                .symbol_name = "AMFS_4X4_SHADING_REQUEST_SLICE3",
                .desc = "Number of Shading Request (evaluate) messages processed by AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext607__amfs_4_x4_shading_request_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext607_AMFS_4X4_SHADING_REQUEST_SLICE3_availability,
            },

            {
                .name = "AMFS 4X4 SHADING REQUEST SLICE4",
                .symbol_name = "AMFS_4X4_SHADING_REQUEST_SLICE4",
                .desc = "Number of Shading Request (evaluate) messages processed by AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext607__amfs_4_x4_shading_request_slice4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext607_AMFS_4X4_SHADING_REQUEST_SLICE4_availability,
            },

            {
                .name = "AMFS 4X4 SHADING REQUEST SLICE5",
                .symbol_name = "AMFS_4X4_SHADING_REQUEST_SLICE5",
                .desc = "Number of Shading Request (evaluate) messages processed by AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext607__amfs_4_x4_shading_request_slice5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext607_AMFS_4X4_SHADING_REQUEST_SLICE5_availability,
            },

            {
                .name = "AMFS 4X4 SHADING REQUEST SLICE6",
                .symbol_name = "AMFS_4X4_SHADING_REQUEST_SLICE6",
                .desc = "Number of Shading Request (evaluate) messages processed by AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext607__amfs_4_x4_shading_request_slice6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext607_AMFS_4X4_SHADING_REQUEST_SLICE6_availability,
            },

            {
                .name = "AMFS 4X4 SHADING REQUEST SLICE7",
                .symbol_name = "AMFS_4X4_SHADING_REQUEST_SLICE7",
                .desc = "Number of Shading Request (evaluate) messages processed by AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext607__amfs_4_x4_shading_request_slice7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext607_AMFS_4X4_SHADING_REQUEST_SLICE7_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext607__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext607__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext607__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext607__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext608_AMFS_L3_ATOMIC_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext608_AMFS_L3_ATOMIC_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext608_AMFS_L3_ATOMIC_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext608_AMFS_L3_ATOMIC_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext608_AMFS_L3_ATOMIC_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext608_AMFS_L3_ATOMIC_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext608_AMFS_L3_ATOMIC_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext608_AMFS_L3_ATOMIC_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext608_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext608";
    metric_set->symbol_name = "Ext608";
    metric_set->hw_config_guid = "8dcf0fe7-8df6-4abc-a15d-26dcdb7634f0";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext608_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS L3 ATOMIC SLICE0",
                .symbol_name = "AMFS_L3_ATOMIC_SLICE0",
                .desc = "Number of AMFS atomics to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext608__amfs_l3_atomic_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext608_AMFS_L3_ATOMIC_SLICE0_availability,
            },

            {
                .name = "AMFS L3 ATOMIC SLICE1",
                .symbol_name = "AMFS_L3_ATOMIC_SLICE1",
                .desc = "Number of AMFS atomics to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext608__amfs_l3_atomic_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext608_AMFS_L3_ATOMIC_SLICE1_availability,
            },

            {
                .name = "AMFS L3 ATOMIC SLICE2",
                .symbol_name = "AMFS_L3_ATOMIC_SLICE2",
                .desc = "Number of AMFS atomics to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext608__amfs_l3_atomic_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext608_AMFS_L3_ATOMIC_SLICE2_availability,
            },

            {
                .name = "AMFS L3 ATOMIC SLICE3",
                .symbol_name = "AMFS_L3_ATOMIC_SLICE3",
                .desc = "Number of AMFS atomics to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext608__amfs_l3_atomic_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext608_AMFS_L3_ATOMIC_SLICE3_availability,
            },

            {
                .name = "AMFS L3 ATOMIC SLICE4",
                .symbol_name = "AMFS_L3_ATOMIC_SLICE4",
                .desc = "Number of AMFS atomics to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext608__amfs_l3_atomic_slice4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext608_AMFS_L3_ATOMIC_SLICE4_availability,
            },

            {
                .name = "AMFS L3 ATOMIC SLICE5",
                .symbol_name = "AMFS_L3_ATOMIC_SLICE5",
                .desc = "Number of AMFS atomics to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext608__amfs_l3_atomic_slice5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext608_AMFS_L3_ATOMIC_SLICE5_availability,
            },

            {
                .name = "AMFS L3 ATOMIC SLICE6",
                .symbol_name = "AMFS_L3_ATOMIC_SLICE6",
                .desc = "Number of AMFS atomics to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext608__amfs_l3_atomic_slice6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext608_AMFS_L3_ATOMIC_SLICE6_availability,
            },

            {
                .name = "AMFS L3 ATOMIC SLICE7",
                .symbol_name = "AMFS_L3_ATOMIC_SLICE7",
                .desc = "Number of AMFS atomics to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext608__amfs_l3_atomic_slice7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext608_AMFS_L3_ATOMIC_SLICE7_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext608__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext608__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext608__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext608__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext609_AMFS_L3_ACCESS_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext609_AMFS_L3_ACCESS_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext609_AMFS_L3_ACCESS_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext609_AMFS_L3_ACCESS_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext609_AMFS_L3_ACCESS_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext609_AMFS_L3_ACCESS_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext609_AMFS_L3_ACCESS_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext609_AMFS_L3_ACCESS_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext609_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext609";
    metric_set->symbol_name = "Ext609";
    metric_set->hw_config_guid = "ee320b1d-1350-4b3a-bcbf-9de658bcd8f5";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext609_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS L3 ACCESS SLICE0",
                .symbol_name = "AMFS_L3_ACCESS_SLICE0",
                .desc = "Number of AMFS accesses to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext609__amfs_l3_access_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext609_AMFS_L3_ACCESS_SLICE0_availability,
            },

            {
                .name = "AMFS L3 ACCESS SLICE1",
                .symbol_name = "AMFS_L3_ACCESS_SLICE1",
                .desc = "Number of AMFS accesses to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext609__amfs_l3_access_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext609_AMFS_L3_ACCESS_SLICE1_availability,
            },

            {
                .name = "AMFS L3 ACCESS SLICE2",
                .symbol_name = "AMFS_L3_ACCESS_SLICE2",
                .desc = "Number of AMFS accesses to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext609__amfs_l3_access_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext609_AMFS_L3_ACCESS_SLICE2_availability,
            },

            {
                .name = "AMFS L3 ACCESS SLICE3",
                .symbol_name = "AMFS_L3_ACCESS_SLICE3",
                .desc = "Number of AMFS accesses to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext609__amfs_l3_access_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext609_AMFS_L3_ACCESS_SLICE3_availability,
            },

            {
                .name = "AMFS L3 ACCESS SLICE4",
                .symbol_name = "AMFS_L3_ACCESS_SLICE4",
                .desc = "Number of AMFS accesses to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext609__amfs_l3_access_slice4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext609_AMFS_L3_ACCESS_SLICE4_availability,
            },

            {
                .name = "AMFS L3 ACCESS SLICE5",
                .symbol_name = "AMFS_L3_ACCESS_SLICE5",
                .desc = "Number of AMFS accesses to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext609__amfs_l3_access_slice5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext609_AMFS_L3_ACCESS_SLICE5_availability,
            },

            {
                .name = "AMFS L3 ACCESS SLICE6",
                .symbol_name = "AMFS_L3_ACCESS_SLICE6",
                .desc = "Number of AMFS accesses to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext609__amfs_l3_access_slice6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext609_AMFS_L3_ACCESS_SLICE6_availability,
            },

            {
                .name = "AMFS L3 ACCESS SLICE7",
                .symbol_name = "AMFS_L3_ACCESS_SLICE7",
                .desc = "Number of AMFS accesses to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext609__amfs_l3_access_slice7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext609_AMFS_L3_ACCESS_SLICE7_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext609__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext609__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext609__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext609__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext610_AMFS_L3_WRITE_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext610_AMFS_L3_WRITE_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext610_AMFS_L3_WRITE_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext610_AMFS_L3_WRITE_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext610_AMFS_L3_WRITE_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext610_AMFS_L3_WRITE_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext610_AMFS_L3_WRITE_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext610_AMFS_L3_WRITE_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext610_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext610";
    metric_set->symbol_name = "Ext610";
    metric_set->hw_config_guid = "2530a673-a35d-4646-82c3-a8c3330c1baf";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext610_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS L3 WRITE SLICE0",
                .symbol_name = "AMFS_L3_WRITE_SLICE0",
                .desc = "Number of AMFS writes to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext610__amfs_l3_write_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext610_AMFS_L3_WRITE_SLICE0_availability,
            },

            {
                .name = "AMFS L3 WRITE SLICE1",
                .symbol_name = "AMFS_L3_WRITE_SLICE1",
                .desc = "Number of AMFS writes to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext610__amfs_l3_write_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext610_AMFS_L3_WRITE_SLICE1_availability,
            },

            {
                .name = "AMFS L3 WRITE SLICE2",
                .symbol_name = "AMFS_L3_WRITE_SLICE2",
                .desc = "Number of AMFS writes to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext610__amfs_l3_write_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext610_AMFS_L3_WRITE_SLICE2_availability,
            },

            {
                .name = "AMFS L3 WRITE SLICE3",
                .symbol_name = "AMFS_L3_WRITE_SLICE3",
                .desc = "Number of AMFS writes to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext610__amfs_l3_write_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext610_AMFS_L3_WRITE_SLICE3_availability,
            },

            {
                .name = "AMFS L3 WRITE SLICE4",
                .symbol_name = "AMFS_L3_WRITE_SLICE4",
                .desc = "Number of AMFS writes to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext610__amfs_l3_write_slice4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext610_AMFS_L3_WRITE_SLICE4_availability,
            },

            {
                .name = "AMFS L3 WRITE SLICE5",
                .symbol_name = "AMFS_L3_WRITE_SLICE5",
                .desc = "Number of AMFS writes to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext610__amfs_l3_write_slice5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext610_AMFS_L3_WRITE_SLICE5_availability,
            },

            {
                .name = "AMFS L3 WRITE SLICE6",
                .symbol_name = "AMFS_L3_WRITE_SLICE6",
                .desc = "Number of AMFS writes to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext610__amfs_l3_write_slice6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext610_AMFS_L3_WRITE_SLICE6_availability,
            },

            {
                .name = "AMFS L3 WRITE SLICE7",
                .symbol_name = "AMFS_L3_WRITE_SLICE7",
                .desc = "Number of AMFS writes to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext610__amfs_l3_write_slice7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt3_ext610_AMFS_L3_WRITE_SLICE7_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext610__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext610__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext610__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext610__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext611_CLIPPER_INPUT_VERTEX_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext611_CLIPPER_INPUT_VERTEX_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext611_CLIPPER_INPUT_VERTEX_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext611_CLIPPER_INPUT_VERTEX_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext611_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext611_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext611_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext611_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext611_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext611";
    metric_set->symbol_name = "Ext611";
    metric_set->hw_config_guid = "bb03aede-d6b2-4a50-a851-cdbaaa918df9";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext611_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext611__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext611__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CLIPPER INPUT VERTEX SLICE0",
                .symbol_name = "CLIPPER_INPUT_VERTEX_SLICE0",
                .desc = "Number of Clipper input vertices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext611__clipper_input_vertex_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext611_CLIPPER_INPUT_VERTEX_SLICE0_availability,
            },

            {
                .name = "CLIPPER INPUT VERTEX SLICE1",
                .symbol_name = "CLIPPER_INPUT_VERTEX_SLICE1",
                .desc = "Number of Clipper input vertices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext611__clipper_input_vertex_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext611_CLIPPER_INPUT_VERTEX_SLICE1_availability,
            },

            {
                .name = "CLIPPER INPUT VERTEX SLICE2",
                .symbol_name = "CLIPPER_INPUT_VERTEX_SLICE2",
                .desc = "Number of Clipper input vertices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext611__clipper_input_vertex_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext611_CLIPPER_INPUT_VERTEX_SLICE2_availability,
            },

            {
                .name = "CLIPPER INPUT VERTEX SLICE3",
                .symbol_name = "CLIPPER_INPUT_VERTEX_SLICE3",
                .desc = "Number of Clipper input vertices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext611__clipper_input_vertex_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext611_CLIPPER_INPUT_VERTEX_SLICE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext611__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext611__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "STREAMOUT OUTPUT VERTEX COUNT SLICE0",
                .symbol_name = "STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE0",
                .desc = "Number of vertices written by SOL",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext611__streamout_output_vertex_count_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext611_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE0_availability,
            },

            {
                .name = "STREAMOUT OUTPUT VERTEX COUNT SLICE1",
                .symbol_name = "STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE1",
                .desc = "Number of vertices written by SOL",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext611__streamout_output_vertex_count_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext611_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE1_availability,
            },

            {
                .name = "STREAMOUT OUTPUT VERTEX COUNT SLICE2",
                .symbol_name = "STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE2",
                .desc = "Number of vertices written by SOL",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext611__streamout_output_vertex_count_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext611_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE2_availability,
            },

            {
                .name = "STREAMOUT OUTPUT VERTEX COUNT SLICE3",
                .symbol_name = "STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE3",
                .desc = "Number of vertices written by SOL",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext611__streamout_output_vertex_count_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext611_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext612_CLIPPER_INPUT_VERTEX_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext612_CLIPPER_INPUT_VERTEX_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext612_CLIPPER_INPUT_VERTEX_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext612_CLIPPER_INPUT_VERTEX_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext612_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext612_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext612_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext612_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext612_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext612";
    metric_set->symbol_name = "Ext612";
    metric_set->hw_config_guid = "c9b9305f-5bbd-49cb-8835-f351efcc48ce";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext612_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext612__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext612__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CLIPPER INPUT VERTEX SLICE4",
                .symbol_name = "CLIPPER_INPUT_VERTEX_SLICE4",
                .desc = "Number of Clipper input vertices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext612__clipper_input_vertex_slice4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext612_CLIPPER_INPUT_VERTEX_SLICE4_availability,
            },

            {
                .name = "CLIPPER INPUT VERTEX SLICE5",
                .symbol_name = "CLIPPER_INPUT_VERTEX_SLICE5",
                .desc = "Number of Clipper input vertices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext612__clipper_input_vertex_slice5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext612_CLIPPER_INPUT_VERTEX_SLICE5_availability,
            },

            {
                .name = "CLIPPER INPUT VERTEX SLICE6",
                .symbol_name = "CLIPPER_INPUT_VERTEX_SLICE6",
                .desc = "Number of Clipper input vertices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext612__clipper_input_vertex_slice6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext612_CLIPPER_INPUT_VERTEX_SLICE6_availability,
            },

            {
                .name = "CLIPPER INPUT VERTEX SLICE7",
                .symbol_name = "CLIPPER_INPUT_VERTEX_SLICE7",
                .desc = "Number of Clipper input vertices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext612__clipper_input_vertex_slice7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext612_CLIPPER_INPUT_VERTEX_SLICE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext612__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext612__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "STREAMOUT OUTPUT VERTEX COUNT SLICE4",
                .symbol_name = "STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE4",
                .desc = "Number of vertices written by SOL",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext612__streamout_output_vertex_count_slice4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext612_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE4_availability,
            },

            {
                .name = "STREAMOUT OUTPUT VERTEX COUNT SLICE5",
                .symbol_name = "STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE5",
                .desc = "Number of vertices written by SOL",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext612__streamout_output_vertex_count_slice5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext612_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE5_availability,
            },

            {
                .name = "STREAMOUT OUTPUT VERTEX COUNT SLICE6",
                .symbol_name = "STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE6",
                .desc = "Number of vertices written by SOL",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext612__streamout_output_vertex_count_slice6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext612_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE6_availability,
            },

            {
                .name = "STREAMOUT OUTPUT VERTEX COUNT SLICE7",
                .symbol_name = "STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE7",
                .desc = "Number of vertices written by SOL",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext612__streamout_output_vertex_count_slice7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext612_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext613_VERTEX_FETCH_INPUT_AVAILABLE_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext613_VERTEX_FETCH_INPUT_AVAILABLE_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext613_VERTEX_FETCH_INPUT_AVAILABLE_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext613_VERTEX_FETCH_INPUT_AVAILABLE_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext613_VERTEX_FETCH_INPUT_AVAILABLE_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext613_VERTEX_FETCH_INPUT_AVAILABLE_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext613_VERTEX_FETCH_INPUT_AVAILABLE_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext613_VERTEX_FETCH_INPUT_AVAILABLE_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext613_VERTEX_FETCH_OUTPUT_READY_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext613_VERTEX_FETCH_OUTPUT_READY_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext613_VERTEX_FETCH_OUTPUT_READY_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext613_VERTEX_FETCH_OUTPUT_READY_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext613_VERTEX_FETCH_OUTPUT_READY_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext613_VERTEX_FETCH_OUTPUT_READY_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext613_VERTEX_FETCH_OUTPUT_READY_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext613_VERTEX_FETCH_OUTPUT_READY_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext613_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext613";
    metric_set->symbol_name = "Ext613";
    metric_set->hw_config_guid = "d5d3fda8-e845-4038-a746-538432843c47";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext613_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext613__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext613__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext613__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext613__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "VERTEX FETCH INPUT AVAILABLE SLICE0",
                .symbol_name = "VERTEX_FETCH_INPUT_AVAILABLE_SLICE0",
                .desc = "Percentage of time in which Vertex Fetch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext613__vertex_fetch_input_available_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext613_VERTEX_FETCH_INPUT_AVAILABLE_SLICE0_availability,
            },

            {
                .name = "VERTEX FETCH INPUT AVAILABLE SLICE1",
                .symbol_name = "VERTEX_FETCH_INPUT_AVAILABLE_SLICE1",
                .desc = "Percentage of time in which Vertex Fetch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext613__vertex_fetch_input_available_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext613_VERTEX_FETCH_INPUT_AVAILABLE_SLICE1_availability,
            },

            {
                .name = "VERTEX FETCH INPUT AVAILABLE SLICE2",
                .symbol_name = "VERTEX_FETCH_INPUT_AVAILABLE_SLICE2",
                .desc = "Percentage of time in which Vertex Fetch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext613__vertex_fetch_input_available_slice2__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext613_VERTEX_FETCH_INPUT_AVAILABLE_SLICE2_availability,
            },

            {
                .name = "VERTEX FETCH INPUT AVAILABLE SLICE3",
                .symbol_name = "VERTEX_FETCH_INPUT_AVAILABLE_SLICE3",
                .desc = "Percentage of time in which Vertex Fetch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext613__vertex_fetch_input_available_slice3__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext613_VERTEX_FETCH_INPUT_AVAILABLE_SLICE3_availability,
            },

            {
                .name = "VERTEX FETCH INPUT AVAILABLE SLICE4",
                .symbol_name = "VERTEX_FETCH_INPUT_AVAILABLE_SLICE4",
                .desc = "Percentage of time in which Vertex Fetch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext613__vertex_fetch_input_available_slice4__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext613_VERTEX_FETCH_INPUT_AVAILABLE_SLICE4_availability,
            },

            {
                .name = "VERTEX FETCH INPUT AVAILABLE SLICE5",
                .symbol_name = "VERTEX_FETCH_INPUT_AVAILABLE_SLICE5",
                .desc = "Percentage of time in which Vertex Fetch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext613__vertex_fetch_input_available_slice5__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext613_VERTEX_FETCH_INPUT_AVAILABLE_SLICE5_availability,
            },

            {
                .name = "VERTEX FETCH INPUT AVAILABLE SLICE6",
                .symbol_name = "VERTEX_FETCH_INPUT_AVAILABLE_SLICE6",
                .desc = "Percentage of time in which Vertex Fetch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext613__vertex_fetch_input_available_slice6__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext613_VERTEX_FETCH_INPUT_AVAILABLE_SLICE6_availability,
            },

            {
                .name = "VERTEX FETCH INPUT AVAILABLE SLICE7",
                .symbol_name = "VERTEX_FETCH_INPUT_AVAILABLE_SLICE7",
                .desc = "Percentage of time in which Vertex Fetch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext613__vertex_fetch_input_available_slice7__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext613_VERTEX_FETCH_INPUT_AVAILABLE_SLICE7_availability,
            },

            {
                .name = "VERTEX FETCH OUTPUT READY SLICE0",
                .symbol_name = "VERTEX_FETCH_OUTPUT_READY_SLICE0",
                .desc = "Percentage of time in which Vertex Fetch output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext613__vertex_fetch_output_ready_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext613_VERTEX_FETCH_OUTPUT_READY_SLICE0_availability,
            },

            {
                .name = "VERTEX FETCH OUTPUT READY SLICE1",
                .symbol_name = "VERTEX_FETCH_OUTPUT_READY_SLICE1",
                .desc = "Percentage of time in which Vertex Fetch output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext613__vertex_fetch_output_ready_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext613_VERTEX_FETCH_OUTPUT_READY_SLICE1_availability,
            },

            {
                .name = "VERTEX FETCH OUTPUT READY SLICE2",
                .symbol_name = "VERTEX_FETCH_OUTPUT_READY_SLICE2",
                .desc = "Percentage of time in which Vertex Fetch output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext613__vertex_fetch_output_ready_slice2__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext613_VERTEX_FETCH_OUTPUT_READY_SLICE2_availability,
            },

            {
                .name = "VERTEX FETCH OUTPUT READY SLICE3",
                .symbol_name = "VERTEX_FETCH_OUTPUT_READY_SLICE3",
                .desc = "Percentage of time in which Vertex Fetch output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext613__vertex_fetch_output_ready_slice3__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext613_VERTEX_FETCH_OUTPUT_READY_SLICE3_availability,
            },

            {
                .name = "VERTEX FETCH OUTPUT READY SLICE4",
                .symbol_name = "VERTEX_FETCH_OUTPUT_READY_SLICE4",
                .desc = "Percentage of time in which Vertex Fetch output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext613__vertex_fetch_output_ready_slice4__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext613_VERTEX_FETCH_OUTPUT_READY_SLICE4_availability,
            },

            {
                .name = "VERTEX FETCH OUTPUT READY SLICE5",
                .symbol_name = "VERTEX_FETCH_OUTPUT_READY_SLICE5",
                .desc = "Percentage of time in which Vertex Fetch output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext613__vertex_fetch_output_ready_slice5__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext613_VERTEX_FETCH_OUTPUT_READY_SLICE5_availability,
            },

            {
                .name = "VERTEX FETCH OUTPUT READY SLICE6",
                .symbol_name = "VERTEX_FETCH_OUTPUT_READY_SLICE6",
                .desc = "Percentage of time in which Vertex Fetch output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext613__vertex_fetch_output_ready_slice6__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext613_VERTEX_FETCH_OUTPUT_READY_SLICE6_availability,
            },

            {
                .name = "VERTEX FETCH OUTPUT READY SLICE7",
                .symbol_name = "VERTEX_FETCH_OUTPUT_READY_SLICE7",
                .desc = "Percentage of time in which Vertex Fetch output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext613__vertex_fetch_output_ready_slice7__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext613_VERTEX_FETCH_OUTPUT_READY_SLICE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext614_CLIPPER_INPUT_AVAILABLE_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext614_CLIPPER_INPUT_AVAILABLE_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext614_CLIPPER_INPUT_AVAILABLE_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext614_CLIPPER_INPUT_AVAILABLE_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext614_CLIPPER_INPUT_AVAILABLE_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext614_CLIPPER_INPUT_AVAILABLE_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext614_CLIPPER_INPUT_AVAILABLE_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext614_CLIPPER_INPUT_AVAILABLE_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext614_VS_OUTPUT_READY_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext614_VS_OUTPUT_READY_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext614_VS_OUTPUT_READY_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext614_VS_OUTPUT_READY_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext614_VS_OUTPUT_READY_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext614_VS_OUTPUT_READY_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext614_VS_OUTPUT_READY_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext614_VS_OUTPUT_READY_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext614_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext614";
    metric_set->symbol_name = "Ext614";
    metric_set->hw_config_guid = "2183a6ac-d667-4b20-a851-b97ccb5d5b21";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext614_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext614__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext614__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CLIPPER INPUT AVAILABLE SLICE0",
                .symbol_name = "CLIPPER_INPUT_AVAILABLE_SLICE0",
                .desc = "Percentage of time in which Clipper has input available (from Vertex Shader or SOL)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext614__clipper_input_available_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext614_CLIPPER_INPUT_AVAILABLE_SLICE0_availability,
            },

            {
                .name = "CLIPPER INPUT AVAILABLE SLICE1",
                .symbol_name = "CLIPPER_INPUT_AVAILABLE_SLICE1",
                .desc = "Percentage of time in which Clipper has input available (from Vertex Shader or SOL)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext614__clipper_input_available_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext614_CLIPPER_INPUT_AVAILABLE_SLICE1_availability,
            },

            {
                .name = "CLIPPER INPUT AVAILABLE SLICE2",
                .symbol_name = "CLIPPER_INPUT_AVAILABLE_SLICE2",
                .desc = "Percentage of time in which Clipper has input available (from Vertex Shader or SOL)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext614__clipper_input_available_slice2__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext614_CLIPPER_INPUT_AVAILABLE_SLICE2_availability,
            },

            {
                .name = "CLIPPER INPUT AVAILABLE SLICE3",
                .symbol_name = "CLIPPER_INPUT_AVAILABLE_SLICE3",
                .desc = "Percentage of time in which Clipper has input available (from Vertex Shader or SOL)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext614__clipper_input_available_slice3__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext614_CLIPPER_INPUT_AVAILABLE_SLICE3_availability,
            },

            {
                .name = "CLIPPER INPUT AVAILABLE SLICE4",
                .symbol_name = "CLIPPER_INPUT_AVAILABLE_SLICE4",
                .desc = "Percentage of time in which Clipper has input available (from Vertex Shader or SOL)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext614__clipper_input_available_slice4__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext614_CLIPPER_INPUT_AVAILABLE_SLICE4_availability,
            },

            {
                .name = "CLIPPER INPUT AVAILABLE SLICE5",
                .symbol_name = "CLIPPER_INPUT_AVAILABLE_SLICE5",
                .desc = "Percentage of time in which Clipper has input available (from Vertex Shader or SOL)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext614__clipper_input_available_slice5__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext614_CLIPPER_INPUT_AVAILABLE_SLICE5_availability,
            },

            {
                .name = "CLIPPER INPUT AVAILABLE SLICE6",
                .symbol_name = "CLIPPER_INPUT_AVAILABLE_SLICE6",
                .desc = "Percentage of time in which Clipper has input available (from Vertex Shader or SOL)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext614__clipper_input_available_slice6__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext614_CLIPPER_INPUT_AVAILABLE_SLICE6_availability,
            },

            {
                .name = "CLIPPER INPUT AVAILABLE SLICE7",
                .symbol_name = "CLIPPER_INPUT_AVAILABLE_SLICE7",
                .desc = "Percentage of time in which Clipper has input available (from Vertex Shader or SOL)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext614__clipper_input_available_slice7__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext614_CLIPPER_INPUT_AVAILABLE_SLICE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext614__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext614__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "VS OUTPUT READY SLICE0",
                .symbol_name = "VS_OUTPUT_READY_SLICE0",
                .desc = "Percentage of time in which Vertex Shader output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext614__vs_output_ready_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext614_VS_OUTPUT_READY_SLICE0_availability,
            },

            {
                .name = "VS OUTPUT READY SLICE1",
                .symbol_name = "VS_OUTPUT_READY_SLICE1",
                .desc = "Percentage of time in which Vertex Shader output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext614__vs_output_ready_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext614_VS_OUTPUT_READY_SLICE1_availability,
            },

            {
                .name = "VS OUTPUT READY SLICE2",
                .symbol_name = "VS_OUTPUT_READY_SLICE2",
                .desc = "Percentage of time in which Vertex Shader output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext614__vs_output_ready_slice2__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext614_VS_OUTPUT_READY_SLICE2_availability,
            },

            {
                .name = "VS OUTPUT READY SLICE3",
                .symbol_name = "VS_OUTPUT_READY_SLICE3",
                .desc = "Percentage of time in which Vertex Shader output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext614__vs_output_ready_slice3__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext614_VS_OUTPUT_READY_SLICE3_availability,
            },

            {
                .name = "VS OUTPUT READY SLICE4",
                .symbol_name = "VS_OUTPUT_READY_SLICE4",
                .desc = "Percentage of time in which Vertex Shader output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext614__vs_output_ready_slice4__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext614_VS_OUTPUT_READY_SLICE4_availability,
            },

            {
                .name = "VS OUTPUT READY SLICE5",
                .symbol_name = "VS_OUTPUT_READY_SLICE5",
                .desc = "Percentage of time in which Vertex Shader output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext614__vs_output_ready_slice5__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext614_VS_OUTPUT_READY_SLICE5_availability,
            },

            {
                .name = "VS OUTPUT READY SLICE6",
                .symbol_name = "VS_OUTPUT_READY_SLICE6",
                .desc = "Percentage of time in which Vertex Shader output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext614__vs_output_ready_slice6__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext614_VS_OUTPUT_READY_SLICE6_availability,
            },

            {
                .name = "VS OUTPUT READY SLICE7",
                .symbol_name = "VS_OUTPUT_READY_SLICE7",
                .desc = "Percentage of time in which Vertex Shader output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext614__vs_output_ready_slice7__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext614_VS_OUTPUT_READY_SLICE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext615_CLIPPER_OUTPUT_READY_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext615_CLIPPER_OUTPUT_READY_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext615_CLIPPER_OUTPUT_READY_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext615_CLIPPER_OUTPUT_READY_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext615_CLIPPER_OUTPUT_READY_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext615_CLIPPER_OUTPUT_READY_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext615_CLIPPER_OUTPUT_READY_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext615_CLIPPER_OUTPUT_READY_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext615_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext615";
    metric_set->symbol_name = "Ext615";
    metric_set->hw_config_guid = "736b7243-3c5a-41c7-a212-d506ebdf2fe2";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext615_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext615__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext615__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CLIPPER OUTPUT READY SLICE0",
                .symbol_name = "CLIPPER_OUTPUT_READY_SLICE0",
                .desc = "Percentage of time in which Clipper output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext615__clipper_output_ready_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext615_CLIPPER_OUTPUT_READY_SLICE0_availability,
            },

            {
                .name = "CLIPPER OUTPUT READY SLICE1",
                .symbol_name = "CLIPPER_OUTPUT_READY_SLICE1",
                .desc = "Percentage of time in which Clipper output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext615__clipper_output_ready_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext615_CLIPPER_OUTPUT_READY_SLICE1_availability,
            },

            {
                .name = "CLIPPER OUTPUT READY SLICE2",
                .symbol_name = "CLIPPER_OUTPUT_READY_SLICE2",
                .desc = "Percentage of time in which Clipper output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext615__clipper_output_ready_slice2__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext615_CLIPPER_OUTPUT_READY_SLICE2_availability,
            },

            {
                .name = "CLIPPER OUTPUT READY SLICE3",
                .symbol_name = "CLIPPER_OUTPUT_READY_SLICE3",
                .desc = "Percentage of time in which Clipper output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext615__clipper_output_ready_slice3__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext615_CLIPPER_OUTPUT_READY_SLICE3_availability,
            },

            {
                .name = "CLIPPER OUTPUT READY SLICE4",
                .symbol_name = "CLIPPER_OUTPUT_READY_SLICE4",
                .desc = "Percentage of time in which Clipper output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext615__clipper_output_ready_slice4__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext615_CLIPPER_OUTPUT_READY_SLICE4_availability,
            },

            {
                .name = "CLIPPER OUTPUT READY SLICE5",
                .symbol_name = "CLIPPER_OUTPUT_READY_SLICE5",
                .desc = "Percentage of time in which Clipper output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext615__clipper_output_ready_slice5__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext615_CLIPPER_OUTPUT_READY_SLICE5_availability,
            },

            {
                .name = "CLIPPER OUTPUT READY SLICE6",
                .symbol_name = "CLIPPER_OUTPUT_READY_SLICE6",
                .desc = "Percentage of time in which Clipper output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext615__clipper_output_ready_slice6__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext615_CLIPPER_OUTPUT_READY_SLICE6_availability,
            },

            {
                .name = "CLIPPER OUTPUT READY SLICE7",
                .symbol_name = "CLIPPER_OUTPUT_READY_SLICE7",
                .desc = "Percentage of time in which Clipper output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext615__clipper_output_ready_slice7__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext615_CLIPPER_OUTPUT_READY_SLICE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext615__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext615__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}


static void
acmgt3_add_ext616_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext616";
    metric_set->symbol_name = "Ext616";
    metric_set->hw_config_guid = "bebf8f78-b673-479f-803c-2e1f403454b3";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext616_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext616__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext616__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY WRITE",
                .symbol_name = "GPU_MEMORY_WRITE",
                .desc = "Number of GTI memory writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext616__gpu_memory_write__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY WRITE SQIDI0",
                .symbol_name = "GPU_MEMORY_WRITE_SQIDI0",
                .desc = "Number of GTI memory writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext616__gpu_memory_write_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY WRITE SQIDI1",
                .symbol_name = "GPU_MEMORY_WRITE_SQIDI1",
                .desc = "Number of GTI memory writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext616__gpu_memory_write_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY WRITE SQIDI2",
                .symbol_name = "GPU_MEMORY_WRITE_SQIDI2",
                .desc = "Number of GTI memory writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext616__gpu_memory_write_sqidi2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY WRITE SQIDI3",
                .symbol_name = "GPU_MEMORY_WRITE_SQIDI3",
                .desc = "Number of GTI memory writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext616__gpu_memory_write_sqidi3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY WRITE SQIDI4",
                .symbol_name = "GPU_MEMORY_WRITE_SQIDI4",
                .desc = "Number of GTI memory writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext616__gpu_memory_write_sqidi4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY WRITE SQIDI5",
                .symbol_name = "GPU_MEMORY_WRITE_SQIDI5",
                .desc = "Number of GTI memory writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext616__gpu_memory_write_sqidi5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY WRITE SQIDI6",
                .symbol_name = "GPU_MEMORY_WRITE_SQIDI6",
                .desc = "Number of GTI memory writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext616__gpu_memory_write_sqidi6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY WRITE SQIDI7",
                .symbol_name = "GPU_MEMORY_WRITE_SQIDI7",
                .desc = "Number of GTI memory writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext616__gpu_memory_write_sqidi7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext616__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext616__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt3_ext617_CLIPPER_PRIMITIVE_OUTPUT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext617_CLIPPER_PRIMITIVE_OUTPUT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext617_CLIPPER_PRIMITIVE_OUTPUT_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext617_CLIPPER_PRIMITIVE_OUTPUT_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext617_CLIPPER_PRIMITIVE_OUTPUT_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext617_CLIPPER_PRIMITIVE_OUTPUT_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext617_CLIPPER_PRIMITIVE_OUTPUT_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext617_CLIPPER_PRIMITIVE_OUTPUT_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext617_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext617";
    metric_set->symbol_name = "Ext617";
    metric_set->hw_config_guid = "3a2d5424-78f7-445d-857f-fbea361be3fb";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext617_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext617__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext617__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CLIPPER PRIMITIVE OUTPUT SLICE0",
                .symbol_name = "CLIPPER_PRIMITIVE_OUTPUT_SLICE0",
                .desc = "Number of primitives going out of Clipper, must clip plus the trivial accept",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext617__clipper_primitive_output_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext617_CLIPPER_PRIMITIVE_OUTPUT_SLICE0_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE OUTPUT SLICE1",
                .symbol_name = "CLIPPER_PRIMITIVE_OUTPUT_SLICE1",
                .desc = "Number of primitives going out of Clipper, must clip plus the trivial accept",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext617__clipper_primitive_output_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext617_CLIPPER_PRIMITIVE_OUTPUT_SLICE1_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE OUTPUT SLICE2",
                .symbol_name = "CLIPPER_PRIMITIVE_OUTPUT_SLICE2",
                .desc = "Number of primitives going out of Clipper, must clip plus the trivial accept",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext617__clipper_primitive_output_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext617_CLIPPER_PRIMITIVE_OUTPUT_SLICE2_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE OUTPUT SLICE3",
                .symbol_name = "CLIPPER_PRIMITIVE_OUTPUT_SLICE3",
                .desc = "Number of primitives going out of Clipper, must clip plus the trivial accept",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext617__clipper_primitive_output_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext617_CLIPPER_PRIMITIVE_OUTPUT_SLICE3_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE OUTPUT SLICE4",
                .symbol_name = "CLIPPER_PRIMITIVE_OUTPUT_SLICE4",
                .desc = "Number of primitives going out of Clipper, must clip plus the trivial accept",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext617__clipper_primitive_output_slice4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext617_CLIPPER_PRIMITIVE_OUTPUT_SLICE4_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE OUTPUT SLICE5",
                .symbol_name = "CLIPPER_PRIMITIVE_OUTPUT_SLICE5",
                .desc = "Number of primitives going out of Clipper, must clip plus the trivial accept",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext617__clipper_primitive_output_slice5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext617_CLIPPER_PRIMITIVE_OUTPUT_SLICE5_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE OUTPUT SLICE6",
                .symbol_name = "CLIPPER_PRIMITIVE_OUTPUT_SLICE6",
                .desc = "Number of primitives going out of Clipper, must clip plus the trivial accept",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext617__clipper_primitive_output_slice6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext617_CLIPPER_PRIMITIVE_OUTPUT_SLICE6_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE OUTPUT SLICE7",
                .symbol_name = "CLIPPER_PRIMITIVE_OUTPUT_SLICE7",
                .desc = "Number of primitives going out of Clipper, must clip plus the trivial accept",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext617__clipper_primitive_output_slice7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext617_CLIPPER_PRIMITIVE_OUTPUT_SLICE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext617__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext617__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext618_CLIPPER_PRIMITIVE_CULL_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext618_CLIPPER_PRIMITIVE_CULL_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext618_CLIPPER_PRIMITIVE_CULL_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext618_CLIPPER_PRIMITIVE_CULL_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext618_CLIPPER_PRIMITIVE_CULL_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext618_CLIPPER_PRIMITIVE_CULL_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext618_CLIPPER_PRIMITIVE_CULL_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext618_CLIPPER_PRIMITIVE_CULL_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext618_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext618";
    metric_set->symbol_name = "Ext618";
    metric_set->hw_config_guid = "43c7733d-9c5e-48c8-a1a6-4c82e487dab9";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext618_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext618__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext618__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CLIPPER PRIMITIVE CULL SLICE0",
                .symbol_name = "CLIPPER_PRIMITIVE_CULL_SLICE0",
                .desc = "Number of Clipper early cull primitives",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext618__clipper_primitive_cull_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext618_CLIPPER_PRIMITIVE_CULL_SLICE0_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE CULL SLICE1",
                .symbol_name = "CLIPPER_PRIMITIVE_CULL_SLICE1",
                .desc = "Number of Clipper early cull primitives",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext618__clipper_primitive_cull_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext618_CLIPPER_PRIMITIVE_CULL_SLICE1_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE CULL SLICE2",
                .symbol_name = "CLIPPER_PRIMITIVE_CULL_SLICE2",
                .desc = "Number of Clipper early cull primitives",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext618__clipper_primitive_cull_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext618_CLIPPER_PRIMITIVE_CULL_SLICE2_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE CULL SLICE3",
                .symbol_name = "CLIPPER_PRIMITIVE_CULL_SLICE3",
                .desc = "Number of Clipper early cull primitives",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext618__clipper_primitive_cull_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext618_CLIPPER_PRIMITIVE_CULL_SLICE3_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE CULL SLICE4",
                .symbol_name = "CLIPPER_PRIMITIVE_CULL_SLICE4",
                .desc = "Number of Clipper early cull primitives",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext618__clipper_primitive_cull_slice4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext618_CLIPPER_PRIMITIVE_CULL_SLICE4_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE CULL SLICE5",
                .symbol_name = "CLIPPER_PRIMITIVE_CULL_SLICE5",
                .desc = "Number of Clipper early cull primitives",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext618__clipper_primitive_cull_slice5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext618_CLIPPER_PRIMITIVE_CULL_SLICE5_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE CULL SLICE6",
                .symbol_name = "CLIPPER_PRIMITIVE_CULL_SLICE6",
                .desc = "Number of Clipper early cull primitives",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext618__clipper_primitive_cull_slice6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext618_CLIPPER_PRIMITIVE_CULL_SLICE6_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE CULL SLICE7",
                .symbol_name = "CLIPPER_PRIMITIVE_CULL_SLICE7",
                .desc = "Number of Clipper early cull primitives",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext618__clipper_primitive_cull_slice7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext618_CLIPPER_PRIMITIVE_CULL_SLICE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext618__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext618__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext619_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext619_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext619_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext619_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext619_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext619";
    metric_set->symbol_name = "Ext619";
    metric_set->hw_config_guid = "51f2492c-e8fb-4f62-b4a7-3acd0301e2f2";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext619_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext619__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext619__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CLIPPER PRIMITIVE FAR NEAR CLIP SLICE0",
                .symbol_name = "CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE0",
                .desc = "Number of primitives clipped by Clipper due to near/far planes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext619__clipper_primitive_far_near_clip_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext619_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE0_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE FAR NEAR CLIP SLICE1",
                .symbol_name = "CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE1",
                .desc = "Number of primitives clipped by Clipper due to near/far planes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext619__clipper_primitive_far_near_clip_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext619_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE1_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE FAR NEAR CLIP SLICE2",
                .symbol_name = "CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE2",
                .desc = "Number of primitives clipped by Clipper due to near/far planes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext619__clipper_primitive_far_near_clip_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext619_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE2_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE FAR NEAR CLIP SLICE3",
                .symbol_name = "CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE3",
                .desc = "Number of primitives clipped by Clipper due to near/far planes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext619__clipper_primitive_far_near_clip_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext619_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext619__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext619__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext620_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext620_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext620_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext620_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext620_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext620";
    metric_set->symbol_name = "Ext620";
    metric_set->hw_config_guid = "dd87d3c7-2f33-41ba-a19f-36cc5eecf723";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext620_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext620__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext620__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CLIPPER PRIMITIVE FAR NEAR CLIP SLICE4",
                .symbol_name = "CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE4",
                .desc = "Number of primitives clipped by Clipper due to near/far planes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext620__clipper_primitive_far_near_clip_slice4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext620_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE4_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE FAR NEAR CLIP SLICE5",
                .symbol_name = "CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE5",
                .desc = "Number of primitives clipped by Clipper due to near/far planes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext620__clipper_primitive_far_near_clip_slice5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext620_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE5_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE FAR NEAR CLIP SLICE6",
                .symbol_name = "CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE6",
                .desc = "Number of primitives clipped by Clipper due to near/far planes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext620__clipper_primitive_far_near_clip_slice6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext620_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE6_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE FAR NEAR CLIP SLICE7",
                .symbol_name = "CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE7",
                .desc = "Number of primitives clipped by Clipper due to near/far planes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext620__clipper_primitive_far_near_clip_slice7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext620_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext620__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext620__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext621_CLIPPER_TRANSACTION_OUTPUT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext621_CLIPPER_TRANSACTION_OUTPUT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext621_CLIPPER_TRANSACTION_OUTPUT_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext621_CLIPPER_TRANSACTION_OUTPUT_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext621_CLIPPER_TRANSACTION_OUTPUT_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext621_CLIPPER_TRANSACTION_OUTPUT_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext621_CLIPPER_TRANSACTION_OUTPUT_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext621_CLIPPER_TRANSACTION_OUTPUT_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext621_RASTERIZER_INPUT_AVAILABLE_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext621_RASTERIZER_INPUT_AVAILABLE_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext621_RASTERIZER_INPUT_AVAILABLE_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext621_RASTERIZER_INPUT_AVAILABLE_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext621_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext621";
    metric_set->symbol_name = "Ext621";
    metric_set->hw_config_guid = "5762280f-381f-4c9a-99dd-96811abec85d";
    metric_set->counters = calloc(15, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext621_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext621__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext621__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CLIPPER TRANSACTION OUTPUT SLICE0",
                .symbol_name = "CLIPPER_TRANSACTION_OUTPUT_SLICE0",
                .desc = "Number of elements pushed by Clipper into Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext621__clipper_transaction_output_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext621_CLIPPER_TRANSACTION_OUTPUT_SLICE0_availability,
            },

            {
                .name = "CLIPPER TRANSACTION OUTPUT SLICE1",
                .symbol_name = "CLIPPER_TRANSACTION_OUTPUT_SLICE1",
                .desc = "Number of elements pushed by Clipper into Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext621__clipper_transaction_output_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext621_CLIPPER_TRANSACTION_OUTPUT_SLICE1_availability,
            },

            {
                .name = "CLIPPER TRANSACTION OUTPUT SLICE2",
                .symbol_name = "CLIPPER_TRANSACTION_OUTPUT_SLICE2",
                .desc = "Number of elements pushed by Clipper into Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext621__clipper_transaction_output_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext621_CLIPPER_TRANSACTION_OUTPUT_SLICE2_availability,
            },

            {
                .name = "CLIPPER TRANSACTION OUTPUT SLICE3",
                .symbol_name = "CLIPPER_TRANSACTION_OUTPUT_SLICE3",
                .desc = "Number of elements pushed by Clipper into Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext621__clipper_transaction_output_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext621_CLIPPER_TRANSACTION_OUTPUT_SLICE3_availability,
            },

            {
                .name = "CLIPPER TRANSACTION OUTPUT SLICE4",
                .symbol_name = "CLIPPER_TRANSACTION_OUTPUT_SLICE4",
                .desc = "Number of elements pushed by Clipper into Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext621__clipper_transaction_output_slice4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext621_CLIPPER_TRANSACTION_OUTPUT_SLICE4_availability,
            },

            {
                .name = "CLIPPER TRANSACTION OUTPUT SLICE5",
                .symbol_name = "CLIPPER_TRANSACTION_OUTPUT_SLICE5",
                .desc = "Number of elements pushed by Clipper into Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext621__clipper_transaction_output_slice5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext621_CLIPPER_TRANSACTION_OUTPUT_SLICE5_availability,
            },

            {
                .name = "CLIPPER TRANSACTION OUTPUT SLICE6",
                .symbol_name = "CLIPPER_TRANSACTION_OUTPUT_SLICE6",
                .desc = "Number of elements pushed by Clipper into Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext621__clipper_transaction_output_slice6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext621_CLIPPER_TRANSACTION_OUTPUT_SLICE6_availability,
            },

            {
                .name = "CLIPPER TRANSACTION OUTPUT SLICE7",
                .symbol_name = "CLIPPER_TRANSACTION_OUTPUT_SLICE7",
                .desc = "Number of elements pushed by Clipper into Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext621__clipper_transaction_output_slice7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext621_CLIPPER_TRANSACTION_OUTPUT_SLICE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext621__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext621__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RASTERIZER INPUT AVAILABLE SLICE0",
                .symbol_name = "RASTERIZER_INPUT_AVAILABLE_SLICE0",
                .desc = "Percentage of time in which Rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext621__rasterizer_input_available_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_ext621_RASTERIZER_INPUT_AVAILABLE_SLICE0_availability,
            },

            {
                .name = "RASTERIZER INPUT AVAILABLE SLICE1",
                .symbol_name = "RASTERIZER_INPUT_AVAILABLE_SLICE1",
                .desc = "Percentage of time in which Rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext621__rasterizer_input_available_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_ext621_RASTERIZER_INPUT_AVAILABLE_SLICE1_availability,
            },

            {
                .name = "RASTERIZER INPUT AVAILABLE SLICE2",
                .symbol_name = "RASTERIZER_INPUT_AVAILABLE_SLICE2",
                .desc = "Percentage of time in which Rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext621__rasterizer_input_available_slice2__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_ext621_RASTERIZER_INPUT_AVAILABLE_SLICE2_availability,
            },

            {
                .name = "RASTERIZER INPUT AVAILABLE SLICE3",
                .symbol_name = "RASTERIZER_INPUT_AVAILABLE_SLICE3",
                .desc = "Percentage of time in which Rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext621__rasterizer_input_available_slice3__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_ext621_RASTERIZER_INPUT_AVAILABLE_SLICE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 15);
}

static bool acmgt3_ext622_RASTERIZER_INPUT_AVAILABLE_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext622_RASTERIZER_INPUT_AVAILABLE_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext622_RASTERIZER_INPUT_AVAILABLE_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext622_RASTERIZER_INPUT_AVAILABLE_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext622_RASTERIZER_TRANSACTION_OUTPUT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext622_RASTERIZER_TRANSACTION_OUTPUT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext622_RASTERIZER_TRANSACTION_OUTPUT_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext622_RASTERIZER_TRANSACTION_OUTPUT_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext622_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext622";
    metric_set->symbol_name = "Ext622";
    metric_set->hw_config_guid = "21c9f2d3-9ffa-48a0-8f77-b25bc916b889";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext622_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext622__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext622__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext622__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext622__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RASTERIZER INPUT AVAILABLE SLICE4",
                .symbol_name = "RASTERIZER_INPUT_AVAILABLE_SLICE4",
                .desc = "Percentage of time in which Rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext622__rasterizer_input_available_slice4__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_ext622_RASTERIZER_INPUT_AVAILABLE_SLICE4_availability,
            },

            {
                .name = "RASTERIZER INPUT AVAILABLE SLICE5",
                .symbol_name = "RASTERIZER_INPUT_AVAILABLE_SLICE5",
                .desc = "Percentage of time in which Rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext622__rasterizer_input_available_slice5__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_ext622_RASTERIZER_INPUT_AVAILABLE_SLICE5_availability,
            },

            {
                .name = "RASTERIZER INPUT AVAILABLE SLICE6",
                .symbol_name = "RASTERIZER_INPUT_AVAILABLE_SLICE6",
                .desc = "Percentage of time in which Rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext622__rasterizer_input_available_slice6__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_ext622_RASTERIZER_INPUT_AVAILABLE_SLICE6_availability,
            },

            {
                .name = "RASTERIZER INPUT AVAILABLE SLICE7",
                .symbol_name = "RASTERIZER_INPUT_AVAILABLE_SLICE7",
                .desc = "Percentage of time in which Rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext622__rasterizer_input_available_slice7__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_ext622_RASTERIZER_INPUT_AVAILABLE_SLICE7_availability,
            },

            {
                .name = "RASTERIZER TRANSACTION OUTPUT SLICE0",
                .symbol_name = "RASTERIZER_TRANSACTION_OUTPUT_SLICE0",
                .desc = "Number of transactions pushed from Rasterizer to the Z pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext622__rasterizer_transaction_output_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
                .availability = acmgt3_ext622_RASTERIZER_TRANSACTION_OUTPUT_SLICE0_availability,
            },

            {
                .name = "RASTERIZER TRANSACTION OUTPUT SLICE1",
                .symbol_name = "RASTERIZER_TRANSACTION_OUTPUT_SLICE1",
                .desc = "Number of transactions pushed from Rasterizer to the Z pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext622__rasterizer_transaction_output_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
                .availability = acmgt3_ext622_RASTERIZER_TRANSACTION_OUTPUT_SLICE1_availability,
            },

            {
                .name = "RASTERIZER TRANSACTION OUTPUT SLICE2",
                .symbol_name = "RASTERIZER_TRANSACTION_OUTPUT_SLICE2",
                .desc = "Number of transactions pushed from Rasterizer to the Z pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext622__rasterizer_transaction_output_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
                .availability = acmgt3_ext622_RASTERIZER_TRANSACTION_OUTPUT_SLICE2_availability,
            },

            {
                .name = "RASTERIZER TRANSACTION OUTPUT SLICE3",
                .symbol_name = "RASTERIZER_TRANSACTION_OUTPUT_SLICE3",
                .desc = "Number of transactions pushed from Rasterizer to the Z pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext622__rasterizer_transaction_output_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
                .availability = acmgt3_ext622_RASTERIZER_TRANSACTION_OUTPUT_SLICE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext623_RASTERIZER_TRANSACTION_OUTPUT_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext623_RASTERIZER_TRANSACTION_OUTPUT_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext623_RASTERIZER_TRANSACTION_OUTPUT_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext623_RASTERIZER_TRANSACTION_OUTPUT_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext623_STRIPSFAN_OBJECTS_CULL_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext623_STRIPSFAN_OBJECTS_CULL_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext623_STRIPSFAN_OBJECTS_CULL_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext623_STRIPSFAN_OBJECTS_CULL_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext623_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext623";
    metric_set->symbol_name = "Ext623";
    metric_set->hw_config_guid = "fa526e5f-fd03-4a7c-a49f-fda2ade7305c";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext623_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext623__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext623__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext623__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext623__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RASTERIZER TRANSACTION OUTPUT SLICE4",
                .symbol_name = "RASTERIZER_TRANSACTION_OUTPUT_SLICE4",
                .desc = "Number of transactions pushed from Rasterizer to the Z pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext623__rasterizer_transaction_output_slice4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
                .availability = acmgt3_ext623_RASTERIZER_TRANSACTION_OUTPUT_SLICE4_availability,
            },

            {
                .name = "RASTERIZER TRANSACTION OUTPUT SLICE5",
                .symbol_name = "RASTERIZER_TRANSACTION_OUTPUT_SLICE5",
                .desc = "Number of transactions pushed from Rasterizer to the Z pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext623__rasterizer_transaction_output_slice5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
                .availability = acmgt3_ext623_RASTERIZER_TRANSACTION_OUTPUT_SLICE5_availability,
            },

            {
                .name = "RASTERIZER TRANSACTION OUTPUT SLICE6",
                .symbol_name = "RASTERIZER_TRANSACTION_OUTPUT_SLICE6",
                .desc = "Number of transactions pushed from Rasterizer to the Z pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext623__rasterizer_transaction_output_slice6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
                .availability = acmgt3_ext623_RASTERIZER_TRANSACTION_OUTPUT_SLICE6_availability,
            },

            {
                .name = "RASTERIZER TRANSACTION OUTPUT SLICE7",
                .symbol_name = "RASTERIZER_TRANSACTION_OUTPUT_SLICE7",
                .desc = "Number of transactions pushed from Rasterizer to the Z pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext623__rasterizer_transaction_output_slice7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
                .availability = acmgt3_ext623_RASTERIZER_TRANSACTION_OUTPUT_SLICE7_availability,
            },

            {
                .name = "STRIPSFAN OBJECTS CULL SLICE0",
                .symbol_name = "STRIPSFAN_OBJECTS_CULL_SLICE0",
                .desc = "Number of simple culled objects in Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext623__stripsfan_objects_cull_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext623_STRIPSFAN_OBJECTS_CULL_SLICE0_availability,
            },

            {
                .name = "STRIPSFAN OBJECTS CULL SLICE1",
                .symbol_name = "STRIPSFAN_OBJECTS_CULL_SLICE1",
                .desc = "Number of simple culled objects in Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext623__stripsfan_objects_cull_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext623_STRIPSFAN_OBJECTS_CULL_SLICE1_availability,
            },

            {
                .name = "STRIPSFAN OBJECTS CULL SLICE2",
                .symbol_name = "STRIPSFAN_OBJECTS_CULL_SLICE2",
                .desc = "Number of simple culled objects in Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext623__stripsfan_objects_cull_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext623_STRIPSFAN_OBJECTS_CULL_SLICE2_availability,
            },

            {
                .name = "STRIPSFAN OBJECTS CULL SLICE3",
                .symbol_name = "STRIPSFAN_OBJECTS_CULL_SLICE3",
                .desc = "Number of simple culled objects in Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext623__stripsfan_objects_cull_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext623_STRIPSFAN_OBJECTS_CULL_SLICE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext624_RASTERIZER_OUTPUT_READY_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext624_RASTERIZER_OUTPUT_READY_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext624_RASTERIZER_OUTPUT_READY_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext624_RASTERIZER_OUTPUT_READY_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext624_RASTERIZER_OUTPUT_READY_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext624_RASTERIZER_OUTPUT_READY_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext624_RASTERIZER_OUTPUT_READY_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext624_RASTERIZER_OUTPUT_READY_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext624_STRIPSFAN_OBJECT_COUNT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext624_STRIPSFAN_OBJECT_COUNT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext624_STRIPSFAN_OBJECT_COUNT_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext624_STRIPSFAN_OBJECT_COUNT_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext624_STRIPSFAN_OBJECT_COUNT_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext624_STRIPSFAN_OBJECT_COUNT_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext624_STRIPSFAN_OBJECT_COUNT_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext624_STRIPSFAN_OBJECT_COUNT_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext624_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext624";
    metric_set->symbol_name = "Ext624";
    metric_set->hw_config_guid = "4fffc158-263b-4d29-afd1-1aa0dd09f1e3";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext624_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext624__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext624__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext624__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext624__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RASTERIZER OUTPUT READY SLICE0",
                .symbol_name = "RASTERIZER_OUTPUT_READY_SLICE0",
                .desc = "Percentage of time in which Rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext624__rasterizer_output_ready_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_ext624_RASTERIZER_OUTPUT_READY_SLICE0_availability,
            },

            {
                .name = "RASTERIZER OUTPUT READY SLICE1",
                .symbol_name = "RASTERIZER_OUTPUT_READY_SLICE1",
                .desc = "Percentage of time in which Rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext624__rasterizer_output_ready_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_ext624_RASTERIZER_OUTPUT_READY_SLICE1_availability,
            },

            {
                .name = "RASTERIZER OUTPUT READY SLICE2",
                .symbol_name = "RASTERIZER_OUTPUT_READY_SLICE2",
                .desc = "Percentage of time in which Rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext624__rasterizer_output_ready_slice2__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_ext624_RASTERIZER_OUTPUT_READY_SLICE2_availability,
            },

            {
                .name = "RASTERIZER OUTPUT READY SLICE3",
                .symbol_name = "RASTERIZER_OUTPUT_READY_SLICE3",
                .desc = "Percentage of time in which Rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext624__rasterizer_output_ready_slice3__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_ext624_RASTERIZER_OUTPUT_READY_SLICE3_availability,
            },

            {
                .name = "RASTERIZER OUTPUT READY SLICE4",
                .symbol_name = "RASTERIZER_OUTPUT_READY_SLICE4",
                .desc = "Percentage of time in which Rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext624__rasterizer_output_ready_slice4__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_ext624_RASTERIZER_OUTPUT_READY_SLICE4_availability,
            },

            {
                .name = "RASTERIZER OUTPUT READY SLICE5",
                .symbol_name = "RASTERIZER_OUTPUT_READY_SLICE5",
                .desc = "Percentage of time in which Rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext624__rasterizer_output_ready_slice5__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_ext624_RASTERIZER_OUTPUT_READY_SLICE5_availability,
            },

            {
                .name = "RASTERIZER OUTPUT READY SLICE6",
                .symbol_name = "RASTERIZER_OUTPUT_READY_SLICE6",
                .desc = "Percentage of time in which Rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext624__rasterizer_output_ready_slice6__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_ext624_RASTERIZER_OUTPUT_READY_SLICE6_availability,
            },

            {
                .name = "RASTERIZER OUTPUT READY SLICE7",
                .symbol_name = "RASTERIZER_OUTPUT_READY_SLICE7",
                .desc = "Percentage of time in which Rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext624__rasterizer_output_ready_slice7__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt3_ext624_RASTERIZER_OUTPUT_READY_SLICE7_availability,
            },

            {
                .name = "STRIPSFAN OBJECT COUNT SLICE0",
                .symbol_name = "STRIPSFAN_OBJECT_COUNT_SLICE0",
                .desc = "Number of objects exiting Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext624__stripsfan_object_count_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext624_STRIPSFAN_OBJECT_COUNT_SLICE0_availability,
            },

            {
                .name = "STRIPSFAN OBJECT COUNT SLICE1",
                .symbol_name = "STRIPSFAN_OBJECT_COUNT_SLICE1",
                .desc = "Number of objects exiting Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext624__stripsfan_object_count_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext624_STRIPSFAN_OBJECT_COUNT_SLICE1_availability,
            },

            {
                .name = "STRIPSFAN OBJECT COUNT SLICE2",
                .symbol_name = "STRIPSFAN_OBJECT_COUNT_SLICE2",
                .desc = "Number of objects exiting Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext624__stripsfan_object_count_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext624_STRIPSFAN_OBJECT_COUNT_SLICE2_availability,
            },

            {
                .name = "STRIPSFAN OBJECT COUNT SLICE3",
                .symbol_name = "STRIPSFAN_OBJECT_COUNT_SLICE3",
                .desc = "Number of objects exiting Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext624__stripsfan_object_count_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext624_STRIPSFAN_OBJECT_COUNT_SLICE3_availability,
            },

            {
                .name = "STRIPSFAN OBJECT COUNT SLICE4",
                .symbol_name = "STRIPSFAN_OBJECT_COUNT_SLICE4",
                .desc = "Number of objects exiting Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext624__stripsfan_object_count_slice4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext624_STRIPSFAN_OBJECT_COUNT_SLICE4_availability,
            },

            {
                .name = "STRIPSFAN OBJECT COUNT SLICE5",
                .symbol_name = "STRIPSFAN_OBJECT_COUNT_SLICE5",
                .desc = "Number of objects exiting Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext624__stripsfan_object_count_slice5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext624_STRIPSFAN_OBJECT_COUNT_SLICE5_availability,
            },

            {
                .name = "STRIPSFAN OBJECT COUNT SLICE6",
                .symbol_name = "STRIPSFAN_OBJECT_COUNT_SLICE6",
                .desc = "Number of objects exiting Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext624__stripsfan_object_count_slice6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext624_STRIPSFAN_OBJECT_COUNT_SLICE6_availability,
            },

            {
                .name = "STRIPSFAN OBJECT COUNT SLICE7",
                .symbol_name = "STRIPSFAN_OBJECT_COUNT_SLICE7",
                .desc = "Number of objects exiting Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext624__stripsfan_object_count_slice7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext624_STRIPSFAN_OBJECT_COUNT_SLICE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext625_STRIPSFAN_OBJECTS_CULL_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext625_STRIPSFAN_OBJECTS_CULL_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext625_STRIPSFAN_OBJECTS_CULL_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext625_STRIPSFAN_OBJECTS_CULL_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext625_STRIPSFAN_OUTPUT_READY_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext625_STRIPSFAN_OUTPUT_READY_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext625_STRIPSFAN_OUTPUT_READY_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext625_STRIPSFAN_OUTPUT_READY_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext625_STRIPSFAN_OUTPUT_READY_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext625_STRIPSFAN_OUTPUT_READY_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext625_STRIPSFAN_OUTPUT_READY_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext625_STRIPSFAN_OUTPUT_READY_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext625_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext625";
    metric_set->symbol_name = "Ext625";
    metric_set->hw_config_guid = "84cc7f2d-8833-4508-b075-965fc4d88ee2";
    metric_set->counters = calloc(15, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext625_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext625__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext625__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext625__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext625__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "STRIPSFAN OBJECTS CULL SLICE4",
                .symbol_name = "STRIPSFAN_OBJECTS_CULL_SLICE4",
                .desc = "Number of simple culled objects in Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext625__stripsfan_objects_cull_slice4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext625_STRIPSFAN_OBJECTS_CULL_SLICE4_availability,
            },

            {
                .name = "STRIPSFAN OBJECTS CULL SLICE5",
                .symbol_name = "STRIPSFAN_OBJECTS_CULL_SLICE5",
                .desc = "Number of simple culled objects in Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext625__stripsfan_objects_cull_slice5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext625_STRIPSFAN_OBJECTS_CULL_SLICE5_availability,
            },

            {
                .name = "STRIPSFAN OBJECTS CULL SLICE6",
                .symbol_name = "STRIPSFAN_OBJECTS_CULL_SLICE6",
                .desc = "Number of simple culled objects in Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext625__stripsfan_objects_cull_slice6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext625_STRIPSFAN_OBJECTS_CULL_SLICE6_availability,
            },

            {
                .name = "STRIPSFAN OBJECTS CULL SLICE7",
                .symbol_name = "STRIPSFAN_OBJECTS_CULL_SLICE7",
                .desc = "Number of simple culled objects in Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext625__stripsfan_objects_cull_slice7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt3_ext625_STRIPSFAN_OBJECTS_CULL_SLICE7_availability,
            },

            {
                .name = "STRIPSFAN OUTPUT READY SLICE0",
                .symbol_name = "STRIPSFAN_OUTPUT_READY_SLICE0",
                .desc = "Percentage of time in which in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext625__stripsfan_output_ready_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext625_STRIPSFAN_OUTPUT_READY_SLICE0_availability,
            },

            {
                .name = "STRIPSFAN OUTPUT READY SLICE1",
                .symbol_name = "STRIPSFAN_OUTPUT_READY_SLICE1",
                .desc = "Percentage of time in which in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext625__stripsfan_output_ready_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext625_STRIPSFAN_OUTPUT_READY_SLICE1_availability,
            },

            {
                .name = "STRIPSFAN OUTPUT READY SLICE2",
                .symbol_name = "STRIPSFAN_OUTPUT_READY_SLICE2",
                .desc = "Percentage of time in which in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext625__stripsfan_output_ready_slice2__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext625_STRIPSFAN_OUTPUT_READY_SLICE2_availability,
            },

            {
                .name = "STRIPSFAN OUTPUT READY SLICE3",
                .symbol_name = "STRIPSFAN_OUTPUT_READY_SLICE3",
                .desc = "Percentage of time in which in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext625__stripsfan_output_ready_slice3__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext625_STRIPSFAN_OUTPUT_READY_SLICE3_availability,
            },

            {
                .name = "STRIPSFAN OUTPUT READY SLICE4",
                .symbol_name = "STRIPSFAN_OUTPUT_READY_SLICE4",
                .desc = "Percentage of time in which in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext625__stripsfan_output_ready_slice4__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext625_STRIPSFAN_OUTPUT_READY_SLICE4_availability,
            },

            {
                .name = "STRIPSFAN OUTPUT READY SLICE5",
                .symbol_name = "STRIPSFAN_OUTPUT_READY_SLICE5",
                .desc = "Percentage of time in which in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext625__stripsfan_output_ready_slice5__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext625_STRIPSFAN_OUTPUT_READY_SLICE5_availability,
            },

            {
                .name = "STRIPSFAN OUTPUT READY SLICE6",
                .symbol_name = "STRIPSFAN_OUTPUT_READY_SLICE6",
                .desc = "Percentage of time in which in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext625__stripsfan_output_ready_slice6__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext625_STRIPSFAN_OUTPUT_READY_SLICE6_availability,
            },

            {
                .name = "STRIPSFAN OUTPUT READY SLICE7",
                .symbol_name = "STRIPSFAN_OUTPUT_READY_SLICE7",
                .desc = "Percentage of time in which in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext625__stripsfan_output_ready_slice7__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt3_ext625_STRIPSFAN_OUTPUT_READY_SLICE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 15);
}

static bool acmgt3_ext626_URB_CROSS_SLICE_READ_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext626_URB_READ_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext626_URB_WRITE_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext626_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext626";
    metric_set->symbol_name = "Ext626";
    metric_set->hw_config_guid = "0a6dbfd2-9294-4638-98ca-730eb9906e7f";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext626_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext626__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext626__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext626__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext626__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "URB CROSS SLICE READ SLICE0",
                .symbol_name = "URB_CROSS_SLICE_READ_SLICE0",
                .desc = "Number of URB reads occurred from cross slices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext626__urb_cross_slice_read_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt3_ext626_URB_CROSS_SLICE_READ_SLICE0_availability,
            },

            {
                .name = "URB READ SLICE0",
                .symbol_name = "URB_READ_SLICE0",
                .desc = "Number of URB reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext626__urb_read_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt3_ext626_URB_READ_SLICE0_availability,
            },

            {
                .name = "URB WRITE SLICE0",
                .symbol_name = "URB_WRITE_SLICE0",
                .desc = "Number of URB writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext626__urb_write_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt3_ext626_URB_WRITE_SLICE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext627_URB_CROSS_SLICE_READ_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext627_URB_READ_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext627_URB_WRITE_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext627_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext627";
    metric_set->symbol_name = "Ext627";
    metric_set->hw_config_guid = "59af2a26-e755-437d-9bf0-8ce5ac59c5e3";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext627_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext627__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext627__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext627__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext627__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "URB CROSS SLICE READ SLICE1",
                .symbol_name = "URB_CROSS_SLICE_READ_SLICE1",
                .desc = "Number of URB reads occurred from cross slices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext627__urb_cross_slice_read_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt3_ext627_URB_CROSS_SLICE_READ_SLICE1_availability,
            },

            {
                .name = "URB READ SLICE1",
                .symbol_name = "URB_READ_SLICE1",
                .desc = "Number of URB reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext627__urb_read_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt3_ext627_URB_READ_SLICE1_availability,
            },

            {
                .name = "URB WRITE SLICE1",
                .symbol_name = "URB_WRITE_SLICE1",
                .desc = "Number of URB writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext627__urb_write_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt3_ext627_URB_WRITE_SLICE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext628_URB_CROSS_SLICE_READ_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext628_URB_READ_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext628_URB_WRITE_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext628_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext628";
    metric_set->symbol_name = "Ext628";
    metric_set->hw_config_guid = "07ea29bd-3559-458b-8aa8-75bbdde0f619";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext628_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext628__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext628__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext628__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext628__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "URB CROSS SLICE READ SLICE2",
                .symbol_name = "URB_CROSS_SLICE_READ_SLICE2",
                .desc = "Number of URB reads occurred from cross slices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext628__urb_cross_slice_read_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt3_ext628_URB_CROSS_SLICE_READ_SLICE2_availability,
            },

            {
                .name = "URB READ SLICE2",
                .symbol_name = "URB_READ_SLICE2",
                .desc = "Number of URB reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext628__urb_read_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt3_ext628_URB_READ_SLICE2_availability,
            },

            {
                .name = "URB WRITE SLICE2",
                .symbol_name = "URB_WRITE_SLICE2",
                .desc = "Number of URB writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext628__urb_write_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt3_ext628_URB_WRITE_SLICE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext629_URB_CROSS_SLICE_READ_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext629_URB_READ_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext629_URB_WRITE_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext629_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext629";
    metric_set->symbol_name = "Ext629";
    metric_set->hw_config_guid = "c0a396af-30c1-458b-ae7f-e39cd59e6e99";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext629_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext629__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext629__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext629__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext629__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "URB CROSS SLICE READ SLICE3",
                .symbol_name = "URB_CROSS_SLICE_READ_SLICE3",
                .desc = "Number of URB reads occurred from cross slices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext629__urb_cross_slice_read_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt3_ext629_URB_CROSS_SLICE_READ_SLICE3_availability,
            },

            {
                .name = "URB READ SLICE3",
                .symbol_name = "URB_READ_SLICE3",
                .desc = "Number of URB reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext629__urb_read_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt3_ext629_URB_READ_SLICE3_availability,
            },

            {
                .name = "URB WRITE SLICE3",
                .symbol_name = "URB_WRITE_SLICE3",
                .desc = "Number of URB writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext629__urb_write_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt3_ext629_URB_WRITE_SLICE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext630_URB_CROSS_SLICE_READ_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext630_URB_READ_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext630_URB_WRITE_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext630_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext630";
    metric_set->symbol_name = "Ext630";
    metric_set->hw_config_guid = "fdbc72a7-fd96-4120-b5fb-f7340e4ef6aa";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext630_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext630__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext630__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext630__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext630__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "URB CROSS SLICE READ SLICE4",
                .symbol_name = "URB_CROSS_SLICE_READ_SLICE4",
                .desc = "Number of URB reads occurred from cross slices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext630__urb_cross_slice_read_slice4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt3_ext630_URB_CROSS_SLICE_READ_SLICE4_availability,
            },

            {
                .name = "URB READ SLICE4",
                .symbol_name = "URB_READ_SLICE4",
                .desc = "Number of URB reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext630__urb_read_slice4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt3_ext630_URB_READ_SLICE4_availability,
            },

            {
                .name = "URB WRITE SLICE4",
                .symbol_name = "URB_WRITE_SLICE4",
                .desc = "Number of URB writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext630__urb_write_slice4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt3_ext630_URB_WRITE_SLICE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext631_URB_CROSS_SLICE_READ_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext631_URB_READ_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext631_URB_WRITE_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext631_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext631";
    metric_set->symbol_name = "Ext631";
    metric_set->hw_config_guid = "8a190eb3-4bf6-456f-ba97-6ad3dd9f9041";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext631_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext631__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext631__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext631__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext631__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "URB CROSS SLICE READ SLICE5",
                .symbol_name = "URB_CROSS_SLICE_READ_SLICE5",
                .desc = "Number of URB reads occurred from cross slices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext631__urb_cross_slice_read_slice5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt3_ext631_URB_CROSS_SLICE_READ_SLICE5_availability,
            },

            {
                .name = "URB READ SLICE5",
                .symbol_name = "URB_READ_SLICE5",
                .desc = "Number of URB reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext631__urb_read_slice5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt3_ext631_URB_READ_SLICE5_availability,
            },

            {
                .name = "URB WRITE SLICE5",
                .symbol_name = "URB_WRITE_SLICE5",
                .desc = "Number of URB writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext631__urb_write_slice5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt3_ext631_URB_WRITE_SLICE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext632_URB_CROSS_SLICE_READ_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext632_URB_READ_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext632_URB_WRITE_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext632_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext632";
    metric_set->symbol_name = "Ext632";
    metric_set->hw_config_guid = "690cf267-acc5-4f2a-a9d9-e424d39d0085";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext632_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext632__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext632__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext632__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext632__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "URB CROSS SLICE READ SLICE6",
                .symbol_name = "URB_CROSS_SLICE_READ_SLICE6",
                .desc = "Number of URB reads occurred from cross slices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext632__urb_cross_slice_read_slice6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt3_ext632_URB_CROSS_SLICE_READ_SLICE6_availability,
            },

            {
                .name = "URB READ SLICE6",
                .symbol_name = "URB_READ_SLICE6",
                .desc = "Number of URB reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext632__urb_read_slice6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt3_ext632_URB_READ_SLICE6_availability,
            },

            {
                .name = "URB WRITE SLICE6",
                .symbol_name = "URB_WRITE_SLICE6",
                .desc = "Number of URB writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext632__urb_write_slice6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt3_ext632_URB_WRITE_SLICE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext633_URB_CROSS_SLICE_READ_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext633_URB_READ_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext633_URB_WRITE_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext633_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext633";
    metric_set->symbol_name = "Ext633";
    metric_set->hw_config_guid = "7dfd1792-f14e-47cb-b3c3-969deb04e830";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext633_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext633__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext633__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext633__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext633__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "URB CROSS SLICE READ SLICE7",
                .symbol_name = "URB_CROSS_SLICE_READ_SLICE7",
                .desc = "Number of URB reads occurred from cross slices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext633__urb_cross_slice_read_slice7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt3_ext633_URB_CROSS_SLICE_READ_SLICE7_availability,
            },

            {
                .name = "URB READ SLICE7",
                .symbol_name = "URB_READ_SLICE7",
                .desc = "Number of URB reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext633__urb_read_slice7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt3_ext633_URB_READ_SLICE7_availability,
            },

            {
                .name = "URB WRITE SLICE7",
                .symbol_name = "URB_WRITE_SLICE7",
                .desc = "Number of URB writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext633__urb_write_slice7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt3_ext633_URB_WRITE_SLICE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}


static void
acmgt3_add_ext634_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext634";
    metric_set->symbol_name = "Ext634";
    metric_set->hw_config_guid = "255faebf-ef8b-4fa1-9d3c-d82b46a8a9f1";
    metric_set->counters = calloc(9, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext634_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext634__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext634__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE BUSY",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_BUSY",
                .desc = "Percentage of time in which there is a context loaded and active on the compute queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext634__command_parser_compute_engine_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE BUSY CCS0",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_BUSY_CCS0",
                .desc = "Percentage of time in which there is a context loaded and active on the compute queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext634__command_parser_compute_engine_busy_ccs0__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE BUSY CCS1",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_BUSY_CCS1",
                .desc = "Percentage of time in which there is a context loaded and active on the compute queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext634__command_parser_compute_engine_busy_ccs1__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE BUSY CCS2",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_BUSY_CCS2",
                .desc = "Percentage of time in which there is a context loaded and active on the compute queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext634__command_parser_compute_engine_busy_ccs2__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE BUSY CCS3",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_BUSY_CCS3",
                .desc = "Percentage of time in which there is a context loaded and active on the compute queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext634__command_parser_compute_engine_busy_ccs3__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER RENDER ENGINE BUSY",
                .symbol_name = "COMMAND_PARSER_RENDER_ENGINE_BUSY",
                .desc = "Percentage of time in which there is a context loaded and active on the 3D queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext634__command_parser_render_engine_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext634__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext634__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 9);
}


static void
acmgt3_add_ext635_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext635";
    metric_set->symbol_name = "Ext635";
    metric_set->hw_config_guid = "53827355-f253-40a1-b02d-b07b591aa394";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext635_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext635__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext635__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "COMMAND PARSER COPY ENGINE BUSY",
                .symbol_name = "COMMAND_PARSER_COPY_ENGINE_BUSY",
                .desc = "Percentage of time in which there is a context loaded and active on the copy queue.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext635__command_parser_copy_engine_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER VIDEO ENGINE BUSY",
                .symbol_name = "COMMAND_PARSER_VIDEO_ENGINE_BUSY",
                .desc = "Percentage of time in which there is a context loaded and active on the media queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext635__command_parser_video_engine_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER VIDEO ENGINE BUSY VDBOX0",
                .symbol_name = "COMMAND_PARSER_VIDEO_ENGINE_BUSY_VDBOX0",
                .desc = "Percentage of time in which there is a context loaded and active on the media queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext635__command_parser_video_engine_busy_vdbox0__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER VIDEO ENGINE BUSY VDBOX1",
                .symbol_name = "COMMAND_PARSER_VIDEO_ENGINE_BUSY_VDBOX1",
                .desc = "Percentage of time in which there is a context loaded and active on the media queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext635__command_parser_video_engine_busy_vdbox1__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER VIDEO ENHANCEMENT ENGINE BUSY",
                .symbol_name = "COMMAND_PARSER_VIDEO_ENHANCEMENT_ENGINE_BUSY",
                .desc = "Percentage of time in which there is a context loaded and active on the video enhancement queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext635__command_parser_video_enhancement_engine_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER VIDEO ENHANCEMENT ENGINE BUSY VEBOX0",
                .symbol_name = "COMMAND_PARSER_VIDEO_ENHANCEMENT_ENGINE_BUSY_VEBOX0",
                .desc = "Percentage of time in which there is a context loaded and active on the video enhancement queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext635__command_parser_video_enhancement_engine_busy_vebox0__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER VIDEO ENHANCEMENT ENGINE BUSY VEBOX1",
                .symbol_name = "COMMAND_PARSER_VIDEO_ENHANCEMENT_ENGINE_BUSY_VEBOX1",
                .desc = "Percentage of time in which there is a context loaded and active on the video enhancement queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext635__command_parser_video_enhancement_engine_busy_vebox1__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext635__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext635__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}


static void
acmgt3_add_ext636_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext636";
    metric_set->symbol_name = "Ext636";
    metric_set->hw_config_guid = "1902b796-e21e-40b4-8132-0fd73e341735";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext636_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext636__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext636__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_DISPATCH_KERNEL_COUNT",
                .desc = "Number of compute walker commands parsed on the compute engine",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext636__command_parser_compute_engine_dispatch_kernel_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS0",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_DISPATCH_KERNEL_COUNT_CCS0",
                .desc = "Number of compute walker commands parsed on the compute engine",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext636__command_parser_compute_engine_dispatch_kernel_count_ccs0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS1",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_DISPATCH_KERNEL_COUNT_CCS1",
                .desc = "Number of compute walker commands parsed on the compute engine",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext636__command_parser_compute_engine_dispatch_kernel_count_ccs1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS2",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_DISPATCH_KERNEL_COUNT_CCS2",
                .desc = "Number of compute walker commands parsed on the compute engine",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext636__command_parser_compute_engine_dispatch_kernel_count_ccs2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS3",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_DISPATCH_KERNEL_COUNT_CCS3",
                .desc = "Number of compute walker commands parsed on the compute engine",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext636__command_parser_compute_engine_dispatch_kernel_count_ccs3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER FLUSH COUNT",
                .symbol_name = "COMMAND_PARSER_FLUSH_COUNT",
                .desc = "Number of Stalling flushes at the top of the pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext636__command_parser_flush_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER RENDER ENGINE DISPATCH KERNEL COUNT",
                .symbol_name = "COMMAND_PARSER_RENDER_ENGINE_DISPATCH_KERNEL_COUNT",
                .desc = "Number of compute walker commands parsed on the 3D engine",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext636__command_parser_render_engine_dispatch_kernel_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER RENDER ENGINE DRAW COUNT",
                .symbol_name = "COMMAND_PARSER_RENDER_ENGINE_DRAW_COUNT",
                .desc = "Number of DRAW and MESH commands parsed on the 3D engine",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext636__command_parser_render_engine_draw_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext636__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext636__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext637_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext637_XVE_STALL_ALUWR_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext637_XVE_STALL_BARRIER_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext637_XVE_STALL_INSTFETCH_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext637_XVE_STALL_OTHER_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext637_XVE_STALL_SBID_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext637_XVE_STALL_SENDWR_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext637_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext637";
    metric_set->symbol_name = "Ext637";
    metric_set->hw_config_guid = "7ec62259-93dc-464b-99ea-629737cf9861";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext637_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext637__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext637__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext637__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext637__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext637__xve_shared_function_access_hold_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext637_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE0_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext637__xve_stall_aluwr_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext637_XVE_STALL_ALUWR_XECORE0_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext637__xve_stall_barrier_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext637_XVE_STALL_BARRIER_XECORE0_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext637__xve_stall_instfetch_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext637_XVE_STALL_INSTFETCH_XECORE0_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext637__xve_stall_other_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext637_XVE_STALL_OTHER_XECORE0_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext637__xve_stall_sbid_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext637_XVE_STALL_SBID_XECORE0_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext637__xve_stall_sendwr_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext637_XVE_STALL_SENDWR_XECORE0_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext638_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext638_XVE_STALL_ALUWR_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext638_XVE_STALL_BARRIER_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext638_XVE_STALL_INSTFETCH_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext638_XVE_STALL_OTHER_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext638_XVE_STALL_SBID_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext638_XVE_STALL_SENDWR_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext638_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext638";
    metric_set->symbol_name = "Ext638";
    metric_set->hw_config_guid = "32b54940-c66d-4636-b61a-a8f6b46d32d0";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext638_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext638__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext638__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext638__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext638__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext638__xve_shared_function_access_hold_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext638_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE1_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext638__xve_stall_aluwr_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext638_XVE_STALL_ALUWR_XECORE1_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext638__xve_stall_barrier_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext638_XVE_STALL_BARRIER_XECORE1_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext638__xve_stall_instfetch_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext638_XVE_STALL_INSTFETCH_XECORE1_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext638__xve_stall_other_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext638_XVE_STALL_OTHER_XECORE1_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext638__xve_stall_sbid_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext638_XVE_STALL_SBID_XECORE1_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext638__xve_stall_sendwr_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext638_XVE_STALL_SENDWR_XECORE1_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext639_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext639_XVE_STALL_ALUWR_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext639_XVE_STALL_BARRIER_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext639_XVE_STALL_INSTFETCH_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext639_XVE_STALL_OTHER_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext639_XVE_STALL_SBID_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext639_XVE_STALL_SENDWR_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext639_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext639";
    metric_set->symbol_name = "Ext639";
    metric_set->hw_config_guid = "10e959bd-ef25-44ff-9d2b-b8c773e6087c";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext639_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext639__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext639__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext639__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext639__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext639__xve_shared_function_access_hold_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext639_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE2_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext639__xve_stall_aluwr_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext639_XVE_STALL_ALUWR_XECORE2_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext639__xve_stall_barrier_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext639_XVE_STALL_BARRIER_XECORE2_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext639__xve_stall_instfetch_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext639_XVE_STALL_INSTFETCH_XECORE2_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext639__xve_stall_other_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext639_XVE_STALL_OTHER_XECORE2_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext639__xve_stall_sbid_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext639_XVE_STALL_SBID_XECORE2_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext639__xve_stall_sendwr_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext639_XVE_STALL_SENDWR_XECORE2_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext640_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext640_XVE_STALL_ALUWR_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext640_XVE_STALL_BARRIER_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext640_XVE_STALL_INSTFETCH_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext640_XVE_STALL_OTHER_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext640_XVE_STALL_SBID_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext640_XVE_STALL_SENDWR_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext640_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext640";
    metric_set->symbol_name = "Ext640";
    metric_set->hw_config_guid = "371d7a11-3eef-4da8-88e5-fd25d85d10d6";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext640_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext640__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext640__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext640__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext640__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext640__xve_shared_function_access_hold_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext640_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE3_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext640__xve_stall_aluwr_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext640_XVE_STALL_ALUWR_XECORE3_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext640__xve_stall_barrier_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext640_XVE_STALL_BARRIER_XECORE3_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext640__xve_stall_instfetch_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext640_XVE_STALL_INSTFETCH_XECORE3_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext640__xve_stall_other_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext640_XVE_STALL_OTHER_XECORE3_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext640__xve_stall_sbid_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext640_XVE_STALL_SBID_XECORE3_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext640__xve_stall_sendwr_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext640_XVE_STALL_SENDWR_XECORE3_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext641_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext641_XVE_STALL_ALUWR_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext641_XVE_STALL_BARRIER_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext641_XVE_STALL_INSTFETCH_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext641_XVE_STALL_OTHER_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext641_XVE_STALL_SBID_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext641_XVE_STALL_SENDWR_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext641_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext641";
    metric_set->symbol_name = "Ext641";
    metric_set->hw_config_guid = "a5be5bd5-b23d-48bb-b56b-ae9fd49acca4";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext641_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext641__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext641__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext641__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext641__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext641__xve_shared_function_access_hold_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext641_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE4_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext641__xve_stall_aluwr_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext641_XVE_STALL_ALUWR_XECORE4_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext641__xve_stall_barrier_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext641_XVE_STALL_BARRIER_XECORE4_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext641__xve_stall_instfetch_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext641_XVE_STALL_INSTFETCH_XECORE4_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext641__xve_stall_other_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext641_XVE_STALL_OTHER_XECORE4_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext641__xve_stall_sbid_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext641_XVE_STALL_SBID_XECORE4_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext641__xve_stall_sendwr_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext641_XVE_STALL_SENDWR_XECORE4_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext642_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext642_XVE_STALL_ALUWR_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext642_XVE_STALL_BARRIER_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext642_XVE_STALL_INSTFETCH_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext642_XVE_STALL_OTHER_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext642_XVE_STALL_SBID_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext642_XVE_STALL_SENDWR_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext642_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext642";
    metric_set->symbol_name = "Ext642";
    metric_set->hw_config_guid = "dd277896-494e-4db9-8da4-9efb89846b6b";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext642_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext642__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext642__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext642__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext642__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext642__xve_shared_function_access_hold_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext642_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE5_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext642__xve_stall_aluwr_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext642_XVE_STALL_ALUWR_XECORE5_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext642__xve_stall_barrier_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext642_XVE_STALL_BARRIER_XECORE5_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext642__xve_stall_instfetch_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext642_XVE_STALL_INSTFETCH_XECORE5_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext642__xve_stall_other_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext642_XVE_STALL_OTHER_XECORE5_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext642__xve_stall_sbid_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext642_XVE_STALL_SBID_XECORE5_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext642__xve_stall_sendwr_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext642_XVE_STALL_SENDWR_XECORE5_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext643_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext643_XVE_STALL_ALUWR_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext643_XVE_STALL_BARRIER_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext643_XVE_STALL_INSTFETCH_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext643_XVE_STALL_OTHER_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext643_XVE_STALL_SBID_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext643_XVE_STALL_SENDWR_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext643_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext643";
    metric_set->symbol_name = "Ext643";
    metric_set->hw_config_guid = "4a13f620-9b8f-41e8-9189-0712948bc7ed";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext643_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext643__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext643__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext643__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext643__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext643__xve_shared_function_access_hold_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext643_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE6_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext643__xve_stall_aluwr_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext643_XVE_STALL_ALUWR_XECORE6_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext643__xve_stall_barrier_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext643_XVE_STALL_BARRIER_XECORE6_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext643__xve_stall_instfetch_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext643_XVE_STALL_INSTFETCH_XECORE6_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext643__xve_stall_other_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext643_XVE_STALL_OTHER_XECORE6_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext643__xve_stall_sbid_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext643_XVE_STALL_SBID_XECORE6_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext643__xve_stall_sendwr_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext643_XVE_STALL_SENDWR_XECORE6_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext644_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext644_XVE_STALL_ALUWR_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext644_XVE_STALL_BARRIER_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext644_XVE_STALL_INSTFETCH_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext644_XVE_STALL_OTHER_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext644_XVE_STALL_SBID_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext644_XVE_STALL_SENDWR_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext644_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext644";
    metric_set->symbol_name = "Ext644";
    metric_set->hw_config_guid = "c6b5a675-c1a9-4e9c-bf68-af0b1ad8dc08";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext644_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext644__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext644__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext644__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext644__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext644__xve_shared_function_access_hold_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext644_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE7_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext644__xve_stall_aluwr_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext644_XVE_STALL_ALUWR_XECORE7_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext644__xve_stall_barrier_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext644_XVE_STALL_BARRIER_XECORE7_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext644__xve_stall_instfetch_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext644_XVE_STALL_INSTFETCH_XECORE7_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext644__xve_stall_other_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext644_XVE_STALL_OTHER_XECORE7_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext644__xve_stall_sbid_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext644_XVE_STALL_SBID_XECORE7_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext644__xve_stall_sendwr_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext644_XVE_STALL_SENDWR_XECORE7_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext645_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE8_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext645_XVE_STALL_ALUWR_XECORE8_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext645_XVE_STALL_BARRIER_XECORE8_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext645_XVE_STALL_INSTFETCH_XECORE8_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext645_XVE_STALL_OTHER_XECORE8_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext645_XVE_STALL_SBID_XECORE8_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext645_XVE_STALL_SENDWR_XECORE8_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext645_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext645";
    metric_set->symbol_name = "Ext645";
    metric_set->hw_config_guid = "81a0ff81-482c-4fea-93c8-f2ad4cc6a42e";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext645_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext645__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext645__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext645__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext645__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE8 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE8_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext645__xve_shared_function_access_hold_xecore8_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext645_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE8_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE8 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE8_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext645__xve_stall_aluwr_xecore8_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext645_XVE_STALL_ALUWR_XECORE8_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE8 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE8_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext645__xve_stall_barrier_xecore8_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext645_XVE_STALL_BARRIER_XECORE8_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE8 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE8_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext645__xve_stall_instfetch_xecore8_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext645_XVE_STALL_INSTFETCH_XECORE8_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE8 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE8_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext645__xve_stall_other_xecore8_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext645_XVE_STALL_OTHER_XECORE8_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE8 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE8_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext645__xve_stall_sbid_xecore8_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext645_XVE_STALL_SBID_XECORE8_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE8 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE8_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext645__xve_stall_sendwr_xecore8_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext645_XVE_STALL_SENDWR_XECORE8_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext646_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE9_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext646_XVE_STALL_ALUWR_XECORE9_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext646_XVE_STALL_BARRIER_XECORE9_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext646_XVE_STALL_INSTFETCH_XECORE9_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext646_XVE_STALL_OTHER_XECORE9_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext646_XVE_STALL_SBID_XECORE9_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext646_XVE_STALL_SENDWR_XECORE9_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext646_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext646";
    metric_set->symbol_name = "Ext646";
    metric_set->hw_config_guid = "51ef51ba-0cec-4c46-8cf9-65b6b366a20f";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext646_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext646__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext646__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext646__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext646__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE9 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE9_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext646__xve_shared_function_access_hold_xecore9_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext646_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE9_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE9 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE9_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext646__xve_stall_aluwr_xecore9_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext646_XVE_STALL_ALUWR_XECORE9_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE9 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE9_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext646__xve_stall_barrier_xecore9_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext646_XVE_STALL_BARRIER_XECORE9_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE9 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE9_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext646__xve_stall_instfetch_xecore9_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext646_XVE_STALL_INSTFETCH_XECORE9_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE9 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE9_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext646__xve_stall_other_xecore9_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext646_XVE_STALL_OTHER_XECORE9_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE9 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE9_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext646__xve_stall_sbid_xecore9_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext646_XVE_STALL_SBID_XECORE9_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE9 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE9_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext646__xve_stall_sendwr_xecore9_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext646_XVE_STALL_SENDWR_XECORE9_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext647_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE10_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext647_XVE_STALL_ALUWR_XECORE10_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext647_XVE_STALL_BARRIER_XECORE10_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext647_XVE_STALL_INSTFETCH_XECORE10_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext647_XVE_STALL_OTHER_XECORE10_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext647_XVE_STALL_SBID_XECORE10_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext647_XVE_STALL_SENDWR_XECORE10_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext647_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext647";
    metric_set->symbol_name = "Ext647";
    metric_set->hw_config_guid = "80b23cbe-5ff0-49aa-9591-7f63c958e510";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext647_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext647__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext647__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext647__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext647__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE10 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE10_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext647__xve_shared_function_access_hold_xecore10_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext647_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE10_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE10 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE10_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext647__xve_stall_aluwr_xecore10_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext647_XVE_STALL_ALUWR_XECORE10_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE10 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE10_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext647__xve_stall_barrier_xecore10_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext647_XVE_STALL_BARRIER_XECORE10_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE10 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE10_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext647__xve_stall_instfetch_xecore10_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext647_XVE_STALL_INSTFETCH_XECORE10_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE10 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE10_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext647__xve_stall_other_xecore10_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext647_XVE_STALL_OTHER_XECORE10_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE10 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE10_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext647__xve_stall_sbid_xecore10_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext647_XVE_STALL_SBID_XECORE10_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE10 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE10_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext647__xve_stall_sendwr_xecore10_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext647_XVE_STALL_SENDWR_XECORE10_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext648_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE11_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext648_XVE_STALL_ALUWR_XECORE11_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext648_XVE_STALL_BARRIER_XECORE11_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext648_XVE_STALL_INSTFETCH_XECORE11_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext648_XVE_STALL_OTHER_XECORE11_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext648_XVE_STALL_SBID_XECORE11_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext648_XVE_STALL_SENDWR_XECORE11_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext648_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext648";
    metric_set->symbol_name = "Ext648";
    metric_set->hw_config_guid = "c8baa82f-efca-44de-9464-75f7653c1ecd";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext648_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext648__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext648__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext648__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext648__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE11 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE11_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext648__xve_shared_function_access_hold_xecore11_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext648_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE11_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE11 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE11_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext648__xve_stall_aluwr_xecore11_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext648_XVE_STALL_ALUWR_XECORE11_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE11 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE11_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext648__xve_stall_barrier_xecore11_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext648_XVE_STALL_BARRIER_XECORE11_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE11 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE11_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext648__xve_stall_instfetch_xecore11_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext648_XVE_STALL_INSTFETCH_XECORE11_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE11 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE11_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext648__xve_stall_other_xecore11_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext648_XVE_STALL_OTHER_XECORE11_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE11 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE11_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext648__xve_stall_sbid_xecore11_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext648_XVE_STALL_SBID_XECORE11_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE11 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE11_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext648__xve_stall_sendwr_xecore11_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext648_XVE_STALL_SENDWR_XECORE11_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext649_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE12_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext649_XVE_STALL_ALUWR_XECORE12_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext649_XVE_STALL_BARRIER_XECORE12_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext649_XVE_STALL_INSTFETCH_XECORE12_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext649_XVE_STALL_OTHER_XECORE12_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext649_XVE_STALL_SBID_XECORE12_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext649_XVE_STALL_SENDWR_XECORE12_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext649_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext649";
    metric_set->symbol_name = "Ext649";
    metric_set->hw_config_guid = "417cd1e9-b680-4389-99a0-d11bd6076465";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext649_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext649__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext649__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext649__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext649__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE12 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE12_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext649__xve_shared_function_access_hold_xecore12_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext649_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE12_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE12 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE12_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext649__xve_stall_aluwr_xecore12_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext649_XVE_STALL_ALUWR_XECORE12_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE12 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE12_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext649__xve_stall_barrier_xecore12_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext649_XVE_STALL_BARRIER_XECORE12_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE12 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE12_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext649__xve_stall_instfetch_xecore12_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext649_XVE_STALL_INSTFETCH_XECORE12_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE12 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE12_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext649__xve_stall_other_xecore12_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext649_XVE_STALL_OTHER_XECORE12_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE12 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE12_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext649__xve_stall_sbid_xecore12_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext649_XVE_STALL_SBID_XECORE12_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE12 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE12_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext649__xve_stall_sendwr_xecore12_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext649_XVE_STALL_SENDWR_XECORE12_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext650_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE13_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext650_XVE_STALL_ALUWR_XECORE13_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext650_XVE_STALL_BARRIER_XECORE13_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext650_XVE_STALL_INSTFETCH_XECORE13_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext650_XVE_STALL_OTHER_XECORE13_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext650_XVE_STALL_SBID_XECORE13_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext650_XVE_STALL_SENDWR_XECORE13_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext650_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext650";
    metric_set->symbol_name = "Ext650";
    metric_set->hw_config_guid = "5513c6b2-2b34-43f9-aa42-66ec99231838";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext650_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext650__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext650__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext650__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext650__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE13 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE13_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext650__xve_shared_function_access_hold_xecore13_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext650_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE13_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE13 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE13_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext650__xve_stall_aluwr_xecore13_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext650_XVE_STALL_ALUWR_XECORE13_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE13 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE13_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext650__xve_stall_barrier_xecore13_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext650_XVE_STALL_BARRIER_XECORE13_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE13 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE13_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext650__xve_stall_instfetch_xecore13_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext650_XVE_STALL_INSTFETCH_XECORE13_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE13 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE13_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext650__xve_stall_other_xecore13_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext650_XVE_STALL_OTHER_XECORE13_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE13 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE13_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext650__xve_stall_sbid_xecore13_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext650_XVE_STALL_SBID_XECORE13_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE13 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE13_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext650__xve_stall_sendwr_xecore13_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext650_XVE_STALL_SENDWR_XECORE13_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext651_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE14_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext651_XVE_STALL_ALUWR_XECORE14_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext651_XVE_STALL_BARRIER_XECORE14_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext651_XVE_STALL_INSTFETCH_XECORE14_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext651_XVE_STALL_OTHER_XECORE14_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext651_XVE_STALL_SBID_XECORE14_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext651_XVE_STALL_SENDWR_XECORE14_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext651_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext651";
    metric_set->symbol_name = "Ext651";
    metric_set->hw_config_guid = "e219ac69-3ea7-4ef4-90fc-43da93940404";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext651_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext651__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext651__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext651__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext651__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE14 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE14_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext651__xve_shared_function_access_hold_xecore14_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext651_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE14_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE14 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE14_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext651__xve_stall_aluwr_xecore14_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext651_XVE_STALL_ALUWR_XECORE14_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE14 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE14_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext651__xve_stall_barrier_xecore14_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext651_XVE_STALL_BARRIER_XECORE14_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE14 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE14_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext651__xve_stall_instfetch_xecore14_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext651_XVE_STALL_INSTFETCH_XECORE14_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE14 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE14_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext651__xve_stall_other_xecore14_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext651_XVE_STALL_OTHER_XECORE14_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE14 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE14_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext651__xve_stall_sbid_xecore14_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext651_XVE_STALL_SBID_XECORE14_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE14 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE14_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext651__xve_stall_sendwr_xecore14_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext651_XVE_STALL_SENDWR_XECORE14_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext652_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE15_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext652_XVE_STALL_ALUWR_XECORE15_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext652_XVE_STALL_BARRIER_XECORE15_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext652_XVE_STALL_INSTFETCH_XECORE15_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext652_XVE_STALL_OTHER_XECORE15_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext652_XVE_STALL_SBID_XECORE15_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext652_XVE_STALL_SENDWR_XECORE15_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext652_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext652";
    metric_set->symbol_name = "Ext652";
    metric_set->hw_config_guid = "bd0f78e6-755f-495f-a530-2181a36e202b";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext652_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext652__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext652__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext652__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext652__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE15 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE15_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext652__xve_shared_function_access_hold_xecore15_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext652_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE15_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE15 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE15_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext652__xve_stall_aluwr_xecore15_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext652_XVE_STALL_ALUWR_XECORE15_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE15 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE15_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext652__xve_stall_barrier_xecore15_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext652_XVE_STALL_BARRIER_XECORE15_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE15 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE15_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext652__xve_stall_instfetch_xecore15_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext652_XVE_STALL_INSTFETCH_XECORE15_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE15 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE15_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext652__xve_stall_other_xecore15_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext652_XVE_STALL_OTHER_XECORE15_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE15 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE15_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext652__xve_stall_sbid_xecore15_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext652_XVE_STALL_SBID_XECORE15_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE15 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE15_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext652__xve_stall_sendwr_xecore15_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext652_XVE_STALL_SENDWR_XECORE15_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext653_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE16_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext653_XVE_STALL_ALUWR_XECORE16_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext653_XVE_STALL_BARRIER_XECORE16_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext653_XVE_STALL_INSTFETCH_XECORE16_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext653_XVE_STALL_OTHER_XECORE16_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext653_XVE_STALL_SBID_XECORE16_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext653_XVE_STALL_SENDWR_XECORE16_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext653_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext653";
    metric_set->symbol_name = "Ext653";
    metric_set->hw_config_guid = "ee687e64-5d49-4f00-8487-7f29ce84112b";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext653_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext653__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext653__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext653__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext653__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE16 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE16_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext653__xve_shared_function_access_hold_xecore16_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext653_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE16_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE16 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE16_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext653__xve_stall_aluwr_xecore16_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext653_XVE_STALL_ALUWR_XECORE16_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE16 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE16_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext653__xve_stall_barrier_xecore16_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext653_XVE_STALL_BARRIER_XECORE16_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE16 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE16_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext653__xve_stall_instfetch_xecore16_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext653_XVE_STALL_INSTFETCH_XECORE16_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE16 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE16_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext653__xve_stall_other_xecore16_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext653_XVE_STALL_OTHER_XECORE16_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE16 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE16_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext653__xve_stall_sbid_xecore16_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext653_XVE_STALL_SBID_XECORE16_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE16 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE16_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext653__xve_stall_sendwr_xecore16_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext653_XVE_STALL_SENDWR_XECORE16_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext654_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE17_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext654_XVE_STALL_ALUWR_XECORE17_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext654_XVE_STALL_BARRIER_XECORE17_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext654_XVE_STALL_INSTFETCH_XECORE17_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext654_XVE_STALL_OTHER_XECORE17_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext654_XVE_STALL_SBID_XECORE17_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext654_XVE_STALL_SENDWR_XECORE17_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext654_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext654";
    metric_set->symbol_name = "Ext654";
    metric_set->hw_config_guid = "7fa4182a-6679-43a8-863d-20bf117c2f6e";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext654_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext654__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext654__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext654__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext654__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE17 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE17_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext654__xve_shared_function_access_hold_xecore17_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext654_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE17_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE17 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE17_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext654__xve_stall_aluwr_xecore17_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext654_XVE_STALL_ALUWR_XECORE17_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE17 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE17_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext654__xve_stall_barrier_xecore17_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext654_XVE_STALL_BARRIER_XECORE17_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE17 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE17_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext654__xve_stall_instfetch_xecore17_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext654_XVE_STALL_INSTFETCH_XECORE17_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE17 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE17_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext654__xve_stall_other_xecore17_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext654_XVE_STALL_OTHER_XECORE17_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE17 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE17_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext654__xve_stall_sbid_xecore17_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext654_XVE_STALL_SBID_XECORE17_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE17 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE17_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext654__xve_stall_sendwr_xecore17_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext654_XVE_STALL_SENDWR_XECORE17_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext655_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE18_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext655_XVE_STALL_ALUWR_XECORE18_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext655_XVE_STALL_BARRIER_XECORE18_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext655_XVE_STALL_INSTFETCH_XECORE18_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext655_XVE_STALL_OTHER_XECORE18_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext655_XVE_STALL_SBID_XECORE18_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext655_XVE_STALL_SENDWR_XECORE18_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext655_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext655";
    metric_set->symbol_name = "Ext655";
    metric_set->hw_config_guid = "4776e4a6-e322-4a93-8492-f9e5c7ae25a9";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext655_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext655__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext655__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext655__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext655__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE18 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE18_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext655__xve_shared_function_access_hold_xecore18_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext655_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE18_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE18 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE18_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext655__xve_stall_aluwr_xecore18_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext655_XVE_STALL_ALUWR_XECORE18_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE18 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE18_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext655__xve_stall_barrier_xecore18_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext655_XVE_STALL_BARRIER_XECORE18_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE18 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE18_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext655__xve_stall_instfetch_xecore18_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext655_XVE_STALL_INSTFETCH_XECORE18_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE18 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE18_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext655__xve_stall_other_xecore18_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext655_XVE_STALL_OTHER_XECORE18_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE18 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE18_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext655__xve_stall_sbid_xecore18_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext655_XVE_STALL_SBID_XECORE18_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE18 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE18_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext655__xve_stall_sendwr_xecore18_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext655_XVE_STALL_SENDWR_XECORE18_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext656_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE19_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext656_XVE_STALL_ALUWR_XECORE19_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext656_XVE_STALL_BARRIER_XECORE19_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext656_XVE_STALL_INSTFETCH_XECORE19_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext656_XVE_STALL_OTHER_XECORE19_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext656_XVE_STALL_SBID_XECORE19_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext656_XVE_STALL_SENDWR_XECORE19_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext656_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext656";
    metric_set->symbol_name = "Ext656";
    metric_set->hw_config_guid = "7e54fcd8-7d05-4a6e-a564-77da9ee3d948";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext656_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext656__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext656__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext656__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext656__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE19 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE19_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext656__xve_shared_function_access_hold_xecore19_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext656_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE19_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE19 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE19_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext656__xve_stall_aluwr_xecore19_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext656_XVE_STALL_ALUWR_XECORE19_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE19 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE19_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext656__xve_stall_barrier_xecore19_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext656_XVE_STALL_BARRIER_XECORE19_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE19 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE19_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext656__xve_stall_instfetch_xecore19_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext656_XVE_STALL_INSTFETCH_XECORE19_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE19 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE19_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext656__xve_stall_other_xecore19_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext656_XVE_STALL_OTHER_XECORE19_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE19 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE19_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext656__xve_stall_sbid_xecore19_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext656_XVE_STALL_SBID_XECORE19_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE19 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE19_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext656__xve_stall_sendwr_xecore19_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext656_XVE_STALL_SENDWR_XECORE19_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext657_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE20_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext657_XVE_STALL_ALUWR_XECORE20_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext657_XVE_STALL_BARRIER_XECORE20_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext657_XVE_STALL_INSTFETCH_XECORE20_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext657_XVE_STALL_OTHER_XECORE20_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext657_XVE_STALL_SBID_XECORE20_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext657_XVE_STALL_SENDWR_XECORE20_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext657_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext657";
    metric_set->symbol_name = "Ext657";
    metric_set->hw_config_guid = "616a2406-05c9-412d-a3aa-a524acd66aa0";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext657_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext657__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext657__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext657__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext657__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE20 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE20_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext657__xve_shared_function_access_hold_xecore20_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext657_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE20_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE20 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE20_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext657__xve_stall_aluwr_xecore20_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext657_XVE_STALL_ALUWR_XECORE20_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE20 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE20_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext657__xve_stall_barrier_xecore20_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext657_XVE_STALL_BARRIER_XECORE20_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE20 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE20_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext657__xve_stall_instfetch_xecore20_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext657_XVE_STALL_INSTFETCH_XECORE20_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE20 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE20_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext657__xve_stall_other_xecore20_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext657_XVE_STALL_OTHER_XECORE20_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE20 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE20_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext657__xve_stall_sbid_xecore20_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext657_XVE_STALL_SBID_XECORE20_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE20 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE20_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext657__xve_stall_sendwr_xecore20_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext657_XVE_STALL_SENDWR_XECORE20_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext658_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE21_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext658_XVE_STALL_ALUWR_XECORE21_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext658_XVE_STALL_BARRIER_XECORE21_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext658_XVE_STALL_INSTFETCH_XECORE21_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext658_XVE_STALL_OTHER_XECORE21_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext658_XVE_STALL_SBID_XECORE21_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext658_XVE_STALL_SENDWR_XECORE21_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext658_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext658";
    metric_set->symbol_name = "Ext658";
    metric_set->hw_config_guid = "0902fe2b-216e-4634-ae60-349382ded3ce";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext658_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext658__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext658__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext658__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext658__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE21 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE21_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext658__xve_shared_function_access_hold_xecore21_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext658_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE21_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE21 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE21_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext658__xve_stall_aluwr_xecore21_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext658_XVE_STALL_ALUWR_XECORE21_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE21 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE21_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext658__xve_stall_barrier_xecore21_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext658_XVE_STALL_BARRIER_XECORE21_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE21 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE21_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext658__xve_stall_instfetch_xecore21_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext658_XVE_STALL_INSTFETCH_XECORE21_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE21 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE21_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext658__xve_stall_other_xecore21_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext658_XVE_STALL_OTHER_XECORE21_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE21 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE21_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext658__xve_stall_sbid_xecore21_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext658_XVE_STALL_SBID_XECORE21_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE21 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE21_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext658__xve_stall_sendwr_xecore21_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext658_XVE_STALL_SENDWR_XECORE21_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext659_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE22_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext659_XVE_STALL_ALUWR_XECORE22_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext659_XVE_STALL_BARRIER_XECORE22_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext659_XVE_STALL_INSTFETCH_XECORE22_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext659_XVE_STALL_OTHER_XECORE22_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext659_XVE_STALL_SBID_XECORE22_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext659_XVE_STALL_SENDWR_XECORE22_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext659_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext659";
    metric_set->symbol_name = "Ext659";
    metric_set->hw_config_guid = "3ed655a3-105d-438b-912a-438fb8953965";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext659_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext659__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext659__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext659__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext659__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE22 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE22_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext659__xve_shared_function_access_hold_xecore22_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext659_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE22_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE22 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE22_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext659__xve_stall_aluwr_xecore22_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext659_XVE_STALL_ALUWR_XECORE22_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE22 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE22_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext659__xve_stall_barrier_xecore22_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext659_XVE_STALL_BARRIER_XECORE22_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE22 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE22_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext659__xve_stall_instfetch_xecore22_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext659_XVE_STALL_INSTFETCH_XECORE22_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE22 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE22_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext659__xve_stall_other_xecore22_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext659_XVE_STALL_OTHER_XECORE22_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE22 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE22_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext659__xve_stall_sbid_xecore22_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext659_XVE_STALL_SBID_XECORE22_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE22 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE22_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext659__xve_stall_sendwr_xecore22_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext659_XVE_STALL_SENDWR_XECORE22_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext660_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE23_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext660_XVE_STALL_ALUWR_XECORE23_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext660_XVE_STALL_BARRIER_XECORE23_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext660_XVE_STALL_INSTFETCH_XECORE23_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext660_XVE_STALL_OTHER_XECORE23_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext660_XVE_STALL_SBID_XECORE23_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext660_XVE_STALL_SENDWR_XECORE23_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext660_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext660";
    metric_set->symbol_name = "Ext660";
    metric_set->hw_config_guid = "609bdc17-fa1d-4dc1-b1f9-04d959d9502d";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext660_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext660__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext660__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext660__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext660__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE23 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE23_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext660__xve_shared_function_access_hold_xecore23_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext660_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE23_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE23 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE23_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext660__xve_stall_aluwr_xecore23_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext660_XVE_STALL_ALUWR_XECORE23_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE23 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE23_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext660__xve_stall_barrier_xecore23_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext660_XVE_STALL_BARRIER_XECORE23_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE23 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE23_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext660__xve_stall_instfetch_xecore23_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext660_XVE_STALL_INSTFETCH_XECORE23_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE23 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE23_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext660__xve_stall_other_xecore23_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext660_XVE_STALL_OTHER_XECORE23_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE23 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE23_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext660__xve_stall_sbid_xecore23_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext660_XVE_STALL_SBID_XECORE23_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE23 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE23_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext660__xve_stall_sendwr_xecore23_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext660_XVE_STALL_SENDWR_XECORE23_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext661_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE24_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext661_XVE_STALL_ALUWR_XECORE24_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext661_XVE_STALL_BARRIER_XECORE24_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext661_XVE_STALL_INSTFETCH_XECORE24_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext661_XVE_STALL_OTHER_XECORE24_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext661_XVE_STALL_SBID_XECORE24_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext661_XVE_STALL_SENDWR_XECORE24_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext661_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext661";
    metric_set->symbol_name = "Ext661";
    metric_set->hw_config_guid = "8670adf5-1083-4e44-9b34-1ad5f7187e4b";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext661_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext661__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext661__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext661__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext661__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE24 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE24_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext661__xve_shared_function_access_hold_xecore24_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext661_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE24_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE24 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE24_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext661__xve_stall_aluwr_xecore24_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext661_XVE_STALL_ALUWR_XECORE24_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE24 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE24_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext661__xve_stall_barrier_xecore24_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext661_XVE_STALL_BARRIER_XECORE24_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE24 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE24_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext661__xve_stall_instfetch_xecore24_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext661_XVE_STALL_INSTFETCH_XECORE24_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE24 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE24_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext661__xve_stall_other_xecore24_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext661_XVE_STALL_OTHER_XECORE24_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE24 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE24_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext661__xve_stall_sbid_xecore24_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext661_XVE_STALL_SBID_XECORE24_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE24 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE24_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext661__xve_stall_sendwr_xecore24_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext661_XVE_STALL_SENDWR_XECORE24_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext662_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE25_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext662_XVE_STALL_ALUWR_XECORE25_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext662_XVE_STALL_BARRIER_XECORE25_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext662_XVE_STALL_INSTFETCH_XECORE25_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext662_XVE_STALL_OTHER_XECORE25_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext662_XVE_STALL_SBID_XECORE25_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext662_XVE_STALL_SENDWR_XECORE25_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext662_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext662";
    metric_set->symbol_name = "Ext662";
    metric_set->hw_config_guid = "6295fd5c-e29f-4522-a7bf-83be283e0bbb";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext662_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext662__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext662__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext662__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext662__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE25 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE25_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext662__xve_shared_function_access_hold_xecore25_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext662_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE25_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE25 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE25_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext662__xve_stall_aluwr_xecore25_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext662_XVE_STALL_ALUWR_XECORE25_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE25 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE25_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext662__xve_stall_barrier_xecore25_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext662_XVE_STALL_BARRIER_XECORE25_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE25 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE25_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext662__xve_stall_instfetch_xecore25_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext662_XVE_STALL_INSTFETCH_XECORE25_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE25 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE25_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext662__xve_stall_other_xecore25_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext662_XVE_STALL_OTHER_XECORE25_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE25 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE25_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext662__xve_stall_sbid_xecore25_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext662_XVE_STALL_SBID_XECORE25_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE25 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE25_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext662__xve_stall_sendwr_xecore25_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext662_XVE_STALL_SENDWR_XECORE25_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext663_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE26_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext663_XVE_STALL_ALUWR_XECORE26_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext663_XVE_STALL_BARRIER_XECORE26_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext663_XVE_STALL_INSTFETCH_XECORE26_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext663_XVE_STALL_OTHER_XECORE26_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext663_XVE_STALL_SBID_XECORE26_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext663_XVE_STALL_SENDWR_XECORE26_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext663_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext663";
    metric_set->symbol_name = "Ext663";
    metric_set->hw_config_guid = "a50eb103-f419-4fdc-bdc5-cabcf1f5f799";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext663_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext663__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext663__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext663__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext663__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE26 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE26_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext663__xve_shared_function_access_hold_xecore26_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext663_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE26_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE26 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE26_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext663__xve_stall_aluwr_xecore26_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext663_XVE_STALL_ALUWR_XECORE26_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE26 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE26_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext663__xve_stall_barrier_xecore26_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext663_XVE_STALL_BARRIER_XECORE26_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE26 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE26_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext663__xve_stall_instfetch_xecore26_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext663_XVE_STALL_INSTFETCH_XECORE26_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE26 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE26_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext663__xve_stall_other_xecore26_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext663_XVE_STALL_OTHER_XECORE26_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE26 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE26_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext663__xve_stall_sbid_xecore26_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext663_XVE_STALL_SBID_XECORE26_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE26 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE26_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext663__xve_stall_sendwr_xecore26_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext663_XVE_STALL_SENDWR_XECORE26_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext664_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE27_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext664_XVE_STALL_ALUWR_XECORE27_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext664_XVE_STALL_BARRIER_XECORE27_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext664_XVE_STALL_INSTFETCH_XECORE27_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext664_XVE_STALL_OTHER_XECORE27_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext664_XVE_STALL_SBID_XECORE27_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext664_XVE_STALL_SENDWR_XECORE27_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext664_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext664";
    metric_set->symbol_name = "Ext664";
    metric_set->hw_config_guid = "8a026261-ef0f-4331-8a07-161022e4d2a4";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext664_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext664__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext664__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext664__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext664__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE27 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE27_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext664__xve_shared_function_access_hold_xecore27_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext664_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE27_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE27 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE27_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext664__xve_stall_aluwr_xecore27_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext664_XVE_STALL_ALUWR_XECORE27_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE27 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE27_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext664__xve_stall_barrier_xecore27_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext664_XVE_STALL_BARRIER_XECORE27_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE27 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE27_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext664__xve_stall_instfetch_xecore27_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext664_XVE_STALL_INSTFETCH_XECORE27_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE27 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE27_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext664__xve_stall_other_xecore27_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext664_XVE_STALL_OTHER_XECORE27_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE27 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE27_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext664__xve_stall_sbid_xecore27_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext664_XVE_STALL_SBID_XECORE27_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE27 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE27_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext664__xve_stall_sendwr_xecore27_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext664_XVE_STALL_SENDWR_XECORE27_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext665_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE28_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext665_XVE_STALL_ALUWR_XECORE28_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext665_XVE_STALL_BARRIER_XECORE28_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext665_XVE_STALL_INSTFETCH_XECORE28_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext665_XVE_STALL_OTHER_XECORE28_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext665_XVE_STALL_SBID_XECORE28_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext665_XVE_STALL_SENDWR_XECORE28_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext665_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext665";
    metric_set->symbol_name = "Ext665";
    metric_set->hw_config_guid = "73c5b3d6-f3f9-45d5-8c88-3c3bc7cb2a7b";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext665_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext665__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext665__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext665__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext665__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE28 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE28_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext665__xve_shared_function_access_hold_xecore28_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext665_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE28_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE28 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE28_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext665__xve_stall_aluwr_xecore28_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext665_XVE_STALL_ALUWR_XECORE28_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE28 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE28_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext665__xve_stall_barrier_xecore28_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext665_XVE_STALL_BARRIER_XECORE28_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE28 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE28_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext665__xve_stall_instfetch_xecore28_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext665_XVE_STALL_INSTFETCH_XECORE28_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE28 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE28_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext665__xve_stall_other_xecore28_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext665_XVE_STALL_OTHER_XECORE28_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE28 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE28_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext665__xve_stall_sbid_xecore28_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext665_XVE_STALL_SBID_XECORE28_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE28 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE28_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext665__xve_stall_sendwr_xecore28_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext665_XVE_STALL_SENDWR_XECORE28_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext666_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE29_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext666_XVE_STALL_ALUWR_XECORE29_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext666_XVE_STALL_BARRIER_XECORE29_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext666_XVE_STALL_INSTFETCH_XECORE29_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext666_XVE_STALL_OTHER_XECORE29_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext666_XVE_STALL_SBID_XECORE29_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext666_XVE_STALL_SENDWR_XECORE29_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext666_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext666";
    metric_set->symbol_name = "Ext666";
    metric_set->hw_config_guid = "28f09392-e361-444e-984a-35bc2cd7319e";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext666_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext666__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext666__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext666__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext666__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE29 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE29_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext666__xve_shared_function_access_hold_xecore29_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext666_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE29_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE29 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE29_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext666__xve_stall_aluwr_xecore29_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext666_XVE_STALL_ALUWR_XECORE29_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE29 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE29_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext666__xve_stall_barrier_xecore29_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext666_XVE_STALL_BARRIER_XECORE29_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE29 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE29_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext666__xve_stall_instfetch_xecore29_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext666_XVE_STALL_INSTFETCH_XECORE29_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE29 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE29_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext666__xve_stall_other_xecore29_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext666_XVE_STALL_OTHER_XECORE29_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE29 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE29_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext666__xve_stall_sbid_xecore29_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext666_XVE_STALL_SBID_XECORE29_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE29 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE29_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext666__xve_stall_sendwr_xecore29_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext666_XVE_STALL_SENDWR_XECORE29_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext667_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE30_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext667_XVE_STALL_ALUWR_XECORE30_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext667_XVE_STALL_BARRIER_XECORE30_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext667_XVE_STALL_INSTFETCH_XECORE30_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext667_XVE_STALL_OTHER_XECORE30_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext667_XVE_STALL_SBID_XECORE30_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext667_XVE_STALL_SENDWR_XECORE30_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext667_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext667";
    metric_set->symbol_name = "Ext667";
    metric_set->hw_config_guid = "b5bd5646-7215-4cfb-a393-012e42f86e6b";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext667_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext667__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext667__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext667__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext667__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE30 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE30_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext667__xve_shared_function_access_hold_xecore30_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext667_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE30_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE30 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE30_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext667__xve_stall_aluwr_xecore30_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext667_XVE_STALL_ALUWR_XECORE30_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE30 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE30_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext667__xve_stall_barrier_xecore30_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext667_XVE_STALL_BARRIER_XECORE30_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE30 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE30_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext667__xve_stall_instfetch_xecore30_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext667_XVE_STALL_INSTFETCH_XECORE30_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE30 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE30_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext667__xve_stall_other_xecore30_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext667_XVE_STALL_OTHER_XECORE30_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE30 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE30_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext667__xve_stall_sbid_xecore30_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext667_XVE_STALL_SBID_XECORE30_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE30 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE30_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext667__xve_stall_sendwr_xecore30_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext667_XVE_STALL_SENDWR_XECORE30_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext668_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE31_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext668_XVE_STALL_ALUWR_XECORE31_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext668_XVE_STALL_BARRIER_XECORE31_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext668_XVE_STALL_INSTFETCH_XECORE31_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext668_XVE_STALL_OTHER_XECORE31_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext668_XVE_STALL_SBID_XECORE31_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext668_XVE_STALL_SENDWR_XECORE31_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext668_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext668";
    metric_set->symbol_name = "Ext668";
    metric_set->hw_config_guid = "e3b9472f-95b7-49b7-9f95-96d9cfcea28f";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext668_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext668__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext668__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext668__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext668__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE31 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE31_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext668__xve_shared_function_access_hold_xecore31_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext668_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE31_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE31 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE31_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext668__xve_stall_aluwr_xecore31_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext668_XVE_STALL_ALUWR_XECORE31_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE31 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE31_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext668__xve_stall_barrier_xecore31_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext668_XVE_STALL_BARRIER_XECORE31_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE31 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE31_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext668__xve_stall_instfetch_xecore31_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext668_XVE_STALL_INSTFETCH_XECORE31_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE31 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE31_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext668__xve_stall_other_xecore31_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext668_XVE_STALL_OTHER_XECORE31_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE31 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE31_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext668__xve_stall_sbid_xecore31_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext668_XVE_STALL_SBID_XECORE31_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE31 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE31_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext668__xve_stall_sendwr_xecore31_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext668_XVE_STALL_SENDWR_XECORE31_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt3_ext669_XVE_INST_ISSUED_ALL_XECORE0_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext669_XVE_INST_ISSUED_ALL_XECORE1_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext669_XVE_INST_ISSUED_ALL_XECORE2_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext669_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext669";
    metric_set->symbol_name = "Ext669";
    metric_set->hw_config_guid = "41aa8222-8353-458f-809f-88b87bb3205a";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext669_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext669__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext669__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext669__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext669__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST ISSUED ALL XECORE0 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE0_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext669__xve_inst_issued_all_xecore0_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext669_XVE_INST_ISSUED_ALL_XECORE0_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE1 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE1_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext669__xve_inst_issued_all_xecore1_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext669_XVE_INST_ISSUED_ALL_XECORE1_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE2 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE2_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext669__xve_inst_issued_all_xecore2_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext669_XVE_INST_ISSUED_ALL_XECORE2_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext670_XVE_INST_ISSUED_ALL_XECORE3_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext670_XVE_INST_ISSUED_ALL_XECORE4_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext670_XVE_INST_ISSUED_ALL_XECORE5_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext670_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext670";
    metric_set->symbol_name = "Ext670";
    metric_set->hw_config_guid = "811a2fd2-eabe-421a-822c-9a3187bae218";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext670_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext670__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext670__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext670__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext670__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST ISSUED ALL XECORE3 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE3_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext670__xve_inst_issued_all_xecore3_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext670_XVE_INST_ISSUED_ALL_XECORE3_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE4 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE4_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext670__xve_inst_issued_all_xecore4_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext670_XVE_INST_ISSUED_ALL_XECORE4_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE5 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE5_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext670__xve_inst_issued_all_xecore5_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext670_XVE_INST_ISSUED_ALL_XECORE5_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext671_XVE_INST_ISSUED_ALL_XECORE6_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext671_XVE_INST_ISSUED_ALL_XECORE7_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext671_XVE_INST_ISSUED_ALL_XECORE8_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext671_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext671";
    metric_set->symbol_name = "Ext671";
    metric_set->hw_config_guid = "22d6be5d-b649-4df4-87d3-e9e00f221d5a";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext671_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext671__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext671__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext671__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext671__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST ISSUED ALL XECORE6 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE6_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext671__xve_inst_issued_all_xecore6_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext671_XVE_INST_ISSUED_ALL_XECORE6_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE7 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE7_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext671__xve_inst_issued_all_xecore7_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext671_XVE_INST_ISSUED_ALL_XECORE7_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE8 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE8_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext671__xve_inst_issued_all_xecore8_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext671_XVE_INST_ISSUED_ALL_XECORE8_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext672_XVE_INST_ISSUED_ALL_XECORE10_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext672_XVE_INST_ISSUED_ALL_XECORE11_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext672_XVE_INST_ISSUED_ALL_XECORE9_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext672_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext672";
    metric_set->symbol_name = "Ext672";
    metric_set->hw_config_guid = "0e76590d-a922-4979-9f18-e04bf3619109";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext672_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext672__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext672__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext672__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext672__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST ISSUED ALL XECORE10 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE10_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext672__xve_inst_issued_all_xecore10_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext672_XVE_INST_ISSUED_ALL_XECORE10_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE11 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE11_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext672__xve_inst_issued_all_xecore11_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext672_XVE_INST_ISSUED_ALL_XECORE11_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE9 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE9_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext672__xve_inst_issued_all_xecore9_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext672_XVE_INST_ISSUED_ALL_XECORE9_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext673_XVE_INST_ISSUED_ALL_XECORE12_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext673_XVE_INST_ISSUED_ALL_XECORE13_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext673_XVE_INST_ISSUED_ALL_XECORE14_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext673_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext673";
    metric_set->symbol_name = "Ext673";
    metric_set->hw_config_guid = "1b1b6054-62b3-4811-b3af-7430310b36f7";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext673_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext673__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext673__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext673__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext673__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST ISSUED ALL XECORE12 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE12_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext673__xve_inst_issued_all_xecore12_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext673_XVE_INST_ISSUED_ALL_XECORE12_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE13 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE13_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext673__xve_inst_issued_all_xecore13_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext673_XVE_INST_ISSUED_ALL_XECORE13_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE14 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE14_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext673__xve_inst_issued_all_xecore14_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext673_XVE_INST_ISSUED_ALL_XECORE14_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext674_XVE_INST_ISSUED_ALL_XECORE15_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext674_XVE_INST_ISSUED_ALL_XECORE16_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext674_XVE_INST_ISSUED_ALL_XECORE17_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext674_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext674";
    metric_set->symbol_name = "Ext674";
    metric_set->hw_config_guid = "8485658d-80cd-44e4-b275-e24c659732d4";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext674_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext674__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext674__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext674__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext674__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST ISSUED ALL XECORE15 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE15_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext674__xve_inst_issued_all_xecore15_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext674_XVE_INST_ISSUED_ALL_XECORE15_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE16 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE16_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext674__xve_inst_issued_all_xecore16_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext674_XVE_INST_ISSUED_ALL_XECORE16_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE17 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE17_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext674__xve_inst_issued_all_xecore17_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext674_XVE_INST_ISSUED_ALL_XECORE17_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext675_XVE_INST_ISSUED_ALL_XECORE18_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext675_XVE_INST_ISSUED_ALL_XECORE19_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext675_XVE_INST_ISSUED_ALL_XECORE20_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext675_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext675";
    metric_set->symbol_name = "Ext675";
    metric_set->hw_config_guid = "90e30b6c-ee34-4fac-8b0c-28afe0397b18";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext675_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext675__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext675__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext675__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext675__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST ISSUED ALL XECORE18 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE18_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext675__xve_inst_issued_all_xecore18_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext675_XVE_INST_ISSUED_ALL_XECORE18_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE19 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE19_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext675__xve_inst_issued_all_xecore19_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext675_XVE_INST_ISSUED_ALL_XECORE19_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE20 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE20_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext675__xve_inst_issued_all_xecore20_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext675_XVE_INST_ISSUED_ALL_XECORE20_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext676_XVE_INST_ISSUED_ALL_XECORE21_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext676_XVE_INST_ISSUED_ALL_XECORE22_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext676_XVE_INST_ISSUED_ALL_XECORE23_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext676_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext676";
    metric_set->symbol_name = "Ext676";
    metric_set->hw_config_guid = "ac420c4f-90eb-42ec-9be9-75aaa09c99ff";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext676_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext676__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext676__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext676__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext676__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST ISSUED ALL XECORE21 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE21_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext676__xve_inst_issued_all_xecore21_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext676_XVE_INST_ISSUED_ALL_XECORE21_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE22 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE22_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext676__xve_inst_issued_all_xecore22_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext676_XVE_INST_ISSUED_ALL_XECORE22_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE23 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE23_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext676__xve_inst_issued_all_xecore23_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext676_XVE_INST_ISSUED_ALL_XECORE23_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext677_XVE_INST_ISSUED_ALL_XECORE24_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext677_XVE_INST_ISSUED_ALL_XECORE25_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext677_XVE_INST_ISSUED_ALL_XECORE26_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext677_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext677";
    metric_set->symbol_name = "Ext677";
    metric_set->hw_config_guid = "cded2a1d-8dce-4b4d-91cf-b51859474310";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext677_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext677__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext677__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext677__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext677__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST ISSUED ALL XECORE24 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE24_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext677__xve_inst_issued_all_xecore24_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext677_XVE_INST_ISSUED_ALL_XECORE24_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE25 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE25_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext677__xve_inst_issued_all_xecore25_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext677_XVE_INST_ISSUED_ALL_XECORE25_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE26 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE26_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext677__xve_inst_issued_all_xecore26_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext677_XVE_INST_ISSUED_ALL_XECORE26_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext678_XVE_INST_ISSUED_ALL_XECORE27_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext678_XVE_INST_ISSUED_ALL_XECORE28_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext678_XVE_INST_ISSUED_ALL_XECORE29_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext678_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext678";
    metric_set->symbol_name = "Ext678";
    metric_set->hw_config_guid = "c1339b79-a656-4338-ab32-99638d7cea0a";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext678_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext678__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext678__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext678__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext678__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST ISSUED ALL XECORE27 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE27_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext678__xve_inst_issued_all_xecore27_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext678_XVE_INST_ISSUED_ALL_XECORE27_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE28 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE28_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext678__xve_inst_issued_all_xecore28_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext678_XVE_INST_ISSUED_ALL_XECORE28_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE29 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE29_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext678__xve_inst_issued_all_xecore29_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext678_XVE_INST_ISSUED_ALL_XECORE29_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext679_XVE_INST_ISSUED_ALL_XECORE30_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext679_XVE_INST_ISSUED_ALL_XECORE31_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext679_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext679";
    metric_set->symbol_name = "Ext679";
    metric_set->hw_config_guid = "26d16b76-0337-479c-aa3c-c47a7a10eb23";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext679_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext679__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext679__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext679__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext679__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST ISSUED ALL XECORE30 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE30_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext679__xve_inst_issued_all_xecore30_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext679_XVE_INST_ISSUED_ALL_XECORE30_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE31 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE31_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext679__xve_inst_issued_all_xecore31_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext679_XVE_INST_ISSUED_ALL_XECORE31_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext680_RENDER_CACHE_ALLOC_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext680_RENDER_CACHE_ALLOC_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext680_RENDER_CACHE_ALLOC_L3NODE2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext680_RENDER_CACHE_ALLOC_L3NODE3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext680_RENDER_CACHE_ALLOC_L3NODE4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext680_RENDER_CACHE_ALLOC_L3NODE5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (2 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext680_RENDER_CACHE_ALLOC_L3NODE6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt3_ext680_RENDER_CACHE_ALLOC_L3NODE7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (3 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext680_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext680";
    metric_set->symbol_name = "Ext680";
    metric_set->hw_config_guid = "99d71df4-d88a-4169-a019-2b2758eea5c8";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext680_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext680__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext680__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext680__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext680__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RENDER CACHE ALLOC L3NODE0",
                .symbol_name = "RENDER_CACHE_ALLOC_L3NODE0",
                .desc = "Number of Render Cache allocations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext680__render_cache_alloc_l3_node0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext680_RENDER_CACHE_ALLOC_L3NODE0_availability,
            },

            {
                .name = "RENDER CACHE ALLOC L3NODE1",
                .symbol_name = "RENDER_CACHE_ALLOC_L3NODE1",
                .desc = "Number of Render Cache allocations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext680__render_cache_alloc_l3_node1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext680_RENDER_CACHE_ALLOC_L3NODE1_availability,
            },

            {
                .name = "RENDER CACHE ALLOC L3NODE2",
                .symbol_name = "RENDER_CACHE_ALLOC_L3NODE2",
                .desc = "Number of Render Cache allocations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext680__render_cache_alloc_l3_node2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext680_RENDER_CACHE_ALLOC_L3NODE2_availability,
            },

            {
                .name = "RENDER CACHE ALLOC L3NODE3",
                .symbol_name = "RENDER_CACHE_ALLOC_L3NODE3",
                .desc = "Number of Render Cache allocations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext680__render_cache_alloc_l3_node3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext680_RENDER_CACHE_ALLOC_L3NODE3_availability,
            },

            {
                .name = "RENDER CACHE ALLOC L3NODE4",
                .symbol_name = "RENDER_CACHE_ALLOC_L3NODE4",
                .desc = "Number of Render Cache allocations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext680__render_cache_alloc_l3_node4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext680_RENDER_CACHE_ALLOC_L3NODE4_availability,
            },

            {
                .name = "RENDER CACHE ALLOC L3NODE5",
                .symbol_name = "RENDER_CACHE_ALLOC_L3NODE5",
                .desc = "Number of Render Cache allocations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext680__render_cache_alloc_l3_node5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext680_RENDER_CACHE_ALLOC_L3NODE5_availability,
            },

            {
                .name = "RENDER CACHE ALLOC L3NODE6",
                .symbol_name = "RENDER_CACHE_ALLOC_L3NODE6",
                .desc = "Number of Render Cache allocations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext680__render_cache_alloc_l3_node6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext680_RENDER_CACHE_ALLOC_L3NODE6_availability,
            },

            {
                .name = "RENDER CACHE ALLOC L3NODE7",
                .symbol_name = "RENDER_CACHE_ALLOC_L3NODE7",
                .desc = "Number of Render Cache allocations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext680__render_cache_alloc_l3_node7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext680_RENDER_CACHE_ALLOC_L3NODE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext681_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext681_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext681_GPGPU_THREADGROUP_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext681_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext681";
    metric_set->symbol_name = "Ext681";
    metric_set->hw_config_guid = "1f921826-65ba-4ab6-a1d7-48eba4eedd34";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext681_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE4",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE4",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext681__async_gpgpu_threadgroup_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext681_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE4_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE8",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE8",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext681__async_gpgpu_thread_exit_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext681_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE8_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext681__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext681__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE0",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE0",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext681__gpgpu_threadgroup_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext681_GPGPU_THREADGROUP_COUNT_XECORE0_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext681__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext681__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext682_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext682_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext682_GPGPU_THREADGROUP_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext682_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext682";
    metric_set->symbol_name = "Ext682";
    metric_set->hw_config_guid = "69e3df50-90cf-4346-a55d-1eed069efda7";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext682_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE5",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE5",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext682__async_gpgpu_threadgroup_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext682_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE5_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE9",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE9",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext682__async_gpgpu_thread_exit_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext682_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE9_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext682__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext682__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE1",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE1",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext682__gpgpu_threadgroup_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext682_GPGPU_THREADGROUP_COUNT_XECORE1_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext682__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext682__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext683_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext683_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext683_GPGPU_THREADGROUP_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext683_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext683";
    metric_set->symbol_name = "Ext683";
    metric_set->hw_config_guid = "469421c9-dc97-4550-b37f-7c173053b76c";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext683_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE6",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE6",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext683__async_gpgpu_threadgroup_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext683_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE6_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE10",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE10",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext683__async_gpgpu_thread_exit_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext683_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE10_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext683__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext683__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE2",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE2",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext683__gpgpu_threadgroup_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext683_GPGPU_THREADGROUP_COUNT_XECORE2_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext683__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext683__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext684_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext684_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext684_GPGPU_THREADGROUP_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext684_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext684";
    metric_set->symbol_name = "Ext684";
    metric_set->hw_config_guid = "286faab2-da2e-4608-bd2f-39da15cb678c";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext684_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE7",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE7",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext684__async_gpgpu_threadgroup_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext684_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE7_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE11",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE11",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext684__async_gpgpu_thread_exit_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext684_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE11_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext684__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext684__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE3",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE3",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext684__gpgpu_threadgroup_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext684_GPGPU_THREADGROUP_COUNT_XECORE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext684__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext684__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext685_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext685_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext685_GPGPU_THREADGROUP_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext685_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext685";
    metric_set->symbol_name = "Ext685";
    metric_set->hw_config_guid = "49c8e6b6-5244-4b9f-85cf-2547d6d20a79";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext685_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE8",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE8",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext685__async_gpgpu_threadgroup_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext685_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE8_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE12",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE12",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext685__async_gpgpu_thread_exit_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext685_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE12_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext685__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext685__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE4",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE4",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext685__gpgpu_threadgroup_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext685_GPGPU_THREADGROUP_COUNT_XECORE4_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext685__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext685__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext686_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext686_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext686_GPGPU_THREADGROUP_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext686_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext686";
    metric_set->symbol_name = "Ext686";
    metric_set->hw_config_guid = "79941e03-5bdc-46e4-b142-84d418628e99";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext686_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE9",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE9",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext686__async_gpgpu_threadgroup_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext686_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE9_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE13",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE13",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext686__async_gpgpu_thread_exit_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext686_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE13_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext686__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext686__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE5",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE5",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext686__gpgpu_threadgroup_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext686_GPGPU_THREADGROUP_COUNT_XECORE5_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext686__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext686__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext687_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext687_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext687_GPGPU_THREADGROUP_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext687_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext687";
    metric_set->symbol_name = "Ext687";
    metric_set->hw_config_guid = "9e53769d-3d3b-4a27-ab3f-f524dca94ac8";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext687_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE10",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE10",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext687__async_gpgpu_threadgroup_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext687_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE10_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE14",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE14",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext687__async_gpgpu_thread_exit_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext687_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE14_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext687__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext687__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE6",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE6",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext687__gpgpu_threadgroup_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext687_GPGPU_THREADGROUP_COUNT_XECORE6_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext687__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext687__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext688_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext688_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext688_GPGPU_THREADGROUP_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext688_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext688";
    metric_set->symbol_name = "Ext688";
    metric_set->hw_config_guid = "30301f6f-0a43-4ba9-a9d5-28aebf205bdf";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext688_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE11",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE11",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext688__async_gpgpu_threadgroup_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext688_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE11_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE15",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE15",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext688__async_gpgpu_thread_exit_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext688_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE15_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext688__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext688__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE7",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE7",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext688__gpgpu_threadgroup_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext688_GPGPU_THREADGROUP_COUNT_XECORE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext688__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext688__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext689_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext689_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext689_GPGPU_THREADGROUP_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext689_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext689";
    metric_set->symbol_name = "Ext689";
    metric_set->hw_config_guid = "1d483608-9139-4903-a3af-e3ed4efc0992";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext689_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE12",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE12",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext689__async_gpgpu_threadgroup_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext689_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE12_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE16",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE16",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext689__async_gpgpu_thread_exit_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext689_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE16_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext689__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext689__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE8",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE8",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext689__gpgpu_threadgroup_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext689_GPGPU_THREADGROUP_COUNT_XECORE8_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext689__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext689__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext690_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext690_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext690_GPGPU_THREADGROUP_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext690_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext690";
    metric_set->symbol_name = "Ext690";
    metric_set->hw_config_guid = "a9cf3d9a-04ab-40d7-ab88-0eb97a8ddcca";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext690_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE13",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE13",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext690__async_gpgpu_threadgroup_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext690_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE13_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE17",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE17",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext690__async_gpgpu_thread_exit_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext690_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE17_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext690__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext690__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE9",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE9",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext690__gpgpu_threadgroup_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext690_GPGPU_THREADGROUP_COUNT_XECORE9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext690__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext690__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext691_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext691_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext691_GPGPU_THREADGROUP_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext691_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext691";
    metric_set->symbol_name = "Ext691";
    metric_set->hw_config_guid = "191874c3-d6af-4243-9b01-2b0f85bee6e4";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext691_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE14",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE14",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext691__async_gpgpu_threadgroup_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext691_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE14_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE18",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE18",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext691__async_gpgpu_thread_exit_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext691_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE18_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext691__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext691__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE10",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE10",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext691__gpgpu_threadgroup_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext691_GPGPU_THREADGROUP_COUNT_XECORE10_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext691__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext691__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext692_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext692_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext692_GPGPU_THREADGROUP_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext692_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext692";
    metric_set->symbol_name = "Ext692";
    metric_set->hw_config_guid = "0bcd4036-fa21-4cd9-8f17-dc709ee95db0";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext692_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE15",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE15",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext692__async_gpgpu_threadgroup_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext692_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE15_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE19",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE19",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext692__async_gpgpu_thread_exit_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext692_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE19_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext692__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext692__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE11",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE11",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext692__gpgpu_threadgroup_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext692_GPGPU_THREADGROUP_COUNT_XECORE11_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext692__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext692__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext693_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext693_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext693_GPGPU_THREADGROUP_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext693_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext693";
    metric_set->symbol_name = "Ext693";
    metric_set->hw_config_guid = "b7b13b5c-1e45-4127-9bc9-fabd732ec407";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext693_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE16",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE16",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext693__async_gpgpu_threadgroup_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext693_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE16_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE20",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE20",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext693__async_gpgpu_thread_exit_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext693_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE20_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext693__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext693__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE12",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE12",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext693__gpgpu_threadgroup_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext693_GPGPU_THREADGROUP_COUNT_XECORE12_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext693__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext693__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext694_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext694_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext694_GPGPU_THREADGROUP_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext694_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext694";
    metric_set->symbol_name = "Ext694";
    metric_set->hw_config_guid = "e1c1db08-2425-4276-9b36-13831ce7774a";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext694_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE17",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE17",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext694__async_gpgpu_threadgroup_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext694_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE17_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE21",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE21",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext694__async_gpgpu_thread_exit_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext694_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE21_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext694__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext694__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE13",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE13",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext694__gpgpu_threadgroup_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext694_GPGPU_THREADGROUP_COUNT_XECORE13_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext694__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext694__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext695_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext695_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext695_GPGPU_THREADGROUP_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext695_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext695";
    metric_set->symbol_name = "Ext695";
    metric_set->hw_config_guid = "84e85a65-8a55-41ac-90af-3c4fe98910a5";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext695_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE18",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE18",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext695__async_gpgpu_threadgroup_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext695_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE18_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE22",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE22",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext695__async_gpgpu_thread_exit_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext695_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE22_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext695__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext695__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE14",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE14",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext695__gpgpu_threadgroup_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext695_GPGPU_THREADGROUP_COUNT_XECORE14_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext695__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext695__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext696_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext696_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext696_GPGPU_THREADGROUP_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext696_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext696";
    metric_set->symbol_name = "Ext696";
    metric_set->hw_config_guid = "58ee0229-4bdc-4d5b-beaa-12bdff92eb97";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext696_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE19",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE19",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext696__async_gpgpu_threadgroup_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext696_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE19_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE23",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE23",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext696__async_gpgpu_thread_exit_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext696_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE23_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext696__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext696__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE15",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE15",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext696__gpgpu_threadgroup_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext696_GPGPU_THREADGROUP_COUNT_XECORE15_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext696__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext696__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext697_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext697_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext697_GPGPU_THREADGROUP_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext697_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext697";
    metric_set->symbol_name = "Ext697";
    metric_set->hw_config_guid = "76811470-81d5-4807-9f02-f1c61785015f";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext697_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE20",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE20",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext697__async_gpgpu_threadgroup_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext697_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE20_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE24",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE24",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext697__async_gpgpu_thread_exit_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext697_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE24_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext697__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext697__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE16",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE16",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext697__gpgpu_threadgroup_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext697_GPGPU_THREADGROUP_COUNT_XECORE16_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext697__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext697__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext698_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext698_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext698_GPGPU_THREADGROUP_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext698_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext698";
    metric_set->symbol_name = "Ext698";
    metric_set->hw_config_guid = "ee3d62c3-7921-453e-9e17-4de797e22de6";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext698_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE21",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE21",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext698__async_gpgpu_threadgroup_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext698_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE21_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE25",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE25",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext698__async_gpgpu_thread_exit_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext698_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE25_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext698__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext698__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE17",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE17",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext698__gpgpu_threadgroup_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext698_GPGPU_THREADGROUP_COUNT_XECORE17_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext698__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext698__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext699_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext699_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext699_GPGPU_THREADGROUP_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext699_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext699";
    metric_set->symbol_name = "Ext699";
    metric_set->hw_config_guid = "c53174bb-fbdc-4c0a-8132-75c1a668b433";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext699_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE22",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE22",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext699__async_gpgpu_threadgroup_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext699_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE22_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE26",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE26",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext699__async_gpgpu_thread_exit_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext699_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE26_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext699__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext699__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE18",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE18",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext699__gpgpu_threadgroup_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext699_GPGPU_THREADGROUP_COUNT_XECORE18_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext699__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext699__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext700_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext700_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext700_GPGPU_THREADGROUP_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext700_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext700";
    metric_set->symbol_name = "Ext700";
    metric_set->hw_config_guid = "642d68f5-312a-44d6-9bae-2bd1e3b3e617";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext700_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE23",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE23",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext700__async_gpgpu_threadgroup_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext700_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE23_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE27",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE27",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext700__async_gpgpu_thread_exit_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext700_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE27_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext700__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext700__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE19",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE19",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext700__gpgpu_threadgroup_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext700_GPGPU_THREADGROUP_COUNT_XECORE19_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext700__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext700__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext701_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext701_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext701_GPGPU_THREADGROUP_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext701_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext701";
    metric_set->symbol_name = "Ext701";
    metric_set->hw_config_guid = "5269dd1e-6831-4902-8ca4-592b23c58ef2";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext701_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE24",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE24",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext701__async_gpgpu_threadgroup_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext701_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE24_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE28",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE28",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext701__async_gpgpu_thread_exit_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext701_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE28_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext701__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext701__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE20",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE20",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext701__gpgpu_threadgroup_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext701_GPGPU_THREADGROUP_COUNT_XECORE20_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext701__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext701__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext702_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext702_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext702_GPGPU_THREADGROUP_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext702_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext702";
    metric_set->symbol_name = "Ext702";
    metric_set->hw_config_guid = "b1b5a799-4514-4027-9223-f51839cab382";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext702_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE25",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE25",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext702__async_gpgpu_threadgroup_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext702_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE25_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE29",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE29",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext702__async_gpgpu_thread_exit_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext702_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE29_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext702__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext702__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE21",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE21",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext702__gpgpu_threadgroup_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext702_GPGPU_THREADGROUP_COUNT_XECORE21_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext702__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext702__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext703_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext703_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext703_GPGPU_THREADGROUP_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext703_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext703";
    metric_set->symbol_name = "Ext703";
    metric_set->hw_config_guid = "6357ffd6-fe33-463d-8251-2113c8a90e6b";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext703_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE26",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE26",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext703__async_gpgpu_threadgroup_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext703_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE26_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE30",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE30",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext703__async_gpgpu_thread_exit_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext703_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE30_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext703__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext703__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE22",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE22",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext703__gpgpu_threadgroup_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext703_GPGPU_THREADGROUP_COUNT_XECORE22_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext703__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext703__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext704_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext704_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext704_GPGPU_THREADGROUP_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext704_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext704";
    metric_set->symbol_name = "Ext704";
    metric_set->hw_config_guid = "06b581a0-09fb-4a45-a8d8-bd77234eedf5";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext704_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE27",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE27",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext704__async_gpgpu_threadgroup_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext704_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE27_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE31",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE31",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext704__async_gpgpu_thread_exit_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext704_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE31_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext704__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext704__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE23",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE23",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext704__gpgpu_threadgroup_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext704_GPGPU_THREADGROUP_COUNT_XECORE23_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext704__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext704__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext705_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext705_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext705_GPGPU_THREADGROUP_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext705_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext705";
    metric_set->symbol_name = "Ext705";
    metric_set->hw_config_guid = "8c310d10-71e6-461c-92cb-4b33e359c923";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext705_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE28",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE28",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext705__async_gpgpu_threadgroup_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext705_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE28_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE0",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE0",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext705__async_gpgpu_thread_exit_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext705_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE0_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext705__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext705__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE24",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE24",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext705__gpgpu_threadgroup_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext705_GPGPU_THREADGROUP_COUNT_XECORE24_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext705__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext705__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext706_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext706_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext706_GPGPU_THREADGROUP_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext706_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext706";
    metric_set->symbol_name = "Ext706";
    metric_set->hw_config_guid = "01126493-600a-4768-aa3e-283509f04aaa";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext706_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE29",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE29",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext706__async_gpgpu_threadgroup_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext706_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE29_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE1",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE1",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext706__async_gpgpu_thread_exit_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext706_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE1_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext706__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext706__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE25",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE25",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext706__gpgpu_threadgroup_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext706_GPGPU_THREADGROUP_COUNT_XECORE25_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext706__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext706__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext707_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext707_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext707_GPGPU_THREADGROUP_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext707_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext707";
    metric_set->symbol_name = "Ext707";
    metric_set->hw_config_guid = "516486d7-89fc-4a00-a8ac-8cd23b9fc260";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext707_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE30",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE30",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext707__async_gpgpu_threadgroup_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext707_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE30_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE2",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE2",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext707__async_gpgpu_thread_exit_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext707_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE2_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext707__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext707__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE26",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE26",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext707__gpgpu_threadgroup_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext707_GPGPU_THREADGROUP_COUNT_XECORE26_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext707__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext707__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext708_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext708_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext708_GPGPU_THREADGROUP_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext708_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext708";
    metric_set->symbol_name = "Ext708";
    metric_set->hw_config_guid = "61ba9e98-48b7-4081-8907-a5f9f6a16244";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext708_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE31",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE31",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext708__async_gpgpu_threadgroup_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext708_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE31_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE3",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE3",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext708__async_gpgpu_thread_exit_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext708_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE3_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext708__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext708__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE27",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE27",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext708__gpgpu_threadgroup_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext708_GPGPU_THREADGROUP_COUNT_XECORE27_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext708__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext708__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext709_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext709_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext709_GPGPU_THREADGROUP_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext709_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext709";
    metric_set->symbol_name = "Ext709";
    metric_set->hw_config_guid = "a638ef3a-2575-4dcf-93dc-8d351b712a73";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext709_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE0",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE0",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext709__async_gpgpu_threadgroup_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext709_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE0_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE4",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE4",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext709__async_gpgpu_thread_exit_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext709_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE4_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext709__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext709__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE28",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE28",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext709__gpgpu_threadgroup_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext709_GPGPU_THREADGROUP_COUNT_XECORE28_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext709__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext709__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext710_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext710_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext710_GPGPU_THREADGROUP_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext710_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext710";
    metric_set->symbol_name = "Ext710";
    metric_set->hw_config_guid = "3b04d5c5-301a-4089-ac8b-71ab483ead8b";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext710_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE1",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE1",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext710__async_gpgpu_threadgroup_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext710_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE1_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE5",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE5",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext710__async_gpgpu_thread_exit_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext710_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE5_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext710__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext710__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE29",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE29",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext710__gpgpu_threadgroup_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext710_GPGPU_THREADGROUP_COUNT_XECORE29_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext710__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext710__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext711_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext711_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext711_GPGPU_THREADGROUP_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext711_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext711";
    metric_set->symbol_name = "Ext711";
    metric_set->hw_config_guid = "80168138-f069-490d-8e12-81c65d059597";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext711_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE2",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE2",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext711__async_gpgpu_threadgroup_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext711_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE2_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE6",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE6",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext711__async_gpgpu_thread_exit_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext711_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE6_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext711__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext711__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE30",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE30",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext711__gpgpu_threadgroup_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext711_GPGPU_THREADGROUP_COUNT_XECORE30_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext711__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext711__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext712_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext712_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext712_GPGPU_THREADGROUP_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext712_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext712";
    metric_set->symbol_name = "Ext712";
    metric_set->hw_config_guid = "26fb9ee1-06c9-488f-9454-6506a7fd0843";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext712_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE3",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE3",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext712__async_gpgpu_threadgroup_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext712_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE3_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE7",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE7",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext712__async_gpgpu_thread_exit_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext712_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE7_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext712__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext712__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE31",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE31",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext712__gpgpu_threadgroup_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext712_GPGPU_THREADGROUP_COUNT_XECORE31_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext712__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext712__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext713_TASK_THREADGROUP_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext713_TASK_THREAD_EXIT_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext713_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext713_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext713";
    metric_set->symbol_name = "Ext713";
    metric_set->hw_config_guid = "bf21f1d0-886c-4295-a1ee-dcf1fe02a78b";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext713_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext713__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext713__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext713__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext713__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE0",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE0",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext713__task_threadgroup_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext713_TASK_THREADGROUP_COUNT_XECORE0_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE4",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE4",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext713__task_thread_exit_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext713_TASK_THREAD_EXIT_COUNT_XECORE4_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE8",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE8",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext713__threadgroup_dispatch_resource_stall_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext713_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE8_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext714_TASK_THREADGROUP_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext714_TASK_THREAD_EXIT_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext714_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext714_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext714";
    metric_set->symbol_name = "Ext714";
    metric_set->hw_config_guid = "b2bc5d5d-269d-429b-823a-50fbb0515f9c";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext714_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext714__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext714__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext714__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext714__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE1",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE1",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext714__task_threadgroup_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext714_TASK_THREADGROUP_COUNT_XECORE1_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE5",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE5",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext714__task_thread_exit_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext714_TASK_THREAD_EXIT_COUNT_XECORE5_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE9",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE9",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext714__threadgroup_dispatch_resource_stall_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext714_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext715_TASK_THREADGROUP_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext715_TASK_THREAD_EXIT_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext715_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext715_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext715";
    metric_set->symbol_name = "Ext715";
    metric_set->hw_config_guid = "bfa11009-8e53-4adf-9cdd-68469b9831dc";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext715_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext715__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext715__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext715__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext715__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE2",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE2",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext715__task_threadgroup_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext715_TASK_THREADGROUP_COUNT_XECORE2_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE6",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE6",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext715__task_thread_exit_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext715_TASK_THREAD_EXIT_COUNT_XECORE6_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE10",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE10",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext715__threadgroup_dispatch_resource_stall_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext715_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE10_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext716_TASK_THREADGROUP_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext716_TASK_THREAD_EXIT_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext716_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext716_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext716";
    metric_set->symbol_name = "Ext716";
    metric_set->hw_config_guid = "cfdbeec4-9757-4bbc-88df-c239c4cfd596";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext716_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext716__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext716__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext716__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext716__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE3",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE3",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext716__task_threadgroup_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext716_TASK_THREADGROUP_COUNT_XECORE3_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE7",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE7",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext716__task_thread_exit_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext716_TASK_THREAD_EXIT_COUNT_XECORE7_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE11",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE11",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext716__threadgroup_dispatch_resource_stall_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext716_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext717_TASK_THREADGROUP_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext717_TASK_THREAD_EXIT_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext717_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext717_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext717";
    metric_set->symbol_name = "Ext717";
    metric_set->hw_config_guid = "f846da31-bf9f-4bbd-a0ed-c4b4d5847aa0";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext717_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext717__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext717__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext717__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext717__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE4",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE4",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext717__task_threadgroup_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext717_TASK_THREADGROUP_COUNT_XECORE4_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE8",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE8",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext717__task_thread_exit_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext717_TASK_THREAD_EXIT_COUNT_XECORE8_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE12",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE12",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext717__threadgroup_dispatch_resource_stall_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext717_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE12_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext718_TASK_THREADGROUP_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext718_TASK_THREAD_EXIT_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext718_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext718_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext718";
    metric_set->symbol_name = "Ext718";
    metric_set->hw_config_guid = "894bbe73-d0e2-41ae-86e4-26f2b865b04e";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext718_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext718__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext718__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext718__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext718__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE5",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE5",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext718__task_threadgroup_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext718_TASK_THREADGROUP_COUNT_XECORE5_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE9",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE9",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext718__task_thread_exit_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext718_TASK_THREAD_EXIT_COUNT_XECORE9_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE13",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE13",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext718__threadgroup_dispatch_resource_stall_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext718_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext719_TASK_THREADGROUP_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext719_TASK_THREAD_EXIT_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext719_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext719_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext719";
    metric_set->symbol_name = "Ext719";
    metric_set->hw_config_guid = "59118cde-ff58-4cfc-96f8-bc4339f59ca4";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext719_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext719__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext719__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext719__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext719__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE6",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE6",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext719__task_threadgroup_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext719_TASK_THREADGROUP_COUNT_XECORE6_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE10",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE10",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext719__task_thread_exit_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext719_TASK_THREAD_EXIT_COUNT_XECORE10_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE14",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE14",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext719__threadgroup_dispatch_resource_stall_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext719_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE14_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext720_TASK_THREADGROUP_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext720_TASK_THREAD_EXIT_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext720_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext720_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext720";
    metric_set->symbol_name = "Ext720";
    metric_set->hw_config_guid = "93b6fbd9-7440-4806-be39-642fa92233b3";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext720_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext720__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext720__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext720__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext720__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE7",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE7",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext720__task_threadgroup_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext720_TASK_THREADGROUP_COUNT_XECORE7_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE11",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE11",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext720__task_thread_exit_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext720_TASK_THREAD_EXIT_COUNT_XECORE11_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE15",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE15",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext720__threadgroup_dispatch_resource_stall_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext720_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext721_TASK_THREADGROUP_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext721_TASK_THREAD_EXIT_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext721_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext721_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext721";
    metric_set->symbol_name = "Ext721";
    metric_set->hw_config_guid = "cede3ea4-0edd-4d1f-9cec-0ef818ed889f";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext721_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext721__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext721__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext721__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext721__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE8",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE8",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext721__task_threadgroup_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext721_TASK_THREADGROUP_COUNT_XECORE8_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE12",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE12",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext721__task_thread_exit_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext721_TASK_THREAD_EXIT_COUNT_XECORE12_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE16",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE16",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext721__threadgroup_dispatch_resource_stall_xecore16__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext721_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE16_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext722_TASK_THREADGROUP_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext722_TASK_THREAD_EXIT_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext722_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext722_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext722";
    metric_set->symbol_name = "Ext722";
    metric_set->hw_config_guid = "dce7b950-36f2-44fd-b054-0a0329f3f3f6";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext722_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext722__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext722__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext722__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext722__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE9",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE9",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext722__task_threadgroup_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext722_TASK_THREADGROUP_COUNT_XECORE9_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE13",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE13",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext722__task_thread_exit_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext722_TASK_THREAD_EXIT_COUNT_XECORE13_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE17",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE17",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext722__threadgroup_dispatch_resource_stall_xecore17__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext722_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE17_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext723_TASK_THREADGROUP_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext723_TASK_THREAD_EXIT_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext723_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext723_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext723";
    metric_set->symbol_name = "Ext723";
    metric_set->hw_config_guid = "c3af1c92-2c04-4d33-99a6-20c5354f499d";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext723_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext723__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext723__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext723__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext723__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE10",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE10",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext723__task_threadgroup_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext723_TASK_THREADGROUP_COUNT_XECORE10_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE14",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE14",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext723__task_thread_exit_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext723_TASK_THREAD_EXIT_COUNT_XECORE14_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE18",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE18",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext723__threadgroup_dispatch_resource_stall_xecore18__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext723_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE18_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext724_TASK_THREADGROUP_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext724_TASK_THREAD_EXIT_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext724_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext724_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext724";
    metric_set->symbol_name = "Ext724";
    metric_set->hw_config_guid = "e2e9e72d-9eb9-493e-b8c6-27a4b3864ca0";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext724_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext724__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext724__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext724__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext724__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE11",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE11",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext724__task_threadgroup_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext724_TASK_THREADGROUP_COUNT_XECORE11_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE15",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE15",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext724__task_thread_exit_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext724_TASK_THREAD_EXIT_COUNT_XECORE15_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE19",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE19",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext724__threadgroup_dispatch_resource_stall_xecore19__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext724_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext725_TASK_THREADGROUP_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext725_TASK_THREAD_EXIT_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext725_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext725_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext725";
    metric_set->symbol_name = "Ext725";
    metric_set->hw_config_guid = "0511f93b-3bf2-48f7-afc4-9c4783a17d65";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext725_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext725__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext725__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext725__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext725__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE12",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE12",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext725__task_threadgroup_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext725_TASK_THREADGROUP_COUNT_XECORE12_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE16",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE16",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext725__task_thread_exit_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext725_TASK_THREAD_EXIT_COUNT_XECORE16_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE20",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE20",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext725__threadgroup_dispatch_resource_stall_xecore20__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext725_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE20_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext726_TASK_THREADGROUP_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext726_TASK_THREAD_EXIT_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext726_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext726_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext726";
    metric_set->symbol_name = "Ext726";
    metric_set->hw_config_guid = "eca95fe1-d70f-46a0-b997-858695f87ed2";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext726_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext726__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext726__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext726__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext726__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE13",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE13",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext726__task_threadgroup_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext726_TASK_THREADGROUP_COUNT_XECORE13_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE17",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE17",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext726__task_thread_exit_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext726_TASK_THREAD_EXIT_COUNT_XECORE17_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE21",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE21",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext726__threadgroup_dispatch_resource_stall_xecore21__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext726_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE21_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext727_TASK_THREADGROUP_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext727_TASK_THREAD_EXIT_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext727_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext727_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext727";
    metric_set->symbol_name = "Ext727";
    metric_set->hw_config_guid = "d8a1a2c8-b8bf-40bd-b752-7413f227b6b9";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext727_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext727__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext727__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext727__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext727__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE14",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE14",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext727__task_threadgroup_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext727_TASK_THREADGROUP_COUNT_XECORE14_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE18",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE18",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext727__task_thread_exit_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext727_TASK_THREAD_EXIT_COUNT_XECORE18_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE22",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE22",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext727__threadgroup_dispatch_resource_stall_xecore22__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext727_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE22_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext728_TASK_THREADGROUP_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext728_TASK_THREAD_EXIT_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext728_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext728_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext728";
    metric_set->symbol_name = "Ext728";
    metric_set->hw_config_guid = "8b036b26-9616-4a12-84f7-5a59e54dbd95";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext728_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext728__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext728__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext728__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext728__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE15",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE15",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext728__task_threadgroup_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext728_TASK_THREADGROUP_COUNT_XECORE15_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE19",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE19",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext728__task_thread_exit_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext728_TASK_THREAD_EXIT_COUNT_XECORE19_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE23",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE23",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext728__threadgroup_dispatch_resource_stall_xecore23__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext728_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext729_TASK_THREADGROUP_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext729_TASK_THREAD_EXIT_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext729_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext729_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext729";
    metric_set->symbol_name = "Ext729";
    metric_set->hw_config_guid = "627a650a-b847-4f3b-8e74-5cbe7eded518";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext729_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext729__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext729__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext729__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext729__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE16",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE16",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext729__task_threadgroup_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext729_TASK_THREADGROUP_COUNT_XECORE16_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE20",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE20",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext729__task_thread_exit_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext729_TASK_THREAD_EXIT_COUNT_XECORE20_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE24",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE24",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext729__threadgroup_dispatch_resource_stall_xecore24__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext729_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE24_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext730_TASK_THREADGROUP_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext730_TASK_THREAD_EXIT_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext730_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext730_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext730";
    metric_set->symbol_name = "Ext730";
    metric_set->hw_config_guid = "44ca23da-3f5a-4b64-8dd3-5dc743588b63";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext730_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext730__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext730__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext730__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext730__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE17",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE17",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext730__task_threadgroup_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext730_TASK_THREADGROUP_COUNT_XECORE17_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE21",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE21",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext730__task_thread_exit_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext730_TASK_THREAD_EXIT_COUNT_XECORE21_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE25",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE25",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext730__threadgroup_dispatch_resource_stall_xecore25__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext730_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE25_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext731_TASK_THREADGROUP_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext731_TASK_THREAD_EXIT_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext731_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext731_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext731";
    metric_set->symbol_name = "Ext731";
    metric_set->hw_config_guid = "c1327b57-650a-46c6-a7a1-50567953b8ee";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext731_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext731__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext731__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext731__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext731__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE18",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE18",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext731__task_threadgroup_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext731_TASK_THREADGROUP_COUNT_XECORE18_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE22",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE22",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext731__task_thread_exit_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext731_TASK_THREAD_EXIT_COUNT_XECORE22_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE26",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE26",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext731__threadgroup_dispatch_resource_stall_xecore26__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext731_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE26_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext732_TASK_THREADGROUP_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext732_TASK_THREAD_EXIT_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext732_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext732_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext732";
    metric_set->symbol_name = "Ext732";
    metric_set->hw_config_guid = "8029fecc-6327-44c7-8d6a-e793609f2c4d";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext732_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext732__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext732__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext732__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext732__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE19",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE19",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext732__task_threadgroup_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext732_TASK_THREADGROUP_COUNT_XECORE19_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE23",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE23",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext732__task_thread_exit_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext732_TASK_THREAD_EXIT_COUNT_XECORE23_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE27",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE27",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext732__threadgroup_dispatch_resource_stall_xecore27__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext732_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext733_TASK_THREADGROUP_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext733_TASK_THREAD_EXIT_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext733_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext733_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext733";
    metric_set->symbol_name = "Ext733";
    metric_set->hw_config_guid = "6743fa5a-d2cc-4434-84bb-98ff69765e2e";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext733_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext733__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext733__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext733__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext733__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE20",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE20",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext733__task_threadgroup_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext733_TASK_THREADGROUP_COUNT_XECORE20_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE24",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE24",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext733__task_thread_exit_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext733_TASK_THREAD_EXIT_COUNT_XECORE24_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE28",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE28",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext733__threadgroup_dispatch_resource_stall_xecore28__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext733_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE28_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext734_TASK_THREADGROUP_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext734_TASK_THREAD_EXIT_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext734_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext734_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext734";
    metric_set->symbol_name = "Ext734";
    metric_set->hw_config_guid = "993468bb-355c-44f1-90e2-1aeeff3d2b4e";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext734_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext734__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext734__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext734__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext734__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE21",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE21",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext734__task_threadgroup_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext734_TASK_THREADGROUP_COUNT_XECORE21_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE25",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE25",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext734__task_thread_exit_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext734_TASK_THREAD_EXIT_COUNT_XECORE25_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE29",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE29",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext734__threadgroup_dispatch_resource_stall_xecore29__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext734_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE29_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext735_TASK_THREADGROUP_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext735_TASK_THREAD_EXIT_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext735_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext735_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext735";
    metric_set->symbol_name = "Ext735";
    metric_set->hw_config_guid = "3fffa1b9-22e8-49f0-9f52-6f393fe33471";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext735_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext735__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext735__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext735__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext735__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE22",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE22",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext735__task_threadgroup_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext735_TASK_THREADGROUP_COUNT_XECORE22_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE26",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE26",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext735__task_thread_exit_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext735_TASK_THREAD_EXIT_COUNT_XECORE26_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE30",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE30",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext735__threadgroup_dispatch_resource_stall_xecore30__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext735_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE30_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext736_TASK_THREADGROUP_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext736_TASK_THREAD_EXIT_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext736_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext736_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext736";
    metric_set->symbol_name = "Ext736";
    metric_set->hw_config_guid = "3a9252e0-711a-4c7d-9103-d67ccba0a84c";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext736_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext736__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext736__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext736__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext736__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE23",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE23",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext736__task_threadgroup_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext736_TASK_THREADGROUP_COUNT_XECORE23_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE27",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE27",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext736__task_thread_exit_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext736_TASK_THREAD_EXIT_COUNT_XECORE27_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE31",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE31",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext736__threadgroup_dispatch_resource_stall_xecore31__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext736_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext737_TASK_THREADGROUP_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext737_TASK_THREAD_EXIT_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext737_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext737_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext737";
    metric_set->symbol_name = "Ext737";
    metric_set->hw_config_guid = "7a784b26-20ec-45bd-9e65-cb91454a0529";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext737_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext737__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext737__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext737__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext737__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE24",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE24",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext737__task_threadgroup_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext737_TASK_THREADGROUP_COUNT_XECORE24_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE28",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE28",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext737__task_thread_exit_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext737_TASK_THREAD_EXIT_COUNT_XECORE28_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE0",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE0",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext737__threadgroup_dispatch_resource_stall_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext737_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext738_TASK_THREADGROUP_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext738_TASK_THREAD_EXIT_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext738_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext738_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext738";
    metric_set->symbol_name = "Ext738";
    metric_set->hw_config_guid = "2012b848-bd30-4c0e-8c20-b76c9be7411d";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext738_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext738__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext738__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext738__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext738__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE25",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE25",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext738__task_threadgroup_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext738_TASK_THREADGROUP_COUNT_XECORE25_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE29",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE29",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext738__task_thread_exit_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext738_TASK_THREAD_EXIT_COUNT_XECORE29_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE1",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE1",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext738__threadgroup_dispatch_resource_stall_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext738_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext739_TASK_THREADGROUP_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext739_TASK_THREAD_EXIT_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext739_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext739_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext739";
    metric_set->symbol_name = "Ext739";
    metric_set->hw_config_guid = "c66cdb98-dfcf-4493-97e9-4c779e039ece";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext739_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext739__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext739__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext739__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext739__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE26",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE26",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext739__task_threadgroup_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext739_TASK_THREADGROUP_COUNT_XECORE26_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE30",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE30",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext739__task_thread_exit_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext739_TASK_THREAD_EXIT_COUNT_XECORE30_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE2",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE2",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext739__threadgroup_dispatch_resource_stall_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext739_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext740_TASK_THREADGROUP_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext740_TASK_THREAD_EXIT_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext740_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext740_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext740";
    metric_set->symbol_name = "Ext740";
    metric_set->hw_config_guid = "d38b4fa2-475c-44de-afc2-53bed3d44761";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext740_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext740__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext740__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext740__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext740__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE27",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE27",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext740__task_threadgroup_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext740_TASK_THREADGROUP_COUNT_XECORE27_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE31",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE31",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext740__task_thread_exit_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext740_TASK_THREAD_EXIT_COUNT_XECORE31_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE3",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE3",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext740__threadgroup_dispatch_resource_stall_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext740_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext741_TASK_THREADGROUP_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext741_TASK_THREAD_EXIT_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext741_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext741_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext741";
    metric_set->symbol_name = "Ext741";
    metric_set->hw_config_guid = "b11e2740-3d43-422c-8593-3739b66cdee5";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext741_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext741__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext741__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext741__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext741__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE28",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE28",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext741__task_threadgroup_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext741_TASK_THREADGROUP_COUNT_XECORE28_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE0",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE0",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext741__task_thread_exit_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext741_TASK_THREAD_EXIT_COUNT_XECORE0_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE4",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE4",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext741__threadgroup_dispatch_resource_stall_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext741_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext742_TASK_THREADGROUP_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext742_TASK_THREAD_EXIT_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext742_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext742_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext742";
    metric_set->symbol_name = "Ext742";
    metric_set->hw_config_guid = "3530dd8c-3c07-4b30-bb10-94efd308113e";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext742_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext742__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext742__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext742__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext742__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE29",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE29",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext742__task_threadgroup_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext742_TASK_THREADGROUP_COUNT_XECORE29_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE1",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE1",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext742__task_thread_exit_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext742_TASK_THREAD_EXIT_COUNT_XECORE1_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE5",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE5",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext742__threadgroup_dispatch_resource_stall_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext742_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext743_TASK_THREADGROUP_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext743_TASK_THREAD_EXIT_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext743_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext743_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext743";
    metric_set->symbol_name = "Ext743";
    metric_set->hw_config_guid = "fec76475-ec48-42b1-b794-8fca6c8d3f68";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext743_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext743__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext743__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext743__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext743__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE30",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE30",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext743__task_threadgroup_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext743_TASK_THREADGROUP_COUNT_XECORE30_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE2",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE2",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext743__task_thread_exit_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext743_TASK_THREAD_EXIT_COUNT_XECORE2_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE6",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE6",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext743__threadgroup_dispatch_resource_stall_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext743_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext744_TASK_THREADGROUP_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext744_TASK_THREAD_EXIT_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext744_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext744_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext744";
    metric_set->symbol_name = "Ext744";
    metric_set->hw_config_guid = "8b8d31ad-8dd7-492a-9339-3f735afeb52d";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext744_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext744__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext744__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext744__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext744__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE31",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE31",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext744__task_threadgroup_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext744_TASK_THREADGROUP_COUNT_XECORE31_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE3",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE3",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext744__task_thread_exit_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext744_TASK_THREAD_EXIT_COUNT_XECORE3_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE7",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE7",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext744__threadgroup_dispatch_resource_stall_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext744_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext745_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext745";
    metric_set->symbol_name = "Ext745";
    metric_set->hw_config_guid = "4273606f-d838-4bcd-a192-87ec29f55cb2";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext745_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext745__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext745__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext745__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext745__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE0",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE1",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE10",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE10",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE10_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE11",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE11",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE11_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE12",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE12",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE12_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE13",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE13",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE13_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE14",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE14",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE14_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE15",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE15",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE15_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE2",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE3",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE3_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE4",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE5",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE6",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE7",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE7_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE8",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE8",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE8_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE9",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE9",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext745_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext746_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext746";
    metric_set->symbol_name = "Ext746";
    metric_set->hw_config_guid = "e0518ba4-65e7-4855-83dd-81d0a77f939b";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext746_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext746__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext746__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext746__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext746__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE16",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE16",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore16__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE16_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE17",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE17",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore17__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE17_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE18",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE18",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore18__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE18_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE19",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE19",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore19__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE19_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE20",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE20",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore20__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE20_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE21",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE21",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore21__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE21_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE22",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE22",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore22__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE22_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE23",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE23",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore23__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE23_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE24",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE24",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore24__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE24_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE25",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE25",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore25__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE25_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE26",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE26",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore26__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE26_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE27",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE27",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore27__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE27_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE28",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE28",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore28__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE28_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE29",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE29",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore29__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE29_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE30",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE30",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore30__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE30_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE31",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE31",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore31__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext746_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext747_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext747";
    metric_set->symbol_name = "Ext747";
    metric_set->hw_config_guid = "bde1c4bb-6237-4038-becf-218c1c17d872";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext747_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext747__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext747__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext747__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext747__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE0",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE1",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE10",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE10",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE10_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE11",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE11",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE11_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE12",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE12",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE12_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE13",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE13",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE13_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE14",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE14",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE14_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE15",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE15",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE15_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE2",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE3",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE3_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE4",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE5",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE6",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE7",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE7_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE8",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE8",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE8_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE9",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE9",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext747_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext748_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext748";
    metric_set->symbol_name = "Ext748";
    metric_set->hw_config_guid = "331329d1-35f6-421d-9bdb-528bb0e20659";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext748_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext748__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext748__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext748__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext748__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE16",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE16",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore16__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE16_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE17",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE17",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore17__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE17_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE18",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE18",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore18__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE18_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE19",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE19",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore19__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE19_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE20",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE20",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore20__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE20_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE21",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE21",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore21__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE21_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE22",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE22",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore22__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE22_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE23",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE23",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore23__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE23_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE24",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE24",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore24__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE24_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE25",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE25",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore25__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE25_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE26",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE26",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore26__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE26_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE27",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE27",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore27__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE27_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE28",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE28",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore28__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE28_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE29",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE29",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore29__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE29_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE30",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE30",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore30__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE30_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE31",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE31",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore31__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext748_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext749_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext749_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext749_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext749_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext749_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext749_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext749_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext749_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext749_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext749";
    metric_set->symbol_name = "Ext749";
    metric_set->hw_config_guid = "c4cb0cd8-a65d-44f7-b06d-f94cd7c99eb7";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext749_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext749__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext749__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext749__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext749__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE0",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE0",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext749__thread_dispatch_queue0_active_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext749_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE0_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE1",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE1",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext749__thread_dispatch_queue0_active_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext749_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE1_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE2",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE2",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext749__thread_dispatch_queue0_active_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext749_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE2_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE3",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE3",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext749__thread_dispatch_queue0_active_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext749_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE3_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE4",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE4",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext749__thread_dispatch_queue0_active_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext749_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE4_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE5",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE5",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext749__thread_dispatch_queue0_active_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext749_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE5_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE6",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE6",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext749__thread_dispatch_queue0_active_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext749_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE6_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE7",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE7",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext749__thread_dispatch_queue0_active_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext749_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext750_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext750_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext750_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext750_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext750_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext750_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext750_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext750_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext750_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext750";
    metric_set->symbol_name = "Ext750";
    metric_set->hw_config_guid = "2d70235d-0d5a-4aa5-8af5-e027f2a3eb6b";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext750_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext750__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext750__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext750__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext750__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE10",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE10",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext750__thread_dispatch_queue0_active_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext750_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE10_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE11",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE11",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext750__thread_dispatch_queue0_active_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext750_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE11_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE12",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE12",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext750__thread_dispatch_queue0_active_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext750_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE12_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE13",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE13",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext750__thread_dispatch_queue0_active_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext750_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE13_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE14",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE14",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext750__thread_dispatch_queue0_active_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext750_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE14_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE15",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE15",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext750__thread_dispatch_queue0_active_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext750_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE15_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE8",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE8",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext750__thread_dispatch_queue0_active_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext750_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE8_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE9",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE9",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext750__thread_dispatch_queue0_active_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext750_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext751_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext751_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext751_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext751_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext751_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext751_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext751_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext751_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext751_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext751";
    metric_set->symbol_name = "Ext751";
    metric_set->hw_config_guid = "5673e7be-0e2f-4ef4-882d-7c8c10026603";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext751_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext751__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext751__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext751__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext751__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE16",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE16",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext751__thread_dispatch_queue0_active_xecore16__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext751_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE16_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE17",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE17",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext751__thread_dispatch_queue0_active_xecore17__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext751_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE17_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE18",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE18",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext751__thread_dispatch_queue0_active_xecore18__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext751_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE18_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE19",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE19",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext751__thread_dispatch_queue0_active_xecore19__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext751_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE19_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE20",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE20",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext751__thread_dispatch_queue0_active_xecore20__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext751_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE20_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE21",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE21",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext751__thread_dispatch_queue0_active_xecore21__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext751_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE21_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE22",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE22",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext751__thread_dispatch_queue0_active_xecore22__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext751_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE22_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE23",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE23",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext751__thread_dispatch_queue0_active_xecore23__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext751_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext752_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext752_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext752_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext752_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext752_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext752_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext752_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext752_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext752_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext752";
    metric_set->symbol_name = "Ext752";
    metric_set->hw_config_guid = "c95a1628-c0a7-4cd5-98ca-212a6eeb480d";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext752_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext752__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext752__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext752__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext752__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE24",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE24",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext752__thread_dispatch_queue0_active_xecore24__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext752_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE24_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE25",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE25",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext752__thread_dispatch_queue0_active_xecore25__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext752_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE25_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE26",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE26",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext752__thread_dispatch_queue0_active_xecore26__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext752_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE26_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE27",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE27",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext752__thread_dispatch_queue0_active_xecore27__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext752_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE27_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE28",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE28",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext752__thread_dispatch_queue0_active_xecore28__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext752_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE28_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE29",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE29",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext752__thread_dispatch_queue0_active_xecore29__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext752_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE29_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE30",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE30",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext752__thread_dispatch_queue0_active_xecore30__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext752_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE30_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE31",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE31",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext752__thread_dispatch_queue0_active_xecore31__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext752_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext753_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext753_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext753_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext753_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext753_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext753_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext753_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext753_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext753_THREAD_DISPATCH_STALL_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext753_THREAD_DISPATCH_STALL_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext753_THREAD_DISPATCH_STALL_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext753_THREAD_DISPATCH_STALL_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext753_THREAD_DISPATCH_STALL_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext753_THREAD_DISPATCH_STALL_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext753_THREAD_DISPATCH_STALL_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext753_THREAD_DISPATCH_STALL_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext753_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext753";
    metric_set->symbol_name = "Ext753";
    metric_set->hw_config_guid = "35169b45-6470-430f-b450-25c6edbc722c";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext753_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext753__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext753__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext753__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext753__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE0",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE0",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext753__thread_dispatch_queue1_active_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext753_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE0_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE1",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE1",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext753__thread_dispatch_queue1_active_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext753_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE1_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE2",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE2",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext753__thread_dispatch_queue1_active_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext753_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE2_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE3",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE3",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext753__thread_dispatch_queue1_active_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext753_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE3_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE4",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE4",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext753__thread_dispatch_queue1_active_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext753_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE4_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE5",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE5",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext753__thread_dispatch_queue1_active_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext753_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE5_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE6",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE6",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext753__thread_dispatch_queue1_active_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext753_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE6_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE7",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE7",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext753__thread_dispatch_queue1_active_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext753_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE7_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE0",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE0",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext753__thread_dispatch_stall_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext753_THREAD_DISPATCH_STALL_XECORE0_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE1",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE1",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext753__thread_dispatch_stall_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext753_THREAD_DISPATCH_STALL_XECORE1_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE2",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE2",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext753__thread_dispatch_stall_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext753_THREAD_DISPATCH_STALL_XECORE2_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE3",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE3",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext753__thread_dispatch_stall_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext753_THREAD_DISPATCH_STALL_XECORE3_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE4",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE4",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext753__thread_dispatch_stall_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext753_THREAD_DISPATCH_STALL_XECORE4_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE5",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE5",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext753__thread_dispatch_stall_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext753_THREAD_DISPATCH_STALL_XECORE5_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE6",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE6",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext753__thread_dispatch_stall_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext753_THREAD_DISPATCH_STALL_XECORE6_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE7",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE7",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext753__thread_dispatch_stall_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext753_THREAD_DISPATCH_STALL_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext754_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext754_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext754_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext754_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext754_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext754_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext754_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext754_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext754_THREAD_DISPATCH_STALL_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext754_THREAD_DISPATCH_STALL_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext754_THREAD_DISPATCH_STALL_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext754_THREAD_DISPATCH_STALL_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext754_THREAD_DISPATCH_STALL_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext754_THREAD_DISPATCH_STALL_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext754_THREAD_DISPATCH_STALL_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext754_THREAD_DISPATCH_STALL_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext754_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext754";
    metric_set->symbol_name = "Ext754";
    metric_set->hw_config_guid = "654777a6-f5d0-4360-804e-8add6b37700a";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext754_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext754__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext754__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext754__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext754__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE10",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE10",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext754__thread_dispatch_queue1_active_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext754_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE10_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE11",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE11",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext754__thread_dispatch_queue1_active_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext754_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE11_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE12",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE12",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext754__thread_dispatch_queue1_active_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext754_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE12_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE13",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE13",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext754__thread_dispatch_queue1_active_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext754_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE13_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE14",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE14",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext754__thread_dispatch_queue1_active_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext754_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE14_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE15",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE15",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext754__thread_dispatch_queue1_active_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext754_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE15_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE8",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE8",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext754__thread_dispatch_queue1_active_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext754_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE8_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE9",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE9",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext754__thread_dispatch_queue1_active_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext754_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE9_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE10",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE10",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext754__thread_dispatch_stall_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext754_THREAD_DISPATCH_STALL_XECORE10_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE11",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE11",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext754__thread_dispatch_stall_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext754_THREAD_DISPATCH_STALL_XECORE11_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE12",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE12",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext754__thread_dispatch_stall_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext754_THREAD_DISPATCH_STALL_XECORE12_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE13",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE13",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext754__thread_dispatch_stall_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext754_THREAD_DISPATCH_STALL_XECORE13_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE14",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE14",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext754__thread_dispatch_stall_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext754_THREAD_DISPATCH_STALL_XECORE14_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE15",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE15",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext754__thread_dispatch_stall_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext754_THREAD_DISPATCH_STALL_XECORE15_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE8",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE8",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext754__thread_dispatch_stall_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext754_THREAD_DISPATCH_STALL_XECORE8_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE9",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE9",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext754__thread_dispatch_stall_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext754_THREAD_DISPATCH_STALL_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext755_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext755_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext755_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext755_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext755_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext755_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext755_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext755_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext755_THREAD_DISPATCH_STALL_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext755_THREAD_DISPATCH_STALL_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext755_THREAD_DISPATCH_STALL_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext755_THREAD_DISPATCH_STALL_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext755_THREAD_DISPATCH_STALL_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext755_THREAD_DISPATCH_STALL_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext755_THREAD_DISPATCH_STALL_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext755_THREAD_DISPATCH_STALL_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext755_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext755";
    metric_set->symbol_name = "Ext755";
    metric_set->hw_config_guid = "e5ff2f98-6a0a-4a1e-9c6f-fd7e37a4acfd";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext755_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext755__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext755__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext755__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext755__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE16",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE16",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext755__thread_dispatch_queue1_active_xecore16__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext755_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE16_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE17",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE17",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext755__thread_dispatch_queue1_active_xecore17__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext755_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE17_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE18",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE18",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext755__thread_dispatch_queue1_active_xecore18__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext755_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE18_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE19",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE19",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext755__thread_dispatch_queue1_active_xecore19__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext755_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE19_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE20",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE20",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext755__thread_dispatch_queue1_active_xecore20__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext755_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE20_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE21",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE21",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext755__thread_dispatch_queue1_active_xecore21__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext755_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE21_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE22",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE22",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext755__thread_dispatch_queue1_active_xecore22__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext755_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE22_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE23",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE23",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext755__thread_dispatch_queue1_active_xecore23__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext755_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE23_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE16",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE16",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext755__thread_dispatch_stall_xecore16__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext755_THREAD_DISPATCH_STALL_XECORE16_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE17",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE17",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext755__thread_dispatch_stall_xecore17__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext755_THREAD_DISPATCH_STALL_XECORE17_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE18",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE18",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext755__thread_dispatch_stall_xecore18__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext755_THREAD_DISPATCH_STALL_XECORE18_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE19",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE19",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext755__thread_dispatch_stall_xecore19__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext755_THREAD_DISPATCH_STALL_XECORE19_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE20",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE20",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext755__thread_dispatch_stall_xecore20__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext755_THREAD_DISPATCH_STALL_XECORE20_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE21",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE21",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext755__thread_dispatch_stall_xecore21__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext755_THREAD_DISPATCH_STALL_XECORE21_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE22",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE22",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext755__thread_dispatch_stall_xecore22__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext755_THREAD_DISPATCH_STALL_XECORE22_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE23",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE23",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext755__thread_dispatch_stall_xecore23__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext755_THREAD_DISPATCH_STALL_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext756_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext756_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext756_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext756_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext756_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext756_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext756_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext756_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext756_THREAD_DISPATCH_STALL_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext756_THREAD_DISPATCH_STALL_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext756_THREAD_DISPATCH_STALL_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext756_THREAD_DISPATCH_STALL_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext756_THREAD_DISPATCH_STALL_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext756_THREAD_DISPATCH_STALL_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext756_THREAD_DISPATCH_STALL_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext756_THREAD_DISPATCH_STALL_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext756_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext756";
    metric_set->symbol_name = "Ext756";
    metric_set->hw_config_guid = "c5ef0564-f5ee-4c47-81d1-82f9e3c5356e";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext756_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext756__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext756__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext756__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext756__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE24",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE24",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext756__thread_dispatch_queue1_active_xecore24__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext756_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE24_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE25",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE25",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext756__thread_dispatch_queue1_active_xecore25__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext756_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE25_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE26",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE26",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext756__thread_dispatch_queue1_active_xecore26__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext756_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE26_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE27",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE27",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext756__thread_dispatch_queue1_active_xecore27__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext756_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE27_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE28",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE28",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext756__thread_dispatch_queue1_active_xecore28__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext756_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE28_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE29",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE29",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext756__thread_dispatch_queue1_active_xecore29__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext756_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE29_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE30",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE30",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext756__thread_dispatch_queue1_active_xecore30__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext756_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE30_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE31",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE31",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext756__thread_dispatch_queue1_active_xecore31__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext756_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE31_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE24",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE24",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext756__thread_dispatch_stall_xecore24__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext756_THREAD_DISPATCH_STALL_XECORE24_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE25",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE25",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext756__thread_dispatch_stall_xecore25__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext756_THREAD_DISPATCH_STALL_XECORE25_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE26",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE26",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext756__thread_dispatch_stall_xecore26__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext756_THREAD_DISPATCH_STALL_XECORE26_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE27",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE27",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext756__thread_dispatch_stall_xecore27__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext756_THREAD_DISPATCH_STALL_XECORE27_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE28",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE28",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext756__thread_dispatch_stall_xecore28__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext756_THREAD_DISPATCH_STALL_XECORE28_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE29",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE29",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext756__thread_dispatch_stall_xecore29__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext756_THREAD_DISPATCH_STALL_XECORE29_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE30",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE30",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext756__thread_dispatch_stall_xecore30__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext756_THREAD_DISPATCH_STALL_XECORE30_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE31",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE31",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext756__thread_dispatch_stall_xecore31__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext756_THREAD_DISPATCH_STALL_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext757_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext757";
    metric_set->symbol_name = "Ext757";
    metric_set->hw_config_guid = "4b9def4f-6c45-4b4c-aebb-b258b1432dd2";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext757_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext757__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext757__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext757__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext757__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE0",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext757__thread_dispatch_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE1",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext757__thread_dispatch_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE10",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE10",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext757__thread_dispatch_input_available_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE10_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE11",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE11",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext757__thread_dispatch_input_available_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE11_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE12",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE12",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext757__thread_dispatch_input_available_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE12_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE13",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE13",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext757__thread_dispatch_input_available_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE13_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE14",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE14",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext757__thread_dispatch_input_available_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE14_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE15",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE15",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext757__thread_dispatch_input_available_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE15_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE2",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext757__thread_dispatch_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE3",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext757__thread_dispatch_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE3_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE4",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext757__thread_dispatch_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE5",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext757__thread_dispatch_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE6",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext757__thread_dispatch_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE7",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext757__thread_dispatch_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE7_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE8",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE8",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext757__thread_dispatch_input_available_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE8_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE9",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE9",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext757__thread_dispatch_input_available_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext757_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext758_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext758";
    metric_set->symbol_name = "Ext758";
    metric_set->hw_config_guid = "4baa43ef-46f0-4563-a23c-23f7a7831777";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext758_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext758__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext758__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext758__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext758__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE16",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE16",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext758__thread_dispatch_input_available_xecore16__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE16_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE17",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE17",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext758__thread_dispatch_input_available_xecore17__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE17_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE18",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE18",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext758__thread_dispatch_input_available_xecore18__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE18_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE19",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE19",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext758__thread_dispatch_input_available_xecore19__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE19_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE20",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE20",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext758__thread_dispatch_input_available_xecore20__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE20_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE21",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE21",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext758__thread_dispatch_input_available_xecore21__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE21_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE22",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE22",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext758__thread_dispatch_input_available_xecore22__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE22_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE23",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE23",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext758__thread_dispatch_input_available_xecore23__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE23_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE24",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE24",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext758__thread_dispatch_input_available_xecore24__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE24_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE25",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE25",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext758__thread_dispatch_input_available_xecore25__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE25_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE26",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE26",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext758__thread_dispatch_input_available_xecore26__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE26_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE27",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE27",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext758__thread_dispatch_input_available_xecore27__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE27_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE28",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE28",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext758__thread_dispatch_input_available_xecore28__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE28_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE29",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE29",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext758__thread_dispatch_input_available_xecore29__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE29_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE30",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE30",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext758__thread_dispatch_input_available_xecore30__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE30_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE31",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE31",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext758__thread_dispatch_input_available_xecore31__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext758_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext759_THREAD_DISPATCH_PS_ACTIVE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext759_THREAD_DISPATCH_PS_ACTIVE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext759_THREAD_DISPATCH_PS_ACTIVE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext759_THREAD_DISPATCH_PS_ACTIVE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext759_THREAD_DISPATCH_PS_ACTIVE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext759_THREAD_DISPATCH_PS_ACTIVE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext759_THREAD_DISPATCH_PS_ACTIVE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext759_THREAD_DISPATCH_PS_ACTIVE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext759_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext759";
    metric_set->symbol_name = "Ext759";
    metric_set->hw_config_guid = "a41a6cba-5801-4b99-b6ca-522ab27bcc09";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext759_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext759__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext759__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext759__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext759__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE0",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE0",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext759__thread_dispatch_ps_active_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext759_THREAD_DISPATCH_PS_ACTIVE_XECORE0_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE1",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE1",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext759__thread_dispatch_ps_active_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext759_THREAD_DISPATCH_PS_ACTIVE_XECORE1_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE2",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE2",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext759__thread_dispatch_ps_active_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext759_THREAD_DISPATCH_PS_ACTIVE_XECORE2_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE3",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE3",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext759__thread_dispatch_ps_active_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext759_THREAD_DISPATCH_PS_ACTIVE_XECORE3_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE4",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE4",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext759__thread_dispatch_ps_active_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext759_THREAD_DISPATCH_PS_ACTIVE_XECORE4_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE5",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE5",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext759__thread_dispatch_ps_active_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext759_THREAD_DISPATCH_PS_ACTIVE_XECORE5_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE6",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE6",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext759__thread_dispatch_ps_active_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext759_THREAD_DISPATCH_PS_ACTIVE_XECORE6_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE7",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE7",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext759__thread_dispatch_ps_active_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext759_THREAD_DISPATCH_PS_ACTIVE_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext760_THREAD_DISPATCH_PS_ACTIVE_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext760_THREAD_DISPATCH_PS_ACTIVE_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext760_THREAD_DISPATCH_PS_ACTIVE_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext760_THREAD_DISPATCH_PS_ACTIVE_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext760_THREAD_DISPATCH_PS_ACTIVE_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext760_THREAD_DISPATCH_PS_ACTIVE_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext760_THREAD_DISPATCH_PS_ACTIVE_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext760_THREAD_DISPATCH_PS_ACTIVE_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext760_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext760";
    metric_set->symbol_name = "Ext760";
    metric_set->hw_config_guid = "ea5c0abd-cb97-4408-b10c-5b1e5cedfa44";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext760_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext760__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext760__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext760__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext760__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE10",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE10",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext760__thread_dispatch_ps_active_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext760_THREAD_DISPATCH_PS_ACTIVE_XECORE10_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE11",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE11",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext760__thread_dispatch_ps_active_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext760_THREAD_DISPATCH_PS_ACTIVE_XECORE11_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE12",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE12",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext760__thread_dispatch_ps_active_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext760_THREAD_DISPATCH_PS_ACTIVE_XECORE12_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE13",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE13",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext760__thread_dispatch_ps_active_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext760_THREAD_DISPATCH_PS_ACTIVE_XECORE13_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE14",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE14",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext760__thread_dispatch_ps_active_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext760_THREAD_DISPATCH_PS_ACTIVE_XECORE14_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE15",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE15",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext760__thread_dispatch_ps_active_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext760_THREAD_DISPATCH_PS_ACTIVE_XECORE15_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE8",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE8",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext760__thread_dispatch_ps_active_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext760_THREAD_DISPATCH_PS_ACTIVE_XECORE8_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE9",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE9",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext760__thread_dispatch_ps_active_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext760_THREAD_DISPATCH_PS_ACTIVE_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext761_THREAD_DISPATCH_PS_ACTIVE_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext761_THREAD_DISPATCH_PS_ACTIVE_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext761_THREAD_DISPATCH_PS_ACTIVE_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext761_THREAD_DISPATCH_PS_ACTIVE_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext761_THREAD_DISPATCH_PS_ACTIVE_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext761_THREAD_DISPATCH_PS_ACTIVE_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext761_THREAD_DISPATCH_PS_ACTIVE_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext761_THREAD_DISPATCH_PS_ACTIVE_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext761_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext761";
    metric_set->symbol_name = "Ext761";
    metric_set->hw_config_guid = "7d0f9d56-a46e-4af8-80c5-60bad08a9465";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext761_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext761__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext761__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext761__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext761__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE16",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE16",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext761__thread_dispatch_ps_active_xecore16__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext761_THREAD_DISPATCH_PS_ACTIVE_XECORE16_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE17",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE17",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext761__thread_dispatch_ps_active_xecore17__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext761_THREAD_DISPATCH_PS_ACTIVE_XECORE17_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE18",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE18",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext761__thread_dispatch_ps_active_xecore18__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext761_THREAD_DISPATCH_PS_ACTIVE_XECORE18_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE19",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE19",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext761__thread_dispatch_ps_active_xecore19__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext761_THREAD_DISPATCH_PS_ACTIVE_XECORE19_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE20",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE20",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext761__thread_dispatch_ps_active_xecore20__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext761_THREAD_DISPATCH_PS_ACTIVE_XECORE20_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE21",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE21",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext761__thread_dispatch_ps_active_xecore21__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext761_THREAD_DISPATCH_PS_ACTIVE_XECORE21_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE22",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE22",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext761__thread_dispatch_ps_active_xecore22__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext761_THREAD_DISPATCH_PS_ACTIVE_XECORE22_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE23",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE23",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext761__thread_dispatch_ps_active_xecore23__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext761_THREAD_DISPATCH_PS_ACTIVE_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext762_THREAD_DISPATCH_PS_ACTIVE_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext762_THREAD_DISPATCH_PS_ACTIVE_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext762_THREAD_DISPATCH_PS_ACTIVE_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext762_THREAD_DISPATCH_PS_ACTIVE_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext762_THREAD_DISPATCH_PS_ACTIVE_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext762_THREAD_DISPATCH_PS_ACTIVE_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext762_THREAD_DISPATCH_PS_ACTIVE_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext762_THREAD_DISPATCH_PS_ACTIVE_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext762_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext762";
    metric_set->symbol_name = "Ext762";
    metric_set->hw_config_guid = "1471b5b1-3c7f-45a5-b57b-ff70ede916ca";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext762_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext762__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext762__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext762__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext762__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE24",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE24",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext762__thread_dispatch_ps_active_xecore24__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext762_THREAD_DISPATCH_PS_ACTIVE_XECORE24_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE25",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE25",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext762__thread_dispatch_ps_active_xecore25__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext762_THREAD_DISPATCH_PS_ACTIVE_XECORE25_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE26",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE26",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext762__thread_dispatch_ps_active_xecore26__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext762_THREAD_DISPATCH_PS_ACTIVE_XECORE26_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE27",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE27",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext762__thread_dispatch_ps_active_xecore27__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext762_THREAD_DISPATCH_PS_ACTIVE_XECORE27_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE28",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE28",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext762__thread_dispatch_ps_active_xecore28__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext762_THREAD_DISPATCH_PS_ACTIVE_XECORE28_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE29",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE29",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext762__thread_dispatch_ps_active_xecore29__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext762_THREAD_DISPATCH_PS_ACTIVE_XECORE29_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE30",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE30",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext762__thread_dispatch_ps_active_xecore30__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext762_THREAD_DISPATCH_PS_ACTIVE_XECORE30_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE31",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE31",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext762__thread_dispatch_ps_active_xecore31__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext762_THREAD_DISPATCH_PS_ACTIVE_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}


static void
acmgt3_add_ext763_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext763";
    metric_set->symbol_name = "Ext763";
    metric_set->hw_config_guid = "cafc80ac-ba40-47b1-8e73-aad5b08d65fe";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext763_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext763__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext763__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext763__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext763__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HOST TO GPUMEM TRANSACTION READ",
                .symbol_name = "HOST_TO_GPUMEM_TRANSACTION_READ",
                .desc = "Number of host reads to GPU local (HBM) memory (downstream)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext763__host_to_gpumem_transaction_read__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "HOST TO GPUMEM TRANSACTION WRITE",
                .symbol_name = "HOST_TO_GPUMEM_TRANSACTION_WRITE",
                .desc = "Number of host writes to GPU local (HBM) memory (downstream)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext763__host_to_gpumem_transaction_write__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}


static void
acmgt3_add_ext764_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext764";
    metric_set->symbol_name = "Ext764";
    metric_set->hw_config_guid = "0af2df6b-39f4-4104-b2d0-c3e4077f81db";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext764_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext764__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext764__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext764__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext764__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SYSMEM TRANSACTION READ",
                .symbol_name = "SYSMEM_TRANSACTION_READ",
                .desc = "Number of system memory reads (upstream)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext764__sysmem_transaction_read__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "SYSMEM TRANSACTION WRITE",
                .symbol_name = "SYSMEM_TRANSACTION_WRITE",
                .desc = "Number of system memory writes (upstream)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext764__sysmem_transaction_write__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext765_GPGPU_DISPATCH_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext765_GPGPU_DISPATCH_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext765_GPGPU_DISPATCH_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext765_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext765";
    metric_set->symbol_name = "Ext765";
    metric_set->hw_config_guid = "3e45edea-81f9-4d7b-879b-5b4097bdd786";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext765_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext765__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext765__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU DISPATCH XECORE0",
                .symbol_name = "GPGPU_DISPATCH_XECORE0",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext765__gpgpu_dispatch_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext765_GPGPU_DISPATCH_XECORE0_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE1",
                .symbol_name = "GPGPU_DISPATCH_XECORE1",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext765__gpgpu_dispatch_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext765_GPGPU_DISPATCH_XECORE1_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE2",
                .symbol_name = "GPGPU_DISPATCH_XECORE2",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext765__gpgpu_dispatch_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext765_GPGPU_DISPATCH_XECORE2_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext765__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext765__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext766_GPGPU_DISPATCH_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext766_GPGPU_DISPATCH_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext766_GPGPU_DISPATCH_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext766_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext766";
    metric_set->symbol_name = "Ext766";
    metric_set->hw_config_guid = "eeb406e5-89ec-40f8-98d3-26deaad17507";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext766_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext766__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext766__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU DISPATCH XECORE3",
                .symbol_name = "GPGPU_DISPATCH_XECORE3",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext766__gpgpu_dispatch_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext766_GPGPU_DISPATCH_XECORE3_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE4",
                .symbol_name = "GPGPU_DISPATCH_XECORE4",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext766__gpgpu_dispatch_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext766_GPGPU_DISPATCH_XECORE4_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE5",
                .symbol_name = "GPGPU_DISPATCH_XECORE5",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext766__gpgpu_dispatch_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext766_GPGPU_DISPATCH_XECORE5_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext766__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext766__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext767_GPGPU_DISPATCH_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext767_GPGPU_DISPATCH_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext767_GPGPU_DISPATCH_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext767_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext767";
    metric_set->symbol_name = "Ext767";
    metric_set->hw_config_guid = "d68aea6c-1a71-4cec-89cf-9904b9b5707d";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext767_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext767__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext767__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU DISPATCH XECORE6",
                .symbol_name = "GPGPU_DISPATCH_XECORE6",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext767__gpgpu_dispatch_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext767_GPGPU_DISPATCH_XECORE6_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE7",
                .symbol_name = "GPGPU_DISPATCH_XECORE7",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext767__gpgpu_dispatch_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext767_GPGPU_DISPATCH_XECORE7_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE8",
                .symbol_name = "GPGPU_DISPATCH_XECORE8",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext767__gpgpu_dispatch_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext767_GPGPU_DISPATCH_XECORE8_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext767__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext767__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext768_GPGPU_DISPATCH_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext768_GPGPU_DISPATCH_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext768_GPGPU_DISPATCH_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext768_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext768";
    metric_set->symbol_name = "Ext768";
    metric_set->hw_config_guid = "9a25cdbe-0af1-4586-859b-d8f03c5a4c38";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext768_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext768__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext768__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU DISPATCH XECORE10",
                .symbol_name = "GPGPU_DISPATCH_XECORE10",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext768__gpgpu_dispatch_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext768_GPGPU_DISPATCH_XECORE10_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE11",
                .symbol_name = "GPGPU_DISPATCH_XECORE11",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext768__gpgpu_dispatch_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext768_GPGPU_DISPATCH_XECORE11_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE9",
                .symbol_name = "GPGPU_DISPATCH_XECORE9",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext768__gpgpu_dispatch_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext768_GPGPU_DISPATCH_XECORE9_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext768__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext768__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext769_GPGPU_DISPATCH_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext769_GPGPU_DISPATCH_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext769_GPGPU_DISPATCH_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext769_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext769";
    metric_set->symbol_name = "Ext769";
    metric_set->hw_config_guid = "d20aa948-8455-42ca-a4df-cc3040f89330";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext769_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext769__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext769__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU DISPATCH XECORE12",
                .symbol_name = "GPGPU_DISPATCH_XECORE12",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext769__gpgpu_dispatch_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext769_GPGPU_DISPATCH_XECORE12_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE13",
                .symbol_name = "GPGPU_DISPATCH_XECORE13",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext769__gpgpu_dispatch_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext769_GPGPU_DISPATCH_XECORE13_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE14",
                .symbol_name = "GPGPU_DISPATCH_XECORE14",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext769__gpgpu_dispatch_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext769_GPGPU_DISPATCH_XECORE14_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext769__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext769__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext770_GPGPU_DISPATCH_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext770_GPGPU_DISPATCH_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext770_GPGPU_DISPATCH_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext770_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext770";
    metric_set->symbol_name = "Ext770";
    metric_set->hw_config_guid = "adc02df6-b299-43fa-946e-2de9d979fb39";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext770_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext770__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext770__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU DISPATCH XECORE15",
                .symbol_name = "GPGPU_DISPATCH_XECORE15",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext770__gpgpu_dispatch_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext770_GPGPU_DISPATCH_XECORE15_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE16",
                .symbol_name = "GPGPU_DISPATCH_XECORE16",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext770__gpgpu_dispatch_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext770_GPGPU_DISPATCH_XECORE16_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE17",
                .symbol_name = "GPGPU_DISPATCH_XECORE17",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext770__gpgpu_dispatch_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext770_GPGPU_DISPATCH_XECORE17_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext770__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext770__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext771_GPGPU_DISPATCH_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext771_GPGPU_DISPATCH_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext771_GPGPU_DISPATCH_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext771_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext771";
    metric_set->symbol_name = "Ext771";
    metric_set->hw_config_guid = "a5d13667-8d40-4986-bf3c-60c7cdeab38f";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext771_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext771__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext771__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU DISPATCH XECORE18",
                .symbol_name = "GPGPU_DISPATCH_XECORE18",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext771__gpgpu_dispatch_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext771_GPGPU_DISPATCH_XECORE18_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE19",
                .symbol_name = "GPGPU_DISPATCH_XECORE19",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext771__gpgpu_dispatch_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext771_GPGPU_DISPATCH_XECORE19_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE20",
                .symbol_name = "GPGPU_DISPATCH_XECORE20",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext771__gpgpu_dispatch_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext771_GPGPU_DISPATCH_XECORE20_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext771__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext771__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext772_GPGPU_DISPATCH_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext772_GPGPU_DISPATCH_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext772_GPGPU_DISPATCH_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext772_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext772";
    metric_set->symbol_name = "Ext772";
    metric_set->hw_config_guid = "534443d5-42af-4388-8594-e1ff0f90dc3c";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext772_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext772__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext772__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU DISPATCH XECORE21",
                .symbol_name = "GPGPU_DISPATCH_XECORE21",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext772__gpgpu_dispatch_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext772_GPGPU_DISPATCH_XECORE21_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE22",
                .symbol_name = "GPGPU_DISPATCH_XECORE22",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext772__gpgpu_dispatch_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext772_GPGPU_DISPATCH_XECORE22_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE23",
                .symbol_name = "GPGPU_DISPATCH_XECORE23",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext772__gpgpu_dispatch_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext772_GPGPU_DISPATCH_XECORE23_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext772__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext772__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext773_GPGPU_DISPATCH_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext773_GPGPU_DISPATCH_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext773_GPGPU_DISPATCH_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext773_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext773";
    metric_set->symbol_name = "Ext773";
    metric_set->hw_config_guid = "ff303167-7860-456a-bb57-3f33a851b1be";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext773_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext773__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext773__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU DISPATCH XECORE24",
                .symbol_name = "GPGPU_DISPATCH_XECORE24",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext773__gpgpu_dispatch_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext773_GPGPU_DISPATCH_XECORE24_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE25",
                .symbol_name = "GPGPU_DISPATCH_XECORE25",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext773__gpgpu_dispatch_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext773_GPGPU_DISPATCH_XECORE25_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE26",
                .symbol_name = "GPGPU_DISPATCH_XECORE26",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext773__gpgpu_dispatch_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext773_GPGPU_DISPATCH_XECORE26_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext773__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext773__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext774_GPGPU_DISPATCH_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext774_GPGPU_DISPATCH_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext774_GPGPU_DISPATCH_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext774_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext774";
    metric_set->symbol_name = "Ext774";
    metric_set->hw_config_guid = "7bef3eac-1836-440d-be35-4c9b66eb30d5";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext774_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext774__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext774__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU DISPATCH XECORE27",
                .symbol_name = "GPGPU_DISPATCH_XECORE27",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext774__gpgpu_dispatch_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext774_GPGPU_DISPATCH_XECORE27_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE28",
                .symbol_name = "GPGPU_DISPATCH_XECORE28",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext774__gpgpu_dispatch_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext774_GPGPU_DISPATCH_XECORE28_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE29",
                .symbol_name = "GPGPU_DISPATCH_XECORE29",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext774__gpgpu_dispatch_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext774_GPGPU_DISPATCH_XECORE29_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext774__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext774__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext775_GPGPU_DISPATCH_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext775_GPGPU_DISPATCH_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext775_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext775";
    metric_set->symbol_name = "Ext775";
    metric_set->hw_config_guid = "e92a471e-0ed7-49c0-a3c0-fbb3ada6b722";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext775_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext775__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext775__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU DISPATCH XECORE30",
                .symbol_name = "GPGPU_DISPATCH_XECORE30",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext775__gpgpu_dispatch_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext775_GPGPU_DISPATCH_XECORE30_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE31",
                .symbol_name = "GPGPU_DISPATCH_XECORE31",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext775__gpgpu_dispatch_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt3_ext775_GPGPU_DISPATCH_XECORE31_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext775__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext775__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext776_XVE_MULTIPLE_PIPE_ACTIVE_XECORE0_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext776_XVE_MULTIPLE_PIPE_ACTIVE_XECORE1_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext776_XVE_MULTIPLE_PIPE_ACTIVE_XECORE2_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext776_XVE_MULTIPLE_PIPE_ACTIVE_XECORE3_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext776_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext776";
    metric_set->symbol_name = "Ext776";
    metric_set->hw_config_guid = "4a97778b-b9b8-4d0b-925a-82aea8f47efd";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext776_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext776__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext776__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext776__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext776__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE0 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE0_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext776__xve_multiple_pipe_active_xecore0_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext776_XVE_MULTIPLE_PIPE_ACTIVE_XECORE0_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE1 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE1_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext776__xve_multiple_pipe_active_xecore1_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext776_XVE_MULTIPLE_PIPE_ACTIVE_XECORE1_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE2 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE2_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext776__xve_multiple_pipe_active_xecore2_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext776_XVE_MULTIPLE_PIPE_ACTIVE_XECORE2_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE3 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE3_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext776__xve_multiple_pipe_active_xecore3_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext776_XVE_MULTIPLE_PIPE_ACTIVE_XECORE3_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext777_XVE_MULTIPLE_PIPE_ACTIVE_XECORE4_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext777_XVE_MULTIPLE_PIPE_ACTIVE_XECORE5_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext777_XVE_MULTIPLE_PIPE_ACTIVE_XECORE6_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext777_XVE_MULTIPLE_PIPE_ACTIVE_XECORE7_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext777_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext777";
    metric_set->symbol_name = "Ext777";
    metric_set->hw_config_guid = "56abdb73-a247-461c-b516-667a353dba66";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext777_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext777__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext777__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext777__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext777__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE4 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE4_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext777__xve_multiple_pipe_active_xecore4_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext777_XVE_MULTIPLE_PIPE_ACTIVE_XECORE4_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE5 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE5_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext777__xve_multiple_pipe_active_xecore5_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext777_XVE_MULTIPLE_PIPE_ACTIVE_XECORE5_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE6 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE6_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext777__xve_multiple_pipe_active_xecore6_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext777_XVE_MULTIPLE_PIPE_ACTIVE_XECORE6_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE7 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE7_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext777__xve_multiple_pipe_active_xecore7_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext777_XVE_MULTIPLE_PIPE_ACTIVE_XECORE7_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext778_XVE_MULTIPLE_PIPE_ACTIVE_XECORE10_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext778_XVE_MULTIPLE_PIPE_ACTIVE_XECORE11_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext778_XVE_MULTIPLE_PIPE_ACTIVE_XECORE8_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext778_XVE_MULTIPLE_PIPE_ACTIVE_XECORE9_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext778_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext778";
    metric_set->symbol_name = "Ext778";
    metric_set->hw_config_guid = "adb95c52-6732-4701-bf82-b19e40610730";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext778_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext778__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext778__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext778__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext778__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE10 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE10_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext778__xve_multiple_pipe_active_xecore10_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext778_XVE_MULTIPLE_PIPE_ACTIVE_XECORE10_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE11 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE11_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext778__xve_multiple_pipe_active_xecore11_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext778_XVE_MULTIPLE_PIPE_ACTIVE_XECORE11_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE8 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE8_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext778__xve_multiple_pipe_active_xecore8_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext778_XVE_MULTIPLE_PIPE_ACTIVE_XECORE8_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE9 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE9_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext778__xve_multiple_pipe_active_xecore9_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext778_XVE_MULTIPLE_PIPE_ACTIVE_XECORE9_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext779_XVE_MULTIPLE_PIPE_ACTIVE_XECORE12_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext779_XVE_MULTIPLE_PIPE_ACTIVE_XECORE13_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext779_XVE_MULTIPLE_PIPE_ACTIVE_XECORE14_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext779_XVE_MULTIPLE_PIPE_ACTIVE_XECORE15_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext779_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext779";
    metric_set->symbol_name = "Ext779";
    metric_set->hw_config_guid = "25f4ce6e-3e46-47c5-9fab-ba1503e64779";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext779_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext779__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext779__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext779__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext779__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE12 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE12_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext779__xve_multiple_pipe_active_xecore12_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext779_XVE_MULTIPLE_PIPE_ACTIVE_XECORE12_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE13 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE13_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext779__xve_multiple_pipe_active_xecore13_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext779_XVE_MULTIPLE_PIPE_ACTIVE_XECORE13_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE14 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE14_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext779__xve_multiple_pipe_active_xecore14_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext779_XVE_MULTIPLE_PIPE_ACTIVE_XECORE14_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE15 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE15_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext779__xve_multiple_pipe_active_xecore15_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext779_XVE_MULTIPLE_PIPE_ACTIVE_XECORE15_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext780_XVE_MULTIPLE_PIPE_ACTIVE_XECORE16_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext780_XVE_MULTIPLE_PIPE_ACTIVE_XECORE17_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext780_XVE_MULTIPLE_PIPE_ACTIVE_XECORE18_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext780_XVE_MULTIPLE_PIPE_ACTIVE_XECORE19_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext780_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext780";
    metric_set->symbol_name = "Ext780";
    metric_set->hw_config_guid = "1c363007-b280-4450-bf7a-89b2f26bfa87";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext780_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext780__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext780__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext780__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext780__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE16 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE16_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext780__xve_multiple_pipe_active_xecore16_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext780_XVE_MULTIPLE_PIPE_ACTIVE_XECORE16_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE17 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE17_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext780__xve_multiple_pipe_active_xecore17_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext780_XVE_MULTIPLE_PIPE_ACTIVE_XECORE17_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE18 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE18_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext780__xve_multiple_pipe_active_xecore18_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext780_XVE_MULTIPLE_PIPE_ACTIVE_XECORE18_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE19 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE19_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext780__xve_multiple_pipe_active_xecore19_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext780_XVE_MULTIPLE_PIPE_ACTIVE_XECORE19_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext781_XVE_MULTIPLE_PIPE_ACTIVE_XECORE20_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext781_XVE_MULTIPLE_PIPE_ACTIVE_XECORE21_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext781_XVE_MULTIPLE_PIPE_ACTIVE_XECORE22_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext781_XVE_MULTIPLE_PIPE_ACTIVE_XECORE23_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext781_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext781";
    metric_set->symbol_name = "Ext781";
    metric_set->hw_config_guid = "16822061-bdb0-4337-97f9-621fa82266f5";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext781_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext781__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext781__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext781__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext781__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE20 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE20_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext781__xve_multiple_pipe_active_xecore20_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext781_XVE_MULTIPLE_PIPE_ACTIVE_XECORE20_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE21 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE21_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext781__xve_multiple_pipe_active_xecore21_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext781_XVE_MULTIPLE_PIPE_ACTIVE_XECORE21_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE22 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE22_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext781__xve_multiple_pipe_active_xecore22_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext781_XVE_MULTIPLE_PIPE_ACTIVE_XECORE22_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE23 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE23_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext781__xve_multiple_pipe_active_xecore23_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext781_XVE_MULTIPLE_PIPE_ACTIVE_XECORE23_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext782_XVE_MULTIPLE_PIPE_ACTIVE_XECORE24_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext782_XVE_MULTIPLE_PIPE_ACTIVE_XECORE25_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext782_XVE_MULTIPLE_PIPE_ACTIVE_XECORE26_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext782_XVE_MULTIPLE_PIPE_ACTIVE_XECORE27_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext782_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext782";
    metric_set->symbol_name = "Ext782";
    metric_set->hw_config_guid = "1d540165-56a1-4bac-925e-b5f85c930662";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext782_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext782__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext782__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext782__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext782__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE24 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE24_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext782__xve_multiple_pipe_active_xecore24_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext782_XVE_MULTIPLE_PIPE_ACTIVE_XECORE24_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE25 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE25_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext782__xve_multiple_pipe_active_xecore25_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext782_XVE_MULTIPLE_PIPE_ACTIVE_XECORE25_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE26 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE26_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext782__xve_multiple_pipe_active_xecore26_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext782_XVE_MULTIPLE_PIPE_ACTIVE_XECORE26_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE27 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE27_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext782__xve_multiple_pipe_active_xecore27_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext782_XVE_MULTIPLE_PIPE_ACTIVE_XECORE27_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext783_XVE_MULTIPLE_PIPE_ACTIVE_XECORE28_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext783_XVE_MULTIPLE_PIPE_ACTIVE_XECORE29_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext783_XVE_MULTIPLE_PIPE_ACTIVE_XECORE30_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext783_XVE_MULTIPLE_PIPE_ACTIVE_XECORE31_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext783_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext783";
    metric_set->symbol_name = "Ext783";
    metric_set->hw_config_guid = "ded56000-0bad-417e-a357-3e96ff672775";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext783_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext783__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext783__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext783__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext783__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE28 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE28_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext783__xve_multiple_pipe_active_xecore28_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext783_XVE_MULTIPLE_PIPE_ACTIVE_XECORE28_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE29 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE29_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext783__xve_multiple_pipe_active_xecore29_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext783_XVE_MULTIPLE_PIPE_ACTIVE_XECORE29_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE30 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE30_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext783__xve_multiple_pipe_active_xecore30_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext783_XVE_MULTIPLE_PIPE_ACTIVE_XECORE30_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE31 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE31_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext783__xve_multiple_pipe_active_xecore31_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt3_ext783_XVE_MULTIPLE_PIPE_ACTIVE_XECORE31_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext784_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext784_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext784";
    metric_set->symbol_name = "Ext784";
    metric_set->hw_config_guid = "32b605b2-1b0d-4637-9570-7cf8fe65fc4b";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext784_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext784__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext784__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext784__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext784__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE0",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE0",
                .desc = "Number of promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext784__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext784_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext785_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext785_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext785";
    metric_set->symbol_name = "Ext785";
    metric_set->hw_config_guid = "c75ec9a3-1b38-4b79-84ec-5978b66a2025";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext785_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext785__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext785__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext785__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext785__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE1",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE1",
                .desc = "Number of promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext785__pixel_2x2_lit_post_rasterizer_early_depth_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext785_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext786_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext786_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext786";
    metric_set->symbol_name = "Ext786";
    metric_set->hw_config_guid = "91bd53aa-441f-4ac9-98a0-7736d2e0b114";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext786_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext786__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext786__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext786__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext786__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE2",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE2",
                .desc = "Number of promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext786__pixel_2x2_lit_post_rasterizer_early_depth_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext786_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext787_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext787_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext787";
    metric_set->symbol_name = "Ext787";
    metric_set->hw_config_guid = "94f9a5a7-03a9-4b7c-9dbd-9c21a8cf812d";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext787_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext787__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext787__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext787__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext787__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE3",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE3",
                .desc = "Number of promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext787__pixel_2x2_lit_post_rasterizer_early_depth_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext787_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext788_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext788_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext788";
    metric_set->symbol_name = "Ext788";
    metric_set->hw_config_guid = "4f1c78e4-d2fd-4830-aefc-bfb88842abaf";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext788_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext788__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext788__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext788__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext788__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE4",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE4",
                .desc = "Number of promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext788__pixel_2x2_lit_post_rasterizer_early_depth_slice4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext788_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext789_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext789_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext789";
    metric_set->symbol_name = "Ext789";
    metric_set->hw_config_guid = "c5e2f4a2-6f3e-4639-b894-2c45e1a9f0a8";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext789_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext789__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext789__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext789__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext789__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE5",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE5",
                .desc = "Number of promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext789__pixel_2x2_lit_post_rasterizer_early_depth_slice5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext789_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext790_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext790_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext790";
    metric_set->symbol_name = "Ext790";
    metric_set->hw_config_guid = "3b972302-7e1a-4da0-a144-6bd89d47dba6";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext790_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext790__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext790__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext790__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext790__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE6",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE6",
                .desc = "Number of promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext790__pixel_2x2_lit_post_rasterizer_early_depth_slice6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext790_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext791_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext791_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext791";
    metric_set->symbol_name = "Ext791";
    metric_set->hw_config_guid = "3cc5aaa1-5cb8-49d5-ac8f-51520b860975";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext791_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext791__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext791__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext791__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext791__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE7",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE7",
                .desc = "Number of promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext791__pixel_2x2_lit_post_rasterizer_early_depth_slice7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext791_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext792_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext792_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext792";
    metric_set->symbol_name = "Ext792";
    metric_set->hw_config_guid = "ccd1df98-fb94-4b65-94d5-25c3a1d39be5";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext792_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext792__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext792__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext792__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext792__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE0",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE0",
                .desc = "Number of non-promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext792__pixel_2x2_lit_post_rasterizer_late_depth_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext792_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext793_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext793_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext793";
    metric_set->symbol_name = "Ext793";
    metric_set->hw_config_guid = "317b6732-6990-422c-960b-1a82ee3b02d2";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext793_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext793__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext793__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext793__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext793__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE1",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE1",
                .desc = "Number of non-promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext793__pixel_2x2_lit_post_rasterizer_late_depth_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext793_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext794_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext794_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext794";
    metric_set->symbol_name = "Ext794";
    metric_set->hw_config_guid = "d4d3594d-4c78-4a8f-b663-2781c6aef1f7";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext794_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext794__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext794__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext794__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext794__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE2",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE2",
                .desc = "Number of non-promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext794__pixel_2x2_lit_post_rasterizer_late_depth_slice2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext794_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext795_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext795_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext795";
    metric_set->symbol_name = "Ext795";
    metric_set->hw_config_guid = "9d5f4e50-1050-47ea-8876-02e8d2a71e3f";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext795_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext795__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext795__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext795__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext795__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE3",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE3",
                .desc = "Number of non-promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext795__pixel_2x2_lit_post_rasterizer_late_depth_slice3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext795_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext796_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 4)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext796_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext796";
    metric_set->symbol_name = "Ext796";
    metric_set->hw_config_guid = "5b6d809b-26ee-4832-86bf-970d1678489b";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext796_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext796__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext796__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext796__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext796__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE4",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE4",
                .desc = "Number of non-promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext796__pixel_2x2_lit_post_rasterizer_late_depth_slice4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext796_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext797_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 5)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext797_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext797";
    metric_set->symbol_name = "Ext797";
    metric_set->hw_config_guid = "5da0a308-98ff-4ff0-9481-4971aa263b06";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext797_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext797__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext797__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext797__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext797__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE5",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE5",
                .desc = "Number of non-promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext797__pixel_2x2_lit_post_rasterizer_late_depth_slice5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext797_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext798_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 6)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext798_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext798";
    metric_set->symbol_name = "Ext798";
    metric_set->hw_config_guid = "34cac917-42ff-4860-babe-cd0952722cd5";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext798_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext798__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext798__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext798__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext798__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE6",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE6",
                .desc = "Number of non-promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext798__pixel_2x2_lit_post_rasterizer_late_depth_slice6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext798_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext799_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 7)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext799_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext799";
    metric_set->symbol_name = "Ext799";
    metric_set->hw_config_guid = "c7dcda7c-388d-4a21-8e24-dad58512c79d";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext799_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext799__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext799__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext799__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext799__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE7",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE7",
                .desc = "Number of non-promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext799__pixel_2x2_lit_post_rasterizer_late_depth_slice7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt3_ext799_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext800_RT_INSTANCE_NODE_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext800_RT_INTERNAL_NODE_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext800_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext800_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext800";
    metric_set->symbol_name = "Ext800";
    metric_set->hw_config_guid = "1528d417-08e6-4356-863b-c860637abf66";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext800_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext800__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext800__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext800__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext800__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE0",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE0",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext800__rt_instance_node_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext800_RT_INSTANCE_NODE_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE0",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE0",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext800__rt_internal_node_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext800_RT_INTERNAL_NODE_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE0",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE0",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext800__rt_traversal_step_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext800_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext801_RT_INSTANCE_NODE_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext801_RT_INTERNAL_NODE_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext801_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext801_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext801";
    metric_set->symbol_name = "Ext801";
    metric_set->hw_config_guid = "b2263f12-501d-42b8-bcda-f63faa1ba105";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext801_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext801__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext801__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext801__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext801__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE1",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE1",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext801__rt_instance_node_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext801_RT_INSTANCE_NODE_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE1",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE1",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext801__rt_internal_node_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext801_RT_INTERNAL_NODE_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE1",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE1",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext801__rt_traversal_step_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext801_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext802_RT_INSTANCE_NODE_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext802_RT_INTERNAL_NODE_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext802_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext802_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext802";
    metric_set->symbol_name = "Ext802";
    metric_set->hw_config_guid = "5db30c72-78f5-4150-87c8-264d72199699";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext802_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext802__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext802__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext802__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext802__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE2",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE2",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext802__rt_instance_node_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext802_RT_INSTANCE_NODE_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE2",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE2",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext802__rt_internal_node_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext802_RT_INTERNAL_NODE_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE2",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE2",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext802__rt_traversal_step_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext802_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext803_RT_INSTANCE_NODE_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext803_RT_INTERNAL_NODE_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext803_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext803_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext803";
    metric_set->symbol_name = "Ext803";
    metric_set->hw_config_guid = "85f9346c-6b1e-4eb1-8ab7-69cdfcee678d";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext803_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext803__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext803__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext803__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext803__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE3",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE3",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext803__rt_instance_node_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext803_RT_INSTANCE_NODE_RAY_COUNT_XECORE3_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE3",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE3",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext803__rt_internal_node_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext803_RT_INTERNAL_NODE_RAY_COUNT_XECORE3_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE3",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE3",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext803__rt_traversal_step_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext803_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext804_RT_INSTANCE_NODE_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext804_RT_INTERNAL_NODE_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext804_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext804_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext804";
    metric_set->symbol_name = "Ext804";
    metric_set->hw_config_guid = "ba52d055-bcb2-48ba-8c21-9f41517f81e7";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext804_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext804__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext804__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext804__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext804__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE4",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE4",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext804__rt_instance_node_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext804_RT_INSTANCE_NODE_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE4",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE4",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext804__rt_internal_node_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext804_RT_INTERNAL_NODE_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE4",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE4",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext804__rt_traversal_step_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext804_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext805_RT_INSTANCE_NODE_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext805_RT_INTERNAL_NODE_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext805_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext805_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext805";
    metric_set->symbol_name = "Ext805";
    metric_set->hw_config_guid = "4b9170d3-8599-49da-a448-461ab6847b01";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext805_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext805__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext805__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext805__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext805__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE5",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE5",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext805__rt_instance_node_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext805_RT_INSTANCE_NODE_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE5",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE5",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext805__rt_internal_node_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext805_RT_INTERNAL_NODE_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE5",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE5",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext805__rt_traversal_step_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext805_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext806_RT_INSTANCE_NODE_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext806_RT_INTERNAL_NODE_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext806_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext806_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext806";
    metric_set->symbol_name = "Ext806";
    metric_set->hw_config_guid = "01f56dac-1c55-4720-8ecf-de58c295648a";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext806_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext806__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext806__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext806__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext806__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE6",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE6",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext806__rt_instance_node_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext806_RT_INSTANCE_NODE_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE6",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE6",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext806__rt_internal_node_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext806_RT_INTERNAL_NODE_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE6",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE6",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext806__rt_traversal_step_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext806_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext807_RT_INSTANCE_NODE_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext807_RT_INTERNAL_NODE_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext807_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext807_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext807";
    metric_set->symbol_name = "Ext807";
    metric_set->hw_config_guid = "bba5c945-2c0c-4e5a-8a85-233623f5a46e";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext807_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext807__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext807__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext807__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext807__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE7",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE7",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext807__rt_instance_node_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext807_RT_INSTANCE_NODE_RAY_COUNT_XECORE7_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE7",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE7",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext807__rt_internal_node_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext807_RT_INTERNAL_NODE_RAY_COUNT_XECORE7_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE7",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE7",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext807__rt_traversal_step_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext807_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext808_RT_INSTANCE_NODE_RAY_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext808_RT_INTERNAL_NODE_RAY_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext808_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext808_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext808";
    metric_set->symbol_name = "Ext808";
    metric_set->hw_config_guid = "cbd45de0-0a72-4273-a133-04075a1b6606";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext808_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext808__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext808__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext808__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext808__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE8",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE8",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext808__rt_instance_node_ray_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext808_RT_INSTANCE_NODE_RAY_COUNT_XECORE8_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE8",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE8",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext808__rt_internal_node_ray_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext808_RT_INTERNAL_NODE_RAY_COUNT_XECORE8_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE8",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE8",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext808__rt_traversal_step_ray_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext808_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE8_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext809_RT_INSTANCE_NODE_RAY_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext809_RT_INTERNAL_NODE_RAY_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext809_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext809_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext809";
    metric_set->symbol_name = "Ext809";
    metric_set->hw_config_guid = "c5dd3d85-c642-4bab-9b0d-a5cf7516fd9b";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext809_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext809__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext809__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext809__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext809__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE9",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE9",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext809__rt_instance_node_ray_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext809_RT_INSTANCE_NODE_RAY_COUNT_XECORE9_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE9",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE9",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext809__rt_internal_node_ray_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext809_RT_INTERNAL_NODE_RAY_COUNT_XECORE9_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE9",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE9",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext809__rt_traversal_step_ray_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext809_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext810_RT_INSTANCE_NODE_RAY_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext810_RT_INTERNAL_NODE_RAY_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext810_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext810_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext810";
    metric_set->symbol_name = "Ext810";
    metric_set->hw_config_guid = "311d6164-1ed7-416c-b029-e4ce8b6c7bf2";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext810_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext810__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext810__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext810__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext810__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE10",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE10",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext810__rt_instance_node_ray_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext810_RT_INSTANCE_NODE_RAY_COUNT_XECORE10_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE10",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE10",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext810__rt_internal_node_ray_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext810_RT_INTERNAL_NODE_RAY_COUNT_XECORE10_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE10",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE10",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext810__rt_traversal_step_ray_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext810_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE10_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext811_RT_INSTANCE_NODE_RAY_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext811_RT_INTERNAL_NODE_RAY_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext811_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext811_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext811";
    metric_set->symbol_name = "Ext811";
    metric_set->hw_config_guid = "a75430da-ab08-4b44-abf4-21de4a98210d";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext811_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext811__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext811__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext811__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext811__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE11",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE11",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext811__rt_instance_node_ray_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext811_RT_INSTANCE_NODE_RAY_COUNT_XECORE11_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE11",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE11",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext811__rt_internal_node_ray_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext811_RT_INTERNAL_NODE_RAY_COUNT_XECORE11_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE11",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE11",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext811__rt_traversal_step_ray_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext811_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext812_RT_INSTANCE_NODE_RAY_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext812_RT_INTERNAL_NODE_RAY_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext812_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext812_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext812";
    metric_set->symbol_name = "Ext812";
    metric_set->hw_config_guid = "b50ad38b-7555-47d2-a46c-257ba01fa79e";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext812_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext812__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext812__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext812__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext812__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE12",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE12",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext812__rt_instance_node_ray_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext812_RT_INSTANCE_NODE_RAY_COUNT_XECORE12_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE12",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE12",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext812__rt_internal_node_ray_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext812_RT_INTERNAL_NODE_RAY_COUNT_XECORE12_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE12",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE12",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext812__rt_traversal_step_ray_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext812_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE12_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext813_RT_INSTANCE_NODE_RAY_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext813_RT_INTERNAL_NODE_RAY_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext813_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext813_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext813";
    metric_set->symbol_name = "Ext813";
    metric_set->hw_config_guid = "04682809-a9ee-4ef2-a4a7-9d65454305df";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext813_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext813__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext813__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext813__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext813__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE13",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE13",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext813__rt_instance_node_ray_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext813_RT_INSTANCE_NODE_RAY_COUNT_XECORE13_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE13",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE13",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext813__rt_internal_node_ray_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext813_RT_INTERNAL_NODE_RAY_COUNT_XECORE13_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE13",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE13",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext813__rt_traversal_step_ray_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext813_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext814_RT_INSTANCE_NODE_RAY_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext814_RT_INTERNAL_NODE_RAY_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext814_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext814_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext814";
    metric_set->symbol_name = "Ext814";
    metric_set->hw_config_guid = "b8213dc4-d664-4c60-8a93-4eefb9a35c72";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext814_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext814__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext814__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext814__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext814__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE14",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE14",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext814__rt_instance_node_ray_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext814_RT_INSTANCE_NODE_RAY_COUNT_XECORE14_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE14",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE14",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext814__rt_internal_node_ray_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext814_RT_INTERNAL_NODE_RAY_COUNT_XECORE14_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE14",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE14",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext814__rt_traversal_step_ray_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext814_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE14_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext815_RT_INSTANCE_NODE_RAY_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext815_RT_INTERNAL_NODE_RAY_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext815_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext815_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext815";
    metric_set->symbol_name = "Ext815";
    metric_set->hw_config_guid = "b62ea20f-c05b-4817-81c1-d79e28df757c";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext815_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext815__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext815__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext815__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext815__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE15",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE15",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext815__rt_instance_node_ray_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext815_RT_INSTANCE_NODE_RAY_COUNT_XECORE15_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE15",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE15",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext815__rt_internal_node_ray_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext815_RT_INTERNAL_NODE_RAY_COUNT_XECORE15_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE15",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE15",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext815__rt_traversal_step_ray_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext815_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext816_RT_INSTANCE_NODE_RAY_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext816_RT_INTERNAL_NODE_RAY_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext816_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext816_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext816";
    metric_set->symbol_name = "Ext816";
    metric_set->hw_config_guid = "6670d652-d39b-4d76-98f5-c12c50440f15";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext816_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext816__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext816__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext816__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext816__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE16",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE16",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext816__rt_instance_node_ray_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext816_RT_INSTANCE_NODE_RAY_COUNT_XECORE16_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE16",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE16",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext816__rt_internal_node_ray_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext816_RT_INTERNAL_NODE_RAY_COUNT_XECORE16_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE16",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE16",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext816__rt_traversal_step_ray_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext816_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE16_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext817_RT_INSTANCE_NODE_RAY_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext817_RT_INTERNAL_NODE_RAY_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext817_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext817_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext817";
    metric_set->symbol_name = "Ext817";
    metric_set->hw_config_guid = "5e08ce48-10e9-4321-b042-480df816d469";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext817_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext817__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext817__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext817__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext817__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE17",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE17",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext817__rt_instance_node_ray_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext817_RT_INSTANCE_NODE_RAY_COUNT_XECORE17_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE17",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE17",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext817__rt_internal_node_ray_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext817_RT_INTERNAL_NODE_RAY_COUNT_XECORE17_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE17",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE17",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext817__rt_traversal_step_ray_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext817_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE17_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext818_RT_INSTANCE_NODE_RAY_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext818_RT_INTERNAL_NODE_RAY_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext818_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext818_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext818";
    metric_set->symbol_name = "Ext818";
    metric_set->hw_config_guid = "c422c5d1-a02c-48b4-96df-9b8875974dc3";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext818_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext818__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext818__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext818__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext818__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE18",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE18",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext818__rt_instance_node_ray_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext818_RT_INSTANCE_NODE_RAY_COUNT_XECORE18_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE18",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE18",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext818__rt_internal_node_ray_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext818_RT_INTERNAL_NODE_RAY_COUNT_XECORE18_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE18",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE18",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext818__rt_traversal_step_ray_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext818_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE18_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext819_RT_INSTANCE_NODE_RAY_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext819_RT_INTERNAL_NODE_RAY_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext819_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext819_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext819";
    metric_set->symbol_name = "Ext819";
    metric_set->hw_config_guid = "4a75128f-63bb-48d5-a888-ab44203de10a";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext819_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext819__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext819__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext819__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext819__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE19",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE19",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext819__rt_instance_node_ray_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext819_RT_INSTANCE_NODE_RAY_COUNT_XECORE19_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE19",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE19",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext819__rt_internal_node_ray_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext819_RT_INTERNAL_NODE_RAY_COUNT_XECORE19_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE19",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE19",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext819__rt_traversal_step_ray_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext819_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext820_RT_INSTANCE_NODE_RAY_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext820_RT_INTERNAL_NODE_RAY_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext820_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext820_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext820";
    metric_set->symbol_name = "Ext820";
    metric_set->hw_config_guid = "43ba1de5-4b19-4c2c-b009-0cdf4c84c85f";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext820_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext820__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext820__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext820__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext820__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE20",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE20",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext820__rt_instance_node_ray_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext820_RT_INSTANCE_NODE_RAY_COUNT_XECORE20_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE20",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE20",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext820__rt_internal_node_ray_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext820_RT_INTERNAL_NODE_RAY_COUNT_XECORE20_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE20",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE20",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext820__rt_traversal_step_ray_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext820_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE20_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext821_RT_INSTANCE_NODE_RAY_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext821_RT_INTERNAL_NODE_RAY_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext821_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext821_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext821";
    metric_set->symbol_name = "Ext821";
    metric_set->hw_config_guid = "f9881b7a-0445-44f3-a681-38a8a96179d5";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext821_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext821__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext821__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext821__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext821__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE21",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE21",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext821__rt_instance_node_ray_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext821_RT_INSTANCE_NODE_RAY_COUNT_XECORE21_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE21",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE21",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext821__rt_internal_node_ray_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext821_RT_INTERNAL_NODE_RAY_COUNT_XECORE21_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE21",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE21",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext821__rt_traversal_step_ray_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext821_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE21_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext822_RT_INSTANCE_NODE_RAY_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext822_RT_INTERNAL_NODE_RAY_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext822_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext822_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext822";
    metric_set->symbol_name = "Ext822";
    metric_set->hw_config_guid = "0ba4ce29-a0aa-4a5e-8a95-005675a4a7d2";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext822_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext822__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext822__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext822__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext822__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE22",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE22",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext822__rt_instance_node_ray_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext822_RT_INSTANCE_NODE_RAY_COUNT_XECORE22_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE22",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE22",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext822__rt_internal_node_ray_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext822_RT_INTERNAL_NODE_RAY_COUNT_XECORE22_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE22",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE22",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext822__rt_traversal_step_ray_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext822_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE22_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext823_RT_INSTANCE_NODE_RAY_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext823_RT_INTERNAL_NODE_RAY_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext823_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext823_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext823";
    metric_set->symbol_name = "Ext823";
    metric_set->hw_config_guid = "a6008e79-794a-433b-8236-5b0cc13bb166";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext823_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext823__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext823__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext823__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext823__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE23",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE23",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext823__rt_instance_node_ray_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext823_RT_INSTANCE_NODE_RAY_COUNT_XECORE23_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE23",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE23",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext823__rt_internal_node_ray_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext823_RT_INTERNAL_NODE_RAY_COUNT_XECORE23_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE23",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE23",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext823__rt_traversal_step_ray_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext823_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext824_RT_INSTANCE_NODE_RAY_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext824_RT_INTERNAL_NODE_RAY_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext824_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext824_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext824";
    metric_set->symbol_name = "Ext824";
    metric_set->hw_config_guid = "7293c8c9-c859-4f6d-a9e1-7245a5dd2ad5";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext824_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext824__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext824__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext824__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext824__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE24",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE24",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext824__rt_instance_node_ray_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext824_RT_INSTANCE_NODE_RAY_COUNT_XECORE24_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE24",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE24",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext824__rt_internal_node_ray_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext824_RT_INTERNAL_NODE_RAY_COUNT_XECORE24_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE24",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE24",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext824__rt_traversal_step_ray_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext824_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE24_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext825_RT_INSTANCE_NODE_RAY_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext825_RT_INTERNAL_NODE_RAY_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext825_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext825_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext825";
    metric_set->symbol_name = "Ext825";
    metric_set->hw_config_guid = "703e8945-2aba-4163-be6d-46dfc2026a4c";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext825_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext825__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext825__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext825__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext825__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE25",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE25",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext825__rt_instance_node_ray_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext825_RT_INSTANCE_NODE_RAY_COUNT_XECORE25_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE25",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE25",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext825__rt_internal_node_ray_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext825_RT_INTERNAL_NODE_RAY_COUNT_XECORE25_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE25",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE25",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext825__rt_traversal_step_ray_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext825_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE25_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext826_RT_INSTANCE_NODE_RAY_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext826_RT_INTERNAL_NODE_RAY_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext826_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext826_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext826";
    metric_set->symbol_name = "Ext826";
    metric_set->hw_config_guid = "86fe7724-e6d6-4cb8-be2f-e5974a7f09c3";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext826_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext826__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext826__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext826__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext826__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE26",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE26",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext826__rt_instance_node_ray_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext826_RT_INSTANCE_NODE_RAY_COUNT_XECORE26_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE26",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE26",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext826__rt_internal_node_ray_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext826_RT_INTERNAL_NODE_RAY_COUNT_XECORE26_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE26",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE26",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext826__rt_traversal_step_ray_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext826_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE26_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext827_RT_INSTANCE_NODE_RAY_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext827_RT_INTERNAL_NODE_RAY_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext827_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext827_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext827";
    metric_set->symbol_name = "Ext827";
    metric_set->hw_config_guid = "7cdb9b53-1702-4343-bbe1-f82a5a7f0e90";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext827_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext827__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext827__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext827__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext827__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE27",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE27",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext827__rt_instance_node_ray_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext827_RT_INSTANCE_NODE_RAY_COUNT_XECORE27_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE27",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE27",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext827__rt_internal_node_ray_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext827_RT_INTERNAL_NODE_RAY_COUNT_XECORE27_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE27",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE27",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext827__rt_traversal_step_ray_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext827_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext828_RT_INSTANCE_NODE_RAY_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext828_RT_INTERNAL_NODE_RAY_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext828_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext828_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext828";
    metric_set->symbol_name = "Ext828";
    metric_set->hw_config_guid = "49835d12-bfcd-41c8-aab2-623fb75e5af1";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext828_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext828__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext828__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext828__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext828__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE28",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE28",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext828__rt_instance_node_ray_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext828_RT_INSTANCE_NODE_RAY_COUNT_XECORE28_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE28",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE28",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext828__rt_internal_node_ray_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext828_RT_INTERNAL_NODE_RAY_COUNT_XECORE28_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE28",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE28",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext828__rt_traversal_step_ray_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext828_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE28_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext829_RT_INSTANCE_NODE_RAY_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext829_RT_INTERNAL_NODE_RAY_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext829_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext829_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext829";
    metric_set->symbol_name = "Ext829";
    metric_set->hw_config_guid = "bfdd0f51-5128-4a1f-aaa0-02fca7613300";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext829_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext829__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext829__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext829__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext829__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE29",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE29",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext829__rt_instance_node_ray_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext829_RT_INSTANCE_NODE_RAY_COUNT_XECORE29_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE29",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE29",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext829__rt_internal_node_ray_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext829_RT_INTERNAL_NODE_RAY_COUNT_XECORE29_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE29",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE29",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext829__rt_traversal_step_ray_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext829_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE29_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext830_RT_INSTANCE_NODE_RAY_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext830_RT_INTERNAL_NODE_RAY_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext830_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext830_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext830";
    metric_set->symbol_name = "Ext830";
    metric_set->hw_config_guid = "2b893c3a-2f78-4e0e-aa92-bc332d6d1f0f";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext830_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext830__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext830__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext830__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext830__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE30",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE30",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext830__rt_instance_node_ray_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext830_RT_INSTANCE_NODE_RAY_COUNT_XECORE30_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE30",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE30",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext830__rt_internal_node_ray_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext830_RT_INTERNAL_NODE_RAY_COUNT_XECORE30_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE30",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE30",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext830__rt_traversal_step_ray_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext830_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE30_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext831_RT_INSTANCE_NODE_RAY_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext831_RT_INTERNAL_NODE_RAY_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext831_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext831_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext831";
    metric_set->symbol_name = "Ext831";
    metric_set->hw_config_guid = "df89b9fa-509e-4980-be3f-a9fc3604e079";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext831_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext831__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext831__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext831__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext831__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE31",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE31",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext831__rt_instance_node_ray_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext831_RT_INSTANCE_NODE_RAY_COUNT_XECORE31_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE31",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE31",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext831__rt_internal_node_ray_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext831_RT_INTERNAL_NODE_RAY_COUNT_XECORE31_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE31",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE31",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext831__rt_traversal_step_ray_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext831_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt3_ext832_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext832_RT_QUAD_LEAF_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext832_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext832";
    metric_set->symbol_name = "Ext832";
    metric_set->hw_config_guid = "d6a49316-ce8d-467e-930f-66f89748d7f6";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext832_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext832__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext832__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext832__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext832__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE0",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE0",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext832__rt_procedural_node_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext832_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE0",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE0",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext832__rt_quad_leaf_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext832_RT_QUAD_LEAF_RAY_COUNT_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext833_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext833_RT_QUAD_LEAF_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext833_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext833";
    metric_set->symbol_name = "Ext833";
    metric_set->hw_config_guid = "82b22389-9176-4be3-8cf7-ebeb1db973fc";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext833_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext833__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext833__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext833__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext833__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE1",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE1",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext833__rt_procedural_node_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext833_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE1",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE1",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext833__rt_quad_leaf_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext833_RT_QUAD_LEAF_RAY_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext834_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext834_RT_QUAD_LEAF_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext834_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext834";
    metric_set->symbol_name = "Ext834";
    metric_set->hw_config_guid = "c1e9d6fe-8cd9-4c83-b9ec-5669c16e51ca";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext834_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext834__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext834__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext834__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext834__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE2",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE2",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext834__rt_procedural_node_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext834_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE2",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE2",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext834__rt_quad_leaf_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext834_RT_QUAD_LEAF_RAY_COUNT_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext835_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext835_RT_QUAD_LEAF_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext835_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext835";
    metric_set->symbol_name = "Ext835";
    metric_set->hw_config_guid = "ef2c993e-ea71-4d00-81eb-a4192d00cd5d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext835_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext835__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext835__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext835__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext835__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE3",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE3",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext835__rt_procedural_node_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext835_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE3_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE3",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE3",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext835__rt_quad_leaf_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext835_RT_QUAD_LEAF_RAY_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext836_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext836_RT_QUAD_LEAF_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext836_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext836";
    metric_set->symbol_name = "Ext836";
    metric_set->hw_config_guid = "e4a9361e-d864-4368-8129-9171a70c6ab3";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext836_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext836__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext836__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext836__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext836__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE4",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE4",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext836__rt_procedural_node_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext836_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE4",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE4",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext836__rt_quad_leaf_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext836_RT_QUAD_LEAF_RAY_COUNT_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext837_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext837_RT_QUAD_LEAF_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext837_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext837";
    metric_set->symbol_name = "Ext837";
    metric_set->hw_config_guid = "5157b0b6-6842-4d74-afc5-e9cfc011b13f";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext837_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext837__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext837__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext837__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext837__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE5",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE5",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext837__rt_procedural_node_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext837_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE5",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE5",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext837__rt_quad_leaf_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext837_RT_QUAD_LEAF_RAY_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext838_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext838_RT_QUAD_LEAF_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext838_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext838";
    metric_set->symbol_name = "Ext838";
    metric_set->hw_config_guid = "317eb78e-5fd5-4c28-8d28-c0b9e7ec3f4c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext838_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext838__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext838__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext838__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext838__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE6",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE6",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext838__rt_procedural_node_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext838_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE6",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE6",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext838__rt_quad_leaf_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext838_RT_QUAD_LEAF_RAY_COUNT_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext839_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext839_RT_QUAD_LEAF_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext839_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext839";
    metric_set->symbol_name = "Ext839";
    metric_set->hw_config_guid = "e92851dc-f040-4f09-8241-78bc01faeb85";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext839_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext839__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext839__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext839__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext839__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE7",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE7",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext839__rt_procedural_node_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext839_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE7_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE7",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE7",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext839__rt_quad_leaf_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext839_RT_QUAD_LEAF_RAY_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext840_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext840_RT_QUAD_LEAF_RAY_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext840_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext840";
    metric_set->symbol_name = "Ext840";
    metric_set->hw_config_guid = "79e2fa72-7478-4392-bdf7-9b5f13d97dde";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext840_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext840__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext840__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext840__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext840__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE8",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE8",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext840__rt_procedural_node_ray_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext840_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE8_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE8",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE8",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext840__rt_quad_leaf_ray_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext840_RT_QUAD_LEAF_RAY_COUNT_XECORE8_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext841_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext841_RT_QUAD_LEAF_RAY_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext841_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext841";
    metric_set->symbol_name = "Ext841";
    metric_set->hw_config_guid = "8f581530-9676-4f41-9eab-c14b99208ff1";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext841_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext841__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext841__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext841__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext841__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE9",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE9",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext841__rt_procedural_node_ray_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext841_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE9_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE9",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE9",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext841__rt_quad_leaf_ray_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext841_RT_QUAD_LEAF_RAY_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext842_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext842_RT_QUAD_LEAF_RAY_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext842_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext842";
    metric_set->symbol_name = "Ext842";
    metric_set->hw_config_guid = "48da56da-a122-4bde-8004-d5db9d488322";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext842_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext842__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext842__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext842__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext842__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE10",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE10",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext842__rt_procedural_node_ray_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext842_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE10_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE10",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE10",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext842__rt_quad_leaf_ray_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext842_RT_QUAD_LEAF_RAY_COUNT_XECORE10_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext843_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext843_RT_QUAD_LEAF_RAY_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext843_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext843";
    metric_set->symbol_name = "Ext843";
    metric_set->hw_config_guid = "b101af1b-2ecb-4f87-b85f-d3fb1e7d081f";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext843_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext843__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext843__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext843__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext843__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE11",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE11",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext843__rt_procedural_node_ray_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext843_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE11_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE11",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE11",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext843__rt_quad_leaf_ray_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext843_RT_QUAD_LEAF_RAY_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext844_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext844_RT_QUAD_LEAF_RAY_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext844_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext844";
    metric_set->symbol_name = "Ext844";
    metric_set->hw_config_guid = "2cbe2a2f-61bf-4dde-9fa6-89fbe658cbe8";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext844_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext844__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext844__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext844__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext844__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE12",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE12",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext844__rt_procedural_node_ray_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext844_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE12_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE12",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE12",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext844__rt_quad_leaf_ray_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext844_RT_QUAD_LEAF_RAY_COUNT_XECORE12_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext845_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext845_RT_QUAD_LEAF_RAY_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext845_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext845";
    metric_set->symbol_name = "Ext845";
    metric_set->hw_config_guid = "57ac6b30-2145-47c9-a05d-51cde53af72d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext845_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext845__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext845__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext845__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext845__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE13",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE13",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext845__rt_procedural_node_ray_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext845_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE13_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE13",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE13",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext845__rt_quad_leaf_ray_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext845_RT_QUAD_LEAF_RAY_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext846_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext846_RT_QUAD_LEAF_RAY_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext846_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext846";
    metric_set->symbol_name = "Ext846";
    metric_set->hw_config_guid = "4477cd4a-90b5-4ae4-b910-4ffe26ce08eb";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext846_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext846__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext846__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext846__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext846__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE14",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE14",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext846__rt_procedural_node_ray_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext846_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE14_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE14",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE14",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext846__rt_quad_leaf_ray_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext846_RT_QUAD_LEAF_RAY_COUNT_XECORE14_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext847_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext847_RT_QUAD_LEAF_RAY_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext847_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext847";
    metric_set->symbol_name = "Ext847";
    metric_set->hw_config_guid = "9c491ff6-caca-48c7-8f9a-9e2fcdff732d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext847_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext847__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext847__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext847__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext847__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE15",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE15",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext847__rt_procedural_node_ray_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext847_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE15_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE15",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE15",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext847__rt_quad_leaf_ray_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext847_RT_QUAD_LEAF_RAY_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext848_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext848_RT_QUAD_LEAF_RAY_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext848_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext848";
    metric_set->symbol_name = "Ext848";
    metric_set->hw_config_guid = "5d9982c1-e290-475d-8a42-460a08e42b71";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext848_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext848__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext848__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext848__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext848__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE16",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE16",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext848__rt_procedural_node_ray_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext848_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE16_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE16",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE16",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext848__rt_quad_leaf_ray_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext848_RT_QUAD_LEAF_RAY_COUNT_XECORE16_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext849_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext849_RT_QUAD_LEAF_RAY_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext849_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext849";
    metric_set->symbol_name = "Ext849";
    metric_set->hw_config_guid = "86619a01-e374-4120-91c3-77009f623ebf";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext849_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext849__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext849__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext849__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext849__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE17",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE17",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext849__rt_procedural_node_ray_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext849_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE17_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE17",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE17",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext849__rt_quad_leaf_ray_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext849_RT_QUAD_LEAF_RAY_COUNT_XECORE17_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext850_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext850_RT_QUAD_LEAF_RAY_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext850_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext850";
    metric_set->symbol_name = "Ext850";
    metric_set->hw_config_guid = "0bd94d4e-4ad7-4fb3-bc31-5a602fb2712a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext850_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext850__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext850__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext850__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext850__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE18",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE18",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext850__rt_procedural_node_ray_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext850_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE18_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE18",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE18",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext850__rt_quad_leaf_ray_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext850_RT_QUAD_LEAF_RAY_COUNT_XECORE18_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext851_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext851_RT_QUAD_LEAF_RAY_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext851_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext851";
    metric_set->symbol_name = "Ext851";
    metric_set->hw_config_guid = "ce2ff90c-1370-44ef-8cf4-00af4b13faa5";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext851_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext851__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext851__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext851__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext851__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE19",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE19",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext851__rt_procedural_node_ray_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext851_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE19_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE19",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE19",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext851__rt_quad_leaf_ray_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext851_RT_QUAD_LEAF_RAY_COUNT_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext852_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext852_RT_QUAD_LEAF_RAY_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext852_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext852";
    metric_set->symbol_name = "Ext852";
    metric_set->hw_config_guid = "33a19e51-f39f-4933-8aa7-a475e82a38e0";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext852_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext852__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext852__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext852__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext852__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE20",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE20",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext852__rt_procedural_node_ray_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext852_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE20_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE20",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE20",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext852__rt_quad_leaf_ray_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext852_RT_QUAD_LEAF_RAY_COUNT_XECORE20_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext853_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext853_RT_QUAD_LEAF_RAY_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext853_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext853";
    metric_set->symbol_name = "Ext853";
    metric_set->hw_config_guid = "cb81b489-bf38-423d-b4c6-b43360549140";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext853_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext853__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext853__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext853__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext853__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE21",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE21",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext853__rt_procedural_node_ray_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext853_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE21_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE21",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE21",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext853__rt_quad_leaf_ray_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext853_RT_QUAD_LEAF_RAY_COUNT_XECORE21_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext854_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext854_RT_QUAD_LEAF_RAY_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext854_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext854";
    metric_set->symbol_name = "Ext854";
    metric_set->hw_config_guid = "5ed494ff-0fec-4980-960d-897413ec11b9";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext854_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext854__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext854__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext854__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext854__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE22",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE22",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext854__rt_procedural_node_ray_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext854_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE22_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE22",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE22",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext854__rt_quad_leaf_ray_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext854_RT_QUAD_LEAF_RAY_COUNT_XECORE22_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext855_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext855_RT_QUAD_LEAF_RAY_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext855_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext855";
    metric_set->symbol_name = "Ext855";
    metric_set->hw_config_guid = "bc52aa18-e2ae-4254-ac8a-15c8b90f4e5b";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext855_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext855__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext855__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext855__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext855__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE23",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE23",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext855__rt_procedural_node_ray_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext855_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE23_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE23",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE23",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext855__rt_quad_leaf_ray_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext855_RT_QUAD_LEAF_RAY_COUNT_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext856_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext856_RT_QUAD_LEAF_RAY_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext856_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext856";
    metric_set->symbol_name = "Ext856";
    metric_set->hw_config_guid = "fe9d46b1-9ef7-4381-bea4-cd258cd0476f";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext856_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext856__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext856__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext856__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext856__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE24",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE24",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext856__rt_procedural_node_ray_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext856_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE24_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE24",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE24",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext856__rt_quad_leaf_ray_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext856_RT_QUAD_LEAF_RAY_COUNT_XECORE24_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext857_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext857_RT_QUAD_LEAF_RAY_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext857_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext857";
    metric_set->symbol_name = "Ext857";
    metric_set->hw_config_guid = "eac16312-bd15-4486-aa9a-7430b13ec682";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext857_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext857__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext857__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext857__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext857__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE25",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE25",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext857__rt_procedural_node_ray_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext857_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE25_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE25",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE25",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext857__rt_quad_leaf_ray_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext857_RT_QUAD_LEAF_RAY_COUNT_XECORE25_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext858_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext858_RT_QUAD_LEAF_RAY_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext858_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext858";
    metric_set->symbol_name = "Ext858";
    metric_set->hw_config_guid = "6ace67c0-1c29-46ea-ae7a-63591d19d94d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext858_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext858__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext858__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext858__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext858__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE26",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE26",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext858__rt_procedural_node_ray_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext858_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE26_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE26",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE26",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext858__rt_quad_leaf_ray_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext858_RT_QUAD_LEAF_RAY_COUNT_XECORE26_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext859_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext859_RT_QUAD_LEAF_RAY_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext859_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext859";
    metric_set->symbol_name = "Ext859";
    metric_set->hw_config_guid = "21ade297-b5e4-444d-8e59-8aebc60d9d8f";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext859_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext859__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext859__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext859__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext859__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE27",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE27",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext859__rt_procedural_node_ray_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext859_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE27_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE27",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE27",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext859__rt_quad_leaf_ray_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext859_RT_QUAD_LEAF_RAY_COUNT_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext860_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext860_RT_QUAD_LEAF_RAY_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext860_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext860";
    metric_set->symbol_name = "Ext860";
    metric_set->hw_config_guid = "143bd38c-0888-4f91-8d74-56a4fb91aaa4";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext860_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext860__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext860__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext860__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext860__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE28",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE28",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext860__rt_procedural_node_ray_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext860_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE28_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE28",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE28",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext860__rt_quad_leaf_ray_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext860_RT_QUAD_LEAF_RAY_COUNT_XECORE28_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext861_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext861_RT_QUAD_LEAF_RAY_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext861_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext861";
    metric_set->symbol_name = "Ext861";
    metric_set->hw_config_guid = "a7c3ffb6-6925-4fed-88a7-5d06c1d20291";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext861_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext861__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext861__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext861__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext861__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE29",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE29",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext861__rt_procedural_node_ray_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext861_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE29_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE29",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE29",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext861__rt_quad_leaf_ray_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext861_RT_QUAD_LEAF_RAY_COUNT_XECORE29_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext862_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext862_RT_QUAD_LEAF_RAY_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext862_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext862";
    metric_set->symbol_name = "Ext862";
    metric_set->hw_config_guid = "e3c34149-03bc-4d72-8477-261483c6b40e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext862_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext862__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext862__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext862__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext862__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE30",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE30",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext862__rt_procedural_node_ray_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext862_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE30_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE30",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE30",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext862__rt_quad_leaf_ray_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext862_RT_QUAD_LEAF_RAY_COUNT_XECORE30_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext863_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext863_RT_QUAD_LEAF_RAY_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext863_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext863";
    metric_set->symbol_name = "Ext863";
    metric_set->hw_config_guid = "0b4dff70-5115-468b-8dcc-e6e21b9468ee";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext863_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext863__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext863__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext863__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext863__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE31",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE31",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext863__rt_procedural_node_ray_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext863_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE31_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE31",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE31",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext863__rt_quad_leaf_ray_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext863_RT_QUAD_LEAF_RAY_COUNT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext864_RT_BVH_CACHE_MISS_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext864_RT_BVH_CACHE_MISS_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext864_RT_BVH_CACHE_MISS_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext864_RT_BVH_CACHE_MISS_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext864_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext864";
    metric_set->symbol_name = "Ext864";
    metric_set->hw_config_guid = "85869032-aa5e-4109-baff-f124584720c8";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext864_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext864__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext864__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext864__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext864__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT BVH CACHE MISS XECORE0",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE0",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext864__rt_bvh_cache_miss_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext864_RT_BVH_CACHE_MISS_XECORE0_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE1",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE1",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext864__rt_bvh_cache_miss_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext864_RT_BVH_CACHE_MISS_XECORE1_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE2",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE2",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext864__rt_bvh_cache_miss_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext864_RT_BVH_CACHE_MISS_XECORE2_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE3",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE3",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext864__rt_bvh_cache_miss_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext864_RT_BVH_CACHE_MISS_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext865_RT_BVH_CACHE_MISS_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext865_RT_BVH_CACHE_MISS_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext865_RT_BVH_CACHE_MISS_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext865_RT_BVH_CACHE_MISS_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext865_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext865";
    metric_set->symbol_name = "Ext865";
    metric_set->hw_config_guid = "5dd2de9a-2dc8-4f38-8aee-48d720ee1d08";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext865_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext865__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext865__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext865__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext865__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT BVH CACHE MISS XECORE4",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE4",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext865__rt_bvh_cache_miss_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext865_RT_BVH_CACHE_MISS_XECORE4_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE5",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE5",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext865__rt_bvh_cache_miss_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext865_RT_BVH_CACHE_MISS_XECORE5_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE6",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE6",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext865__rt_bvh_cache_miss_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext865_RT_BVH_CACHE_MISS_XECORE6_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE7",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE7",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext865__rt_bvh_cache_miss_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext865_RT_BVH_CACHE_MISS_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext866_RT_BVH_CACHE_MISS_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext866_RT_BVH_CACHE_MISS_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext866_RT_BVH_CACHE_MISS_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext866_RT_BVH_CACHE_MISS_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext866_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext866";
    metric_set->symbol_name = "Ext866";
    metric_set->hw_config_guid = "16098b83-88a3-451d-8c1e-f2b92ef1c2a5";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext866_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext866__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext866__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext866__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext866__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT BVH CACHE MISS XECORE10",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE10",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext866__rt_bvh_cache_miss_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext866_RT_BVH_CACHE_MISS_XECORE10_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE11",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE11",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext866__rt_bvh_cache_miss_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext866_RT_BVH_CACHE_MISS_XECORE11_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE8",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE8",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext866__rt_bvh_cache_miss_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext866_RT_BVH_CACHE_MISS_XECORE8_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE9",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE9",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext866__rt_bvh_cache_miss_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext866_RT_BVH_CACHE_MISS_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext867_RT_BVH_CACHE_MISS_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext867_RT_BVH_CACHE_MISS_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext867_RT_BVH_CACHE_MISS_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext867_RT_BVH_CACHE_MISS_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext867_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext867";
    metric_set->symbol_name = "Ext867";
    metric_set->hw_config_guid = "12e157ed-ca6a-4cc2-a3e7-5c35b9238f54";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext867_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext867__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext867__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext867__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext867__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT BVH CACHE MISS XECORE12",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE12",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext867__rt_bvh_cache_miss_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext867_RT_BVH_CACHE_MISS_XECORE12_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE13",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE13",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext867__rt_bvh_cache_miss_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext867_RT_BVH_CACHE_MISS_XECORE13_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE14",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE14",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext867__rt_bvh_cache_miss_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext867_RT_BVH_CACHE_MISS_XECORE14_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE15",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE15",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext867__rt_bvh_cache_miss_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext867_RT_BVH_CACHE_MISS_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext868_RT_BVH_CACHE_MISS_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext868_RT_BVH_CACHE_MISS_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext868_RT_BVH_CACHE_MISS_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext868_RT_BVH_CACHE_MISS_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext868_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext868";
    metric_set->symbol_name = "Ext868";
    metric_set->hw_config_guid = "7bb5d7df-919a-4c1c-9029-5b34dec3b0a1";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext868_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext868__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext868__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext868__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext868__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT BVH CACHE MISS XECORE16",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE16",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext868__rt_bvh_cache_miss_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext868_RT_BVH_CACHE_MISS_XECORE16_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE17",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE17",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext868__rt_bvh_cache_miss_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext868_RT_BVH_CACHE_MISS_XECORE17_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE18",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE18",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext868__rt_bvh_cache_miss_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext868_RT_BVH_CACHE_MISS_XECORE18_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE19",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE19",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext868__rt_bvh_cache_miss_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext868_RT_BVH_CACHE_MISS_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext869_RT_BVH_CACHE_MISS_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext869_RT_BVH_CACHE_MISS_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext869_RT_BVH_CACHE_MISS_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext869_RT_BVH_CACHE_MISS_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext869_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext869";
    metric_set->symbol_name = "Ext869";
    metric_set->hw_config_guid = "f090fb53-717d-4bcc-8ac0-515ef2e9e732";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext869_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext869__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext869__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext869__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext869__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT BVH CACHE MISS XECORE20",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE20",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext869__rt_bvh_cache_miss_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext869_RT_BVH_CACHE_MISS_XECORE20_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE21",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE21",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext869__rt_bvh_cache_miss_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext869_RT_BVH_CACHE_MISS_XECORE21_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE22",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE22",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext869__rt_bvh_cache_miss_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext869_RT_BVH_CACHE_MISS_XECORE22_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE23",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE23",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext869__rt_bvh_cache_miss_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext869_RT_BVH_CACHE_MISS_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext870_RT_BVH_CACHE_MISS_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext870_RT_BVH_CACHE_MISS_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext870_RT_BVH_CACHE_MISS_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext870_RT_BVH_CACHE_MISS_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext870_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext870";
    metric_set->symbol_name = "Ext870";
    metric_set->hw_config_guid = "aaeae265-2220-4838-947e-98558d911858";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext870_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext870__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext870__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext870__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext870__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT BVH CACHE MISS XECORE24",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE24",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext870__rt_bvh_cache_miss_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext870_RT_BVH_CACHE_MISS_XECORE24_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE25",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE25",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext870__rt_bvh_cache_miss_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext870_RT_BVH_CACHE_MISS_XECORE25_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE26",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE26",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext870__rt_bvh_cache_miss_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext870_RT_BVH_CACHE_MISS_XECORE26_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE27",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE27",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext870__rt_bvh_cache_miss_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext870_RT_BVH_CACHE_MISS_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext871_RT_BVH_CACHE_MISS_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext871_RT_BVH_CACHE_MISS_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext871_RT_BVH_CACHE_MISS_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext871_RT_BVH_CACHE_MISS_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext871_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext871";
    metric_set->symbol_name = "Ext871";
    metric_set->hw_config_guid = "662d8774-3e66-4c9b-b5e2-5be8747980d8";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext871_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext871__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext871__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext871__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext871__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT BVH CACHE MISS XECORE28",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE28",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext871__rt_bvh_cache_miss_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext871_RT_BVH_CACHE_MISS_XECORE28_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE29",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE29",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext871__rt_bvh_cache_miss_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext871_RT_BVH_CACHE_MISS_XECORE29_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE30",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE30",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext871__rt_bvh_cache_miss_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext871_RT_BVH_CACHE_MISS_XECORE30_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE31",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE31",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext871__rt_bvh_cache_miss_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt3_ext871_RT_BVH_CACHE_MISS_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext872_SLM_ACCESS_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext872_SLM_ACCESS_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext872_SLM_ACCESS_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext872_SLM_ACCESS_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext872_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext872";
    metric_set->symbol_name = "Ext872";
    metric_set->hw_config_guid = "2c69a291-9d76-46de-9db5-ceab2dccda57";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext872_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext872__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext872__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext872__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext872__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM ACCESS COUNT XECORE0",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE0",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext872__slm_access_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext872_SLM_ACCESS_COUNT_XECORE0_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE1",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE1",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext872__slm_access_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext872_SLM_ACCESS_COUNT_XECORE1_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE2",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE2",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext872__slm_access_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext872_SLM_ACCESS_COUNT_XECORE2_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE3",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE3",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext872__slm_access_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext872_SLM_ACCESS_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext873_SLM_ACCESS_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext873_SLM_ACCESS_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext873_SLM_ACCESS_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext873_SLM_ACCESS_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext873_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext873";
    metric_set->symbol_name = "Ext873";
    metric_set->hw_config_guid = "0f86e589-8993-42a0-b344-e2b667565ede";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext873_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext873__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext873__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext873__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext873__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM ACCESS COUNT XECORE4",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE4",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext873__slm_access_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext873_SLM_ACCESS_COUNT_XECORE4_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE5",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE5",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext873__slm_access_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext873_SLM_ACCESS_COUNT_XECORE5_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE6",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE6",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext873__slm_access_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext873_SLM_ACCESS_COUNT_XECORE6_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE7",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE7",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext873__slm_access_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext873_SLM_ACCESS_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext874_SLM_ACCESS_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext874_SLM_ACCESS_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext874_SLM_ACCESS_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext874_SLM_ACCESS_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext874_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext874";
    metric_set->symbol_name = "Ext874";
    metric_set->hw_config_guid = "d11c464b-ef9a-4da5-9322-1e57cb0e0897";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext874_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext874__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext874__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext874__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext874__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM ACCESS COUNT XECORE10",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE10",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext874__slm_access_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext874_SLM_ACCESS_COUNT_XECORE10_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE11",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE11",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext874__slm_access_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext874_SLM_ACCESS_COUNT_XECORE11_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE8",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE8",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext874__slm_access_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext874_SLM_ACCESS_COUNT_XECORE8_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE9",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE9",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext874__slm_access_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext874_SLM_ACCESS_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext875_SLM_ACCESS_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext875_SLM_ACCESS_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext875_SLM_ACCESS_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext875_SLM_ACCESS_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext875_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext875";
    metric_set->symbol_name = "Ext875";
    metric_set->hw_config_guid = "49a40c7a-1037-479e-a24c-4e9f4e8ff55a";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext875_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext875__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext875__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext875__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext875__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM ACCESS COUNT XECORE12",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE12",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext875__slm_access_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext875_SLM_ACCESS_COUNT_XECORE12_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE13",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE13",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext875__slm_access_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext875_SLM_ACCESS_COUNT_XECORE13_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE14",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE14",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext875__slm_access_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext875_SLM_ACCESS_COUNT_XECORE14_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE15",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE15",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext875__slm_access_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext875_SLM_ACCESS_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext876_SLM_ACCESS_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext876_SLM_ACCESS_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext876_SLM_ACCESS_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext876_SLM_ACCESS_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext876_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext876";
    metric_set->symbol_name = "Ext876";
    metric_set->hw_config_guid = "80397a0b-40b5-4d6f-bc14-297a9094c5ca";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext876_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext876__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext876__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext876__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext876__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM ACCESS COUNT XECORE16",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE16",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext876__slm_access_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext876_SLM_ACCESS_COUNT_XECORE16_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE17",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE17",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext876__slm_access_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext876_SLM_ACCESS_COUNT_XECORE17_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE18",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE18",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext876__slm_access_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext876_SLM_ACCESS_COUNT_XECORE18_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE19",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE19",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext876__slm_access_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext876_SLM_ACCESS_COUNT_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext877_SLM_ACCESS_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext877_SLM_ACCESS_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext877_SLM_ACCESS_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext877_SLM_ACCESS_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext877_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext877";
    metric_set->symbol_name = "Ext877";
    metric_set->hw_config_guid = "4dd595cc-86a2-4abf-bda8-aaebda8bebe4";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext877_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext877__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext877__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext877__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext877__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM ACCESS COUNT XECORE20",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE20",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext877__slm_access_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext877_SLM_ACCESS_COUNT_XECORE20_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE21",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE21",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext877__slm_access_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext877_SLM_ACCESS_COUNT_XECORE21_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE22",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE22",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext877__slm_access_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext877_SLM_ACCESS_COUNT_XECORE22_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE23",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE23",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext877__slm_access_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext877_SLM_ACCESS_COUNT_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext878_SLM_ACCESS_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext878_SLM_ACCESS_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext878_SLM_ACCESS_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext878_SLM_ACCESS_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext878_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext878";
    metric_set->symbol_name = "Ext878";
    metric_set->hw_config_guid = "4bd452af-bdfc-4d44-a607-3f2b867b5ae5";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext878_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext878__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext878__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext878__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext878__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM ACCESS COUNT XECORE24",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE24",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext878__slm_access_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext878_SLM_ACCESS_COUNT_XECORE24_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE25",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE25",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext878__slm_access_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext878_SLM_ACCESS_COUNT_XECORE25_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE26",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE26",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext878__slm_access_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext878_SLM_ACCESS_COUNT_XECORE26_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE27",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE27",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext878__slm_access_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext878_SLM_ACCESS_COUNT_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext879_SLM_ACCESS_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext879_SLM_ACCESS_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext879_SLM_ACCESS_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext879_SLM_ACCESS_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext879_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext879";
    metric_set->symbol_name = "Ext879";
    metric_set->hw_config_guid = "6793871f-9574-4605-b748-50f227dc8d0d";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext879_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext879__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext879__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext879__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext879__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM ACCESS COUNT XECORE28",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE28",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext879__slm_access_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext879_SLM_ACCESS_COUNT_XECORE28_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE29",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE29",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext879__slm_access_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext879_SLM_ACCESS_COUNT_XECORE29_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE30",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE30",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext879__slm_access_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext879_SLM_ACCESS_COUNT_XECORE30_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE31",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE31",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext879__slm_access_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext879_SLM_ACCESS_COUNT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}


static void
acmgt3_add_ext880_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext880";
    metric_set->symbol_name = "Ext880";
    metric_set->hw_config_guid = "eda73924-faa7-4e99-b942-e571db97ffd9";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext880_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext880__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext880__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 WRITE SQIDI0",
                .symbol_name = "GPU_MEMORY_L3_WRITE_SQIDI0",
                .desc = "Number of GTI memory writes from L3 caused by L3 invalidations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext880__gpu_memory_l3_write_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext880__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext880__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt3_add_ext881_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext881";
    metric_set->symbol_name = "Ext881";
    metric_set->hw_config_guid = "4c4c41af-23de-4ac2-adbc-db69aa7c7a59";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext881_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext881__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext881__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 WRITE SQIDI1",
                .symbol_name = "GPU_MEMORY_L3_WRITE_SQIDI1",
                .desc = "Number of GTI memory writes from L3 caused by L3 invalidations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext881__gpu_memory_l3_write_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext881__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext881__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt3_add_ext882_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext882";
    metric_set->symbol_name = "Ext882";
    metric_set->hw_config_guid = "3d734ca7-99c2-4cc6-a42b-0678c30adafd";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext882_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext882__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext882__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 WRITE SQIDI2",
                .symbol_name = "GPU_MEMORY_L3_WRITE_SQIDI2",
                .desc = "Number of GTI memory writes from L3 caused by L3 invalidations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext882__gpu_memory_l3_write_sqidi2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext882__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext882__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt3_add_ext883_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext883";
    metric_set->symbol_name = "Ext883";
    metric_set->hw_config_guid = "c435cabd-1edf-47e1-a0b8-e952e4144f14";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext883_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext883__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext883__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 WRITE SQIDI3",
                .symbol_name = "GPU_MEMORY_L3_WRITE_SQIDI3",
                .desc = "Number of GTI memory writes from L3 caused by L3 invalidations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext883__gpu_memory_l3_write_sqidi3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext883__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext883__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt3_add_ext884_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext884";
    metric_set->symbol_name = "Ext884";
    metric_set->hw_config_guid = "b51c6d34-8b88-48c1-a88d-d3114cc750a7";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext884_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext884__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext884__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 WRITE SQIDI4",
                .symbol_name = "GPU_MEMORY_L3_WRITE_SQIDI4",
                .desc = "Number of GTI memory writes from L3 caused by L3 invalidations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext884__gpu_memory_l3_write_sqidi4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext884__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext884__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt3_add_ext885_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext885";
    metric_set->symbol_name = "Ext885";
    metric_set->hw_config_guid = "cc13457c-3aef-4c2c-9b3b-d07058268807";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext885_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext885__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext885__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 WRITE SQIDI5",
                .symbol_name = "GPU_MEMORY_L3_WRITE_SQIDI5",
                .desc = "Number of GTI memory writes from L3 caused by L3 invalidations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext885__gpu_memory_l3_write_sqidi5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext885__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext885__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt3_add_ext886_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext886";
    metric_set->symbol_name = "Ext886";
    metric_set->hw_config_guid = "3b526aaf-5919-4a41-ba31-2e6fb7205765";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext886_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext886__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext886__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 WRITE SQIDI6",
                .symbol_name = "GPU_MEMORY_L3_WRITE_SQIDI6",
                .desc = "Number of GTI memory writes from L3 caused by L3 invalidations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext886__gpu_memory_l3_write_sqidi6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext886__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext886__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt3_add_ext887_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext887";
    metric_set->symbol_name = "Ext887";
    metric_set->hw_config_guid = "4e1fdf9d-9a97-45ad-92d5-c4dbf0b6b6c4";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext887_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext887__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext887__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 WRITE SQIDI7",
                .symbol_name = "GPU_MEMORY_L3_WRITE_SQIDI7",
                .desc = "Number of GTI memory writes from L3 caused by L3 invalidations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext887__gpu_memory_l3_write_sqidi7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext887__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext887__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext888_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext888_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext888_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext888_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext888_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext888";
    metric_set->symbol_name = "Ext888";
    metric_set->hw_config_guid = "51d516e5-4f18-4d23-abef-d4fe43d2cedd";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext888_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext888__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext888__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext888__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext888__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE0",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext888__load_store_cache_number_of_bank_access_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext888_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE1",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext888__load_store_cache_number_of_bank_access_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext888_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE2",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext888__load_store_cache_number_of_bank_access_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext888_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE3",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext888__load_store_cache_number_of_bank_access_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext888_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext889_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext889_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext889_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext889_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext889_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext889";
    metric_set->symbol_name = "Ext889";
    metric_set->hw_config_guid = "69746c29-88ae-4e33-9d89-832f961ce4d0";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext889_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext889__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext889__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext889__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext889__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE4",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext889__load_store_cache_number_of_bank_access_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext889_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE5",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext889__load_store_cache_number_of_bank_access_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext889_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE6",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext889__load_store_cache_number_of_bank_access_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext889_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE7",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext889__load_store_cache_number_of_bank_access_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext889_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext890_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext890_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext890_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext890_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext890_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext890";
    metric_set->symbol_name = "Ext890";
    metric_set->hw_config_guid = "3772217c-5bfa-4b4f-8ce6-c1d70e1e7409";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext890_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext890__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext890__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext890__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext890__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE10",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE10",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext890__load_store_cache_number_of_bank_access_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext890_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE10_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE11",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE11",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext890__load_store_cache_number_of_bank_access_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext890_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE11_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE8",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE8",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext890__load_store_cache_number_of_bank_access_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext890_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE8_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE9",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE9",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext890__load_store_cache_number_of_bank_access_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext890_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext891_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext891_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext891_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext891_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext891_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext891";
    metric_set->symbol_name = "Ext891";
    metric_set->hw_config_guid = "f0a9580b-73ae-4ae7-994f-4b6d5d265291";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext891_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext891__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext891__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext891__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext891__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE12",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE12",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext891__load_store_cache_number_of_bank_access_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext891_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE12_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE13",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE13",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext891__load_store_cache_number_of_bank_access_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext891_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE13_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE14",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE14",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext891__load_store_cache_number_of_bank_access_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext891_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE14_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE15",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE15",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext891__load_store_cache_number_of_bank_access_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext891_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext892_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext892_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext892_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext892_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext892_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext892";
    metric_set->symbol_name = "Ext892";
    metric_set->hw_config_guid = "52064d17-d36d-4f45-ab86-8732a72ab376";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext892_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext892__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext892__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext892__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext892__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE16",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE16",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext892__load_store_cache_number_of_bank_access_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext892_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE16_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE17",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE17",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext892__load_store_cache_number_of_bank_access_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext892_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE17_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE18",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE18",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext892__load_store_cache_number_of_bank_access_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext892_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE18_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE19",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE19",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext892__load_store_cache_number_of_bank_access_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext892_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext893_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext893_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext893_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext893_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext893_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext893";
    metric_set->symbol_name = "Ext893";
    metric_set->hw_config_guid = "4b2771bf-21cc-4d4f-b0c5-70b3ff4144d3";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext893_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext893__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext893__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext893__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext893__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE20",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE20",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext893__load_store_cache_number_of_bank_access_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext893_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE20_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE21",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE21",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext893__load_store_cache_number_of_bank_access_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext893_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE21_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE22",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE22",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext893__load_store_cache_number_of_bank_access_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext893_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE22_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE23",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE23",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext893__load_store_cache_number_of_bank_access_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext893_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext894_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext894_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext894_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext894_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext894_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext894";
    metric_set->symbol_name = "Ext894";
    metric_set->hw_config_guid = "d028b5f8-993c-4c35-9d86-2601fa6a78e9";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext894_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext894__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext894__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext894__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext894__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE24",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE24",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext894__load_store_cache_number_of_bank_access_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext894_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE24_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE25",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE25",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext894__load_store_cache_number_of_bank_access_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext894_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE25_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE26",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE26",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext894__load_store_cache_number_of_bank_access_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext894_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE26_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE27",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE27",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext894__load_store_cache_number_of_bank_access_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext894_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext895_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext895_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext895_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext895_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext895_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext895";
    metric_set->symbol_name = "Ext895";
    metric_set->hw_config_guid = "1cd63d28-50ed-4c69-8683-44eba28275b6";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext895_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext895__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext895__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext895__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext895__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE28",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE28",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext895__load_store_cache_number_of_bank_access_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext895_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE28_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE29",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE29",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext895__load_store_cache_number_of_bank_access_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext895_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE29_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE30",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE30",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext895__load_store_cache_number_of_bank_access_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext895_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE30_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE31",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE31",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext895__load_store_cache_number_of_bank_access_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext895_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt3_ext896_ICACHE_HIT_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext896_ICACHE_HIT_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext896_ICACHE_HIT_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext896_ICACHE_HIT_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext896_ICACHE_HIT_BANK0_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext896_ICACHE_HIT_BANK0_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext896_ICACHE_HIT_BANK0_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext896_ICACHE_HIT_BANK0_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext896_ICACHE_MISS_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext896_ICACHE_MISS_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext896_ICACHE_MISS_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext896_ICACHE_MISS_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext896_ICACHE_MISS_BANK0_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext896_ICACHE_MISS_BANK0_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext896_ICACHE_MISS_BANK0_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext896_ICACHE_MISS_BANK0_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext896_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext896";
    metric_set->symbol_name = "Ext896";
    metric_set->hw_config_guid = "ebd6f029-7260-4c80-9698-f18439c74959";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext896_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext896__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext896__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext896__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext896__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK0 XECORE0",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE0",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext896__icache_hit_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext896_ICACHE_HIT_BANK0_XECORE0_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE1",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE1",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext896__icache_hit_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext896_ICACHE_HIT_BANK0_XECORE1_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE2",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE2",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext896__icache_hit_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext896_ICACHE_HIT_BANK0_XECORE2_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE3",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE3",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext896__icache_hit_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext896_ICACHE_HIT_BANK0_XECORE3_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE4",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE4",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext896__icache_hit_bank0_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext896_ICACHE_HIT_BANK0_XECORE4_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE5",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE5",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext896__icache_hit_bank0_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext896_ICACHE_HIT_BANK0_XECORE5_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE6",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE6",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext896__icache_hit_bank0_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext896_ICACHE_HIT_BANK0_XECORE6_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE7",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE7",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext896__icache_hit_bank0_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext896_ICACHE_HIT_BANK0_XECORE7_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE0",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE0",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext896__icache_miss_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext896_ICACHE_MISS_BANK0_XECORE0_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE1",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE1",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext896__icache_miss_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext896_ICACHE_MISS_BANK0_XECORE1_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE2",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE2",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext896__icache_miss_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext896_ICACHE_MISS_BANK0_XECORE2_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE3",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE3",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext896__icache_miss_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext896_ICACHE_MISS_BANK0_XECORE3_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE4",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE4",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext896__icache_miss_bank0_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext896_ICACHE_MISS_BANK0_XECORE4_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE5",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE5",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext896__icache_miss_bank0_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext896_ICACHE_MISS_BANK0_XECORE5_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE6",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE6",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext896__icache_miss_bank0_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext896_ICACHE_MISS_BANK0_XECORE6_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE7",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE7",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext896__icache_miss_bank0_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext896_ICACHE_MISS_BANK0_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext897_ICACHE_HIT_BANK0_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext897_ICACHE_HIT_BANK0_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext897_ICACHE_HIT_BANK0_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext897_ICACHE_HIT_BANK0_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext897_ICACHE_HIT_BANK0_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext897_ICACHE_HIT_BANK0_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext897_ICACHE_HIT_BANK0_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext897_ICACHE_HIT_BANK0_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext897_ICACHE_MISS_BANK0_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext897_ICACHE_MISS_BANK0_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext897_ICACHE_MISS_BANK0_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext897_ICACHE_MISS_BANK0_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext897_ICACHE_MISS_BANK0_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext897_ICACHE_MISS_BANK0_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext897_ICACHE_MISS_BANK0_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext897_ICACHE_MISS_BANK0_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext897_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext897";
    metric_set->symbol_name = "Ext897";
    metric_set->hw_config_guid = "4fef4fe4-17ad-4869-bef4-2ebdebff9f9d";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext897_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext897__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext897__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext897__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext897__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK0 XECORE10",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE10",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext897__icache_hit_bank0_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext897_ICACHE_HIT_BANK0_XECORE10_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE11",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE11",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext897__icache_hit_bank0_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext897_ICACHE_HIT_BANK0_XECORE11_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE12",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE12",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext897__icache_hit_bank0_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext897_ICACHE_HIT_BANK0_XECORE12_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE13",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE13",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext897__icache_hit_bank0_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext897_ICACHE_HIT_BANK0_XECORE13_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE14",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE14",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext897__icache_hit_bank0_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext897_ICACHE_HIT_BANK0_XECORE14_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE15",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE15",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext897__icache_hit_bank0_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext897_ICACHE_HIT_BANK0_XECORE15_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE8",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE8",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext897__icache_hit_bank0_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext897_ICACHE_HIT_BANK0_XECORE8_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE9",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE9",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext897__icache_hit_bank0_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext897_ICACHE_HIT_BANK0_XECORE9_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE10",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE10",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext897__icache_miss_bank0_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext897_ICACHE_MISS_BANK0_XECORE10_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE11",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE11",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext897__icache_miss_bank0_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext897_ICACHE_MISS_BANK0_XECORE11_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE12",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE12",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext897__icache_miss_bank0_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext897_ICACHE_MISS_BANK0_XECORE12_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE13",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE13",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext897__icache_miss_bank0_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext897_ICACHE_MISS_BANK0_XECORE13_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE14",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE14",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext897__icache_miss_bank0_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext897_ICACHE_MISS_BANK0_XECORE14_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE15",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE15",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext897__icache_miss_bank0_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext897_ICACHE_MISS_BANK0_XECORE15_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE8",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE8",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext897__icache_miss_bank0_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext897_ICACHE_MISS_BANK0_XECORE8_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE9",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE9",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext897__icache_miss_bank0_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext897_ICACHE_MISS_BANK0_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext898_ICACHE_HIT_BANK0_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext898_ICACHE_HIT_BANK0_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext898_ICACHE_HIT_BANK0_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext898_ICACHE_HIT_BANK0_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext898_ICACHE_HIT_BANK0_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext898_ICACHE_HIT_BANK0_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext898_ICACHE_HIT_BANK0_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext898_ICACHE_HIT_BANK0_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext898_ICACHE_MISS_BANK0_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext898_ICACHE_MISS_BANK0_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext898_ICACHE_MISS_BANK0_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext898_ICACHE_MISS_BANK0_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext898_ICACHE_MISS_BANK0_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext898_ICACHE_MISS_BANK0_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext898_ICACHE_MISS_BANK0_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext898_ICACHE_MISS_BANK0_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext898_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext898";
    metric_set->symbol_name = "Ext898";
    metric_set->hw_config_guid = "cca4086b-edba-4819-ab17-70039adaa90f";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext898_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext898__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext898__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext898__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext898__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK0 XECORE16",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE16",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext898__icache_hit_bank0_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext898_ICACHE_HIT_BANK0_XECORE16_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE17",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE17",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext898__icache_hit_bank0_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext898_ICACHE_HIT_BANK0_XECORE17_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE18",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE18",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext898__icache_hit_bank0_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext898_ICACHE_HIT_BANK0_XECORE18_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE19",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE19",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext898__icache_hit_bank0_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext898_ICACHE_HIT_BANK0_XECORE19_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE20",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE20",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext898__icache_hit_bank0_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext898_ICACHE_HIT_BANK0_XECORE20_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE21",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE21",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext898__icache_hit_bank0_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext898_ICACHE_HIT_BANK0_XECORE21_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE22",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE22",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext898__icache_hit_bank0_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext898_ICACHE_HIT_BANK0_XECORE22_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE23",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE23",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext898__icache_hit_bank0_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext898_ICACHE_HIT_BANK0_XECORE23_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE16",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE16",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext898__icache_miss_bank0_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext898_ICACHE_MISS_BANK0_XECORE16_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE17",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE17",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext898__icache_miss_bank0_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext898_ICACHE_MISS_BANK0_XECORE17_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE18",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE18",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext898__icache_miss_bank0_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext898_ICACHE_MISS_BANK0_XECORE18_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE19",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE19",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext898__icache_miss_bank0_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext898_ICACHE_MISS_BANK0_XECORE19_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE20",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE20",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext898__icache_miss_bank0_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext898_ICACHE_MISS_BANK0_XECORE20_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE21",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE21",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext898__icache_miss_bank0_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext898_ICACHE_MISS_BANK0_XECORE21_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE22",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE22",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext898__icache_miss_bank0_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext898_ICACHE_MISS_BANK0_XECORE22_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE23",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE23",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext898__icache_miss_bank0_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext898_ICACHE_MISS_BANK0_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext899_ICACHE_HIT_BANK0_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext899_ICACHE_HIT_BANK0_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext899_ICACHE_HIT_BANK0_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext899_ICACHE_HIT_BANK0_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext899_ICACHE_HIT_BANK0_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext899_ICACHE_HIT_BANK0_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext899_ICACHE_HIT_BANK0_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext899_ICACHE_HIT_BANK0_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext899_ICACHE_MISS_BANK0_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext899_ICACHE_MISS_BANK0_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext899_ICACHE_MISS_BANK0_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext899_ICACHE_MISS_BANK0_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext899_ICACHE_MISS_BANK0_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext899_ICACHE_MISS_BANK0_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext899_ICACHE_MISS_BANK0_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext899_ICACHE_MISS_BANK0_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext899_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext899";
    metric_set->symbol_name = "Ext899";
    metric_set->hw_config_guid = "de978459-938a-4d54-8a6f-0860fba80b44";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext899_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext899__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext899__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext899__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext899__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK0 XECORE24",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE24",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext899__icache_hit_bank0_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext899_ICACHE_HIT_BANK0_XECORE24_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE25",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE25",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext899__icache_hit_bank0_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext899_ICACHE_HIT_BANK0_XECORE25_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE26",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE26",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext899__icache_hit_bank0_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext899_ICACHE_HIT_BANK0_XECORE26_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE27",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE27",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext899__icache_hit_bank0_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext899_ICACHE_HIT_BANK0_XECORE27_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE28",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE28",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext899__icache_hit_bank0_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext899_ICACHE_HIT_BANK0_XECORE28_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE29",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE29",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext899__icache_hit_bank0_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext899_ICACHE_HIT_BANK0_XECORE29_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE30",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE30",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext899__icache_hit_bank0_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext899_ICACHE_HIT_BANK0_XECORE30_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE31",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE31",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext899__icache_hit_bank0_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext899_ICACHE_HIT_BANK0_XECORE31_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE24",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE24",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext899__icache_miss_bank0_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext899_ICACHE_MISS_BANK0_XECORE24_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE25",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE25",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext899__icache_miss_bank0_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext899_ICACHE_MISS_BANK0_XECORE25_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE26",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE26",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext899__icache_miss_bank0_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext899_ICACHE_MISS_BANK0_XECORE26_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE27",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE27",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext899__icache_miss_bank0_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext899_ICACHE_MISS_BANK0_XECORE27_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE28",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE28",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext899__icache_miss_bank0_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext899_ICACHE_MISS_BANK0_XECORE28_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE29",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE29",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext899__icache_miss_bank0_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext899_ICACHE_MISS_BANK0_XECORE29_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE30",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE30",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext899__icache_miss_bank0_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext899_ICACHE_MISS_BANK0_XECORE30_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE31",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE31",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext899__icache_miss_bank0_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext899_ICACHE_MISS_BANK0_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext900_ICACHE_HIT_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext900_ICACHE_HIT_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext900_ICACHE_HIT_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext900_ICACHE_HIT_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext900_ICACHE_HIT_BANK1_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext900_ICACHE_HIT_BANK1_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext900_ICACHE_HIT_BANK1_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext900_ICACHE_HIT_BANK1_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext900_ICACHE_MISS_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext900_ICACHE_MISS_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext900_ICACHE_MISS_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext900_ICACHE_MISS_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext900_ICACHE_MISS_BANK1_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext900_ICACHE_MISS_BANK1_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext900_ICACHE_MISS_BANK1_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext900_ICACHE_MISS_BANK1_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext900_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext900";
    metric_set->symbol_name = "Ext900";
    metric_set->hw_config_guid = "31c70c2d-ab25-4333-8242-c980e65fe83b";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext900_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext900__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext900__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext900__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext900__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK1 XECORE0",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE0",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext900__icache_hit_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext900_ICACHE_HIT_BANK1_XECORE0_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE1",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE1",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext900__icache_hit_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext900_ICACHE_HIT_BANK1_XECORE1_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE2",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE2",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext900__icache_hit_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext900_ICACHE_HIT_BANK1_XECORE2_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE3",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE3",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext900__icache_hit_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext900_ICACHE_HIT_BANK1_XECORE3_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE4",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE4",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext900__icache_hit_bank1_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext900_ICACHE_HIT_BANK1_XECORE4_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE5",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE5",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext900__icache_hit_bank1_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext900_ICACHE_HIT_BANK1_XECORE5_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE6",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE6",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext900__icache_hit_bank1_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext900_ICACHE_HIT_BANK1_XECORE6_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE7",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE7",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext900__icache_hit_bank1_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext900_ICACHE_HIT_BANK1_XECORE7_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE0",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE0",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext900__icache_miss_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext900_ICACHE_MISS_BANK1_XECORE0_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE1",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE1",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext900__icache_miss_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext900_ICACHE_MISS_BANK1_XECORE1_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE2",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE2",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext900__icache_miss_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext900_ICACHE_MISS_BANK1_XECORE2_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE3",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE3",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext900__icache_miss_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext900_ICACHE_MISS_BANK1_XECORE3_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE4",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE4",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext900__icache_miss_bank1_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext900_ICACHE_MISS_BANK1_XECORE4_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE5",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE5",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext900__icache_miss_bank1_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext900_ICACHE_MISS_BANK1_XECORE5_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE6",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE6",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext900__icache_miss_bank1_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext900_ICACHE_MISS_BANK1_XECORE6_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE7",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE7",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext900__icache_miss_bank1_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext900_ICACHE_MISS_BANK1_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext901_ICACHE_HIT_BANK1_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext901_ICACHE_HIT_BANK1_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext901_ICACHE_HIT_BANK1_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext901_ICACHE_HIT_BANK1_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext901_ICACHE_HIT_BANK1_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext901_ICACHE_HIT_BANK1_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext901_ICACHE_HIT_BANK1_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext901_ICACHE_HIT_BANK1_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext901_ICACHE_MISS_BANK1_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext901_ICACHE_MISS_BANK1_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext901_ICACHE_MISS_BANK1_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext901_ICACHE_MISS_BANK1_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext901_ICACHE_MISS_BANK1_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext901_ICACHE_MISS_BANK1_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext901_ICACHE_MISS_BANK1_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext901_ICACHE_MISS_BANK1_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext901_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext901";
    metric_set->symbol_name = "Ext901";
    metric_set->hw_config_guid = "bcf7ff4e-50dc-45f7-8c63-d649dc126717";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext901_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext901__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext901__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext901__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext901__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK1 XECORE10",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE10",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext901__icache_hit_bank1_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext901_ICACHE_HIT_BANK1_XECORE10_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE11",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE11",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext901__icache_hit_bank1_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext901_ICACHE_HIT_BANK1_XECORE11_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE12",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE12",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext901__icache_hit_bank1_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext901_ICACHE_HIT_BANK1_XECORE12_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE13",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE13",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext901__icache_hit_bank1_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext901_ICACHE_HIT_BANK1_XECORE13_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE14",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE14",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext901__icache_hit_bank1_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext901_ICACHE_HIT_BANK1_XECORE14_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE15",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE15",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext901__icache_hit_bank1_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext901_ICACHE_HIT_BANK1_XECORE15_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE8",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE8",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext901__icache_hit_bank1_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext901_ICACHE_HIT_BANK1_XECORE8_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE9",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE9",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext901__icache_hit_bank1_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext901_ICACHE_HIT_BANK1_XECORE9_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE10",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE10",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext901__icache_miss_bank1_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext901_ICACHE_MISS_BANK1_XECORE10_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE11",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE11",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext901__icache_miss_bank1_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext901_ICACHE_MISS_BANK1_XECORE11_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE12",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE12",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext901__icache_miss_bank1_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext901_ICACHE_MISS_BANK1_XECORE12_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE13",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE13",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext901__icache_miss_bank1_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext901_ICACHE_MISS_BANK1_XECORE13_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE14",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE14",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext901__icache_miss_bank1_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext901_ICACHE_MISS_BANK1_XECORE14_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE15",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE15",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext901__icache_miss_bank1_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext901_ICACHE_MISS_BANK1_XECORE15_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE8",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE8",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext901__icache_miss_bank1_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext901_ICACHE_MISS_BANK1_XECORE8_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE9",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE9",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext901__icache_miss_bank1_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext901_ICACHE_MISS_BANK1_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext902_ICACHE_HIT_BANK1_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext902_ICACHE_HIT_BANK1_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext902_ICACHE_HIT_BANK1_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext902_ICACHE_HIT_BANK1_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext902_ICACHE_HIT_BANK1_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext902_ICACHE_HIT_BANK1_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext902_ICACHE_HIT_BANK1_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext902_ICACHE_HIT_BANK1_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext902_ICACHE_MISS_BANK1_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext902_ICACHE_MISS_BANK1_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext902_ICACHE_MISS_BANK1_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext902_ICACHE_MISS_BANK1_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext902_ICACHE_MISS_BANK1_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext902_ICACHE_MISS_BANK1_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext902_ICACHE_MISS_BANK1_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext902_ICACHE_MISS_BANK1_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext902_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext902";
    metric_set->symbol_name = "Ext902";
    metric_set->hw_config_guid = "c79fc1e5-c7b5-4dae-ba39-4861365060f3";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext902_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext902__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext902__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext902__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext902__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK1 XECORE16",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE16",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext902__icache_hit_bank1_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext902_ICACHE_HIT_BANK1_XECORE16_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE17",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE17",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext902__icache_hit_bank1_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext902_ICACHE_HIT_BANK1_XECORE17_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE18",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE18",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext902__icache_hit_bank1_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext902_ICACHE_HIT_BANK1_XECORE18_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE19",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE19",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext902__icache_hit_bank1_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext902_ICACHE_HIT_BANK1_XECORE19_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE20",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE20",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext902__icache_hit_bank1_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext902_ICACHE_HIT_BANK1_XECORE20_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE21",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE21",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext902__icache_hit_bank1_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext902_ICACHE_HIT_BANK1_XECORE21_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE22",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE22",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext902__icache_hit_bank1_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext902_ICACHE_HIT_BANK1_XECORE22_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE23",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE23",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext902__icache_hit_bank1_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext902_ICACHE_HIT_BANK1_XECORE23_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE16",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE16",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext902__icache_miss_bank1_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext902_ICACHE_MISS_BANK1_XECORE16_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE17",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE17",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext902__icache_miss_bank1_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext902_ICACHE_MISS_BANK1_XECORE17_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE18",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE18",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext902__icache_miss_bank1_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext902_ICACHE_MISS_BANK1_XECORE18_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE19",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE19",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext902__icache_miss_bank1_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext902_ICACHE_MISS_BANK1_XECORE19_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE20",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE20",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext902__icache_miss_bank1_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext902_ICACHE_MISS_BANK1_XECORE20_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE21",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE21",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext902__icache_miss_bank1_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext902_ICACHE_MISS_BANK1_XECORE21_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE22",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE22",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext902__icache_miss_bank1_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext902_ICACHE_MISS_BANK1_XECORE22_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE23",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE23",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext902__icache_miss_bank1_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext902_ICACHE_MISS_BANK1_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext903_ICACHE_HIT_BANK1_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext903_ICACHE_HIT_BANK1_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext903_ICACHE_HIT_BANK1_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext903_ICACHE_HIT_BANK1_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext903_ICACHE_HIT_BANK1_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext903_ICACHE_HIT_BANK1_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext903_ICACHE_HIT_BANK1_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext903_ICACHE_HIT_BANK1_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext903_ICACHE_MISS_BANK1_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext903_ICACHE_MISS_BANK1_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext903_ICACHE_MISS_BANK1_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext903_ICACHE_MISS_BANK1_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext903_ICACHE_MISS_BANK1_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext903_ICACHE_MISS_BANK1_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext903_ICACHE_MISS_BANK1_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext903_ICACHE_MISS_BANK1_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext903_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext903";
    metric_set->symbol_name = "Ext903";
    metric_set->hw_config_guid = "a213b5c5-965f-4daf-8a43-a254fec22419";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext903_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext903__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext903__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext903__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext903__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK1 XECORE24",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE24",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext903__icache_hit_bank1_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext903_ICACHE_HIT_BANK1_XECORE24_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE25",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE25",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext903__icache_hit_bank1_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext903_ICACHE_HIT_BANK1_XECORE25_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE26",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE26",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext903__icache_hit_bank1_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext903_ICACHE_HIT_BANK1_XECORE26_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE27",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE27",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext903__icache_hit_bank1_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext903_ICACHE_HIT_BANK1_XECORE27_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE28",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE28",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext903__icache_hit_bank1_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext903_ICACHE_HIT_BANK1_XECORE28_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE29",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE29",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext903__icache_hit_bank1_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext903_ICACHE_HIT_BANK1_XECORE29_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE30",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE30",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext903__icache_hit_bank1_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext903_ICACHE_HIT_BANK1_XECORE30_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE31",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE31",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext903__icache_hit_bank1_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext903_ICACHE_HIT_BANK1_XECORE31_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE24",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE24",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext903__icache_miss_bank1_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext903_ICACHE_MISS_BANK1_XECORE24_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE25",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE25",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext903__icache_miss_bank1_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext903_ICACHE_MISS_BANK1_XECORE25_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE26",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE26",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext903__icache_miss_bank1_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext903_ICACHE_MISS_BANK1_XECORE26_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE27",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE27",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext903__icache_miss_bank1_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext903_ICACHE_MISS_BANK1_XECORE27_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE28",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE28",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext903__icache_miss_bank1_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext903_ICACHE_MISS_BANK1_XECORE28_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE29",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE29",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext903__icache_miss_bank1_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext903_ICACHE_MISS_BANK1_XECORE29_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE30",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE30",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext903__icache_miss_bank1_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext903_ICACHE_MISS_BANK1_XECORE30_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE31",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE31",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext903__icache_miss_bank1_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext903_ICACHE_MISS_BANK1_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext904_ICACHE_HIT_BANK2_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext904_ICACHE_HIT_BANK2_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext904_ICACHE_HIT_BANK2_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext904_ICACHE_HIT_BANK2_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext904_ICACHE_HIT_BANK2_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext904_ICACHE_HIT_BANK2_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext904_ICACHE_HIT_BANK2_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext904_ICACHE_HIT_BANK2_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext904_ICACHE_MISS_BANK2_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext904_ICACHE_MISS_BANK2_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext904_ICACHE_MISS_BANK2_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext904_ICACHE_MISS_BANK2_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext904_ICACHE_MISS_BANK2_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext904_ICACHE_MISS_BANK2_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext904_ICACHE_MISS_BANK2_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext904_ICACHE_MISS_BANK2_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext904_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext904";
    metric_set->symbol_name = "Ext904";
    metric_set->hw_config_guid = "3a901be2-0b46-4e5e-8852-dc0187f7a829";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext904_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext904__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext904__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext904__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext904__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK2 XECORE0",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE0",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext904__icache_hit_bank2_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext904_ICACHE_HIT_BANK2_XECORE0_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE1",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE1",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext904__icache_hit_bank2_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext904_ICACHE_HIT_BANK2_XECORE1_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE2",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE2",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext904__icache_hit_bank2_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext904_ICACHE_HIT_BANK2_XECORE2_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE3",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE3",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext904__icache_hit_bank2_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext904_ICACHE_HIT_BANK2_XECORE3_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE4",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE4",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext904__icache_hit_bank2_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext904_ICACHE_HIT_BANK2_XECORE4_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE5",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE5",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext904__icache_hit_bank2_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext904_ICACHE_HIT_BANK2_XECORE5_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE6",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE6",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext904__icache_hit_bank2_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext904_ICACHE_HIT_BANK2_XECORE6_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE7",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE7",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext904__icache_hit_bank2_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext904_ICACHE_HIT_BANK2_XECORE7_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE0",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE0",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext904__icache_miss_bank2_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext904_ICACHE_MISS_BANK2_XECORE0_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE1",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE1",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext904__icache_miss_bank2_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext904_ICACHE_MISS_BANK2_XECORE1_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE2",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE2",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext904__icache_miss_bank2_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext904_ICACHE_MISS_BANK2_XECORE2_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE3",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE3",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext904__icache_miss_bank2_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext904_ICACHE_MISS_BANK2_XECORE3_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE4",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE4",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext904__icache_miss_bank2_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext904_ICACHE_MISS_BANK2_XECORE4_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE5",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE5",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext904__icache_miss_bank2_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext904_ICACHE_MISS_BANK2_XECORE5_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE6",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE6",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext904__icache_miss_bank2_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext904_ICACHE_MISS_BANK2_XECORE6_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE7",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE7",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext904__icache_miss_bank2_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext904_ICACHE_MISS_BANK2_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext905_ICACHE_HIT_BANK2_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext905_ICACHE_HIT_BANK2_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext905_ICACHE_HIT_BANK2_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext905_ICACHE_HIT_BANK2_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext905_ICACHE_HIT_BANK2_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext905_ICACHE_HIT_BANK2_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext905_ICACHE_HIT_BANK2_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext905_ICACHE_HIT_BANK2_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext905_ICACHE_MISS_BANK2_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext905_ICACHE_MISS_BANK2_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext905_ICACHE_MISS_BANK2_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext905_ICACHE_MISS_BANK2_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext905_ICACHE_MISS_BANK2_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext905_ICACHE_MISS_BANK2_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext905_ICACHE_MISS_BANK2_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext905_ICACHE_MISS_BANK2_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext905_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext905";
    metric_set->symbol_name = "Ext905";
    metric_set->hw_config_guid = "9c547e29-18b8-408c-8c43-bcc3c756eed3";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext905_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext905__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext905__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext905__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext905__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK2 XECORE10",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE10",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext905__icache_hit_bank2_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext905_ICACHE_HIT_BANK2_XECORE10_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE11",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE11",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext905__icache_hit_bank2_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext905_ICACHE_HIT_BANK2_XECORE11_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE12",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE12",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext905__icache_hit_bank2_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext905_ICACHE_HIT_BANK2_XECORE12_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE13",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE13",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext905__icache_hit_bank2_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext905_ICACHE_HIT_BANK2_XECORE13_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE14",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE14",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext905__icache_hit_bank2_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext905_ICACHE_HIT_BANK2_XECORE14_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE15",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE15",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext905__icache_hit_bank2_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext905_ICACHE_HIT_BANK2_XECORE15_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE8",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE8",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext905__icache_hit_bank2_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext905_ICACHE_HIT_BANK2_XECORE8_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE9",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE9",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext905__icache_hit_bank2_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext905_ICACHE_HIT_BANK2_XECORE9_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE10",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE10",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext905__icache_miss_bank2_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext905_ICACHE_MISS_BANK2_XECORE10_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE11",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE11",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext905__icache_miss_bank2_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext905_ICACHE_MISS_BANK2_XECORE11_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE12",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE12",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext905__icache_miss_bank2_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext905_ICACHE_MISS_BANK2_XECORE12_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE13",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE13",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext905__icache_miss_bank2_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext905_ICACHE_MISS_BANK2_XECORE13_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE14",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE14",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext905__icache_miss_bank2_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext905_ICACHE_MISS_BANK2_XECORE14_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE15",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE15",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext905__icache_miss_bank2_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext905_ICACHE_MISS_BANK2_XECORE15_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE8",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE8",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext905__icache_miss_bank2_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext905_ICACHE_MISS_BANK2_XECORE8_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE9",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE9",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext905__icache_miss_bank2_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext905_ICACHE_MISS_BANK2_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext906_ICACHE_HIT_BANK2_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext906_ICACHE_HIT_BANK2_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext906_ICACHE_HIT_BANK2_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext906_ICACHE_HIT_BANK2_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext906_ICACHE_HIT_BANK2_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext906_ICACHE_HIT_BANK2_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext906_ICACHE_HIT_BANK2_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext906_ICACHE_HIT_BANK2_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext906_ICACHE_MISS_BANK2_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext906_ICACHE_MISS_BANK2_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext906_ICACHE_MISS_BANK2_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext906_ICACHE_MISS_BANK2_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext906_ICACHE_MISS_BANK2_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext906_ICACHE_MISS_BANK2_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext906_ICACHE_MISS_BANK2_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext906_ICACHE_MISS_BANK2_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext906_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext906";
    metric_set->symbol_name = "Ext906";
    metric_set->hw_config_guid = "64ce4293-1f46-434d-a9e4-709b2fa8b0db";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext906_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext906__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext906__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext906__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext906__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK2 XECORE16",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE16",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext906__icache_hit_bank2_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext906_ICACHE_HIT_BANK2_XECORE16_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE17",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE17",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext906__icache_hit_bank2_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext906_ICACHE_HIT_BANK2_XECORE17_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE18",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE18",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext906__icache_hit_bank2_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext906_ICACHE_HIT_BANK2_XECORE18_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE19",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE19",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext906__icache_hit_bank2_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext906_ICACHE_HIT_BANK2_XECORE19_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE20",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE20",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext906__icache_hit_bank2_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext906_ICACHE_HIT_BANK2_XECORE20_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE21",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE21",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext906__icache_hit_bank2_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext906_ICACHE_HIT_BANK2_XECORE21_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE22",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE22",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext906__icache_hit_bank2_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext906_ICACHE_HIT_BANK2_XECORE22_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE23",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE23",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext906__icache_hit_bank2_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext906_ICACHE_HIT_BANK2_XECORE23_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE16",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE16",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext906__icache_miss_bank2_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext906_ICACHE_MISS_BANK2_XECORE16_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE17",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE17",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext906__icache_miss_bank2_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext906_ICACHE_MISS_BANK2_XECORE17_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE18",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE18",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext906__icache_miss_bank2_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext906_ICACHE_MISS_BANK2_XECORE18_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE19",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE19",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext906__icache_miss_bank2_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext906_ICACHE_MISS_BANK2_XECORE19_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE20",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE20",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext906__icache_miss_bank2_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext906_ICACHE_MISS_BANK2_XECORE20_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE21",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE21",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext906__icache_miss_bank2_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext906_ICACHE_MISS_BANK2_XECORE21_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE22",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE22",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext906__icache_miss_bank2_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext906_ICACHE_MISS_BANK2_XECORE22_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE23",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE23",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext906__icache_miss_bank2_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext906_ICACHE_MISS_BANK2_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext907_ICACHE_HIT_BANK2_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext907_ICACHE_HIT_BANK2_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext907_ICACHE_HIT_BANK2_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext907_ICACHE_HIT_BANK2_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext907_ICACHE_HIT_BANK2_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext907_ICACHE_HIT_BANK2_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext907_ICACHE_HIT_BANK2_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext907_ICACHE_HIT_BANK2_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext907_ICACHE_MISS_BANK2_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext907_ICACHE_MISS_BANK2_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext907_ICACHE_MISS_BANK2_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext907_ICACHE_MISS_BANK2_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext907_ICACHE_MISS_BANK2_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext907_ICACHE_MISS_BANK2_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext907_ICACHE_MISS_BANK2_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext907_ICACHE_MISS_BANK2_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext907_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext907";
    metric_set->symbol_name = "Ext907";
    metric_set->hw_config_guid = "73dc617b-8971-4a76-96e9-2cf205acc81e";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext907_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext907__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext907__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext907__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext907__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK2 XECORE24",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE24",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext907__icache_hit_bank2_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext907_ICACHE_HIT_BANK2_XECORE24_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE25",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE25",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext907__icache_hit_bank2_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext907_ICACHE_HIT_BANK2_XECORE25_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE26",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE26",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext907__icache_hit_bank2_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext907_ICACHE_HIT_BANK2_XECORE26_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE27",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE27",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext907__icache_hit_bank2_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext907_ICACHE_HIT_BANK2_XECORE27_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE28",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE28",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext907__icache_hit_bank2_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext907_ICACHE_HIT_BANK2_XECORE28_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE29",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE29",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext907__icache_hit_bank2_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext907_ICACHE_HIT_BANK2_XECORE29_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE30",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE30",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext907__icache_hit_bank2_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext907_ICACHE_HIT_BANK2_XECORE30_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE31",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE31",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext907__icache_hit_bank2_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext907_ICACHE_HIT_BANK2_XECORE31_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE24",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE24",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext907__icache_miss_bank2_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext907_ICACHE_MISS_BANK2_XECORE24_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE25",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE25",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext907__icache_miss_bank2_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext907_ICACHE_MISS_BANK2_XECORE25_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE26",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE26",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext907__icache_miss_bank2_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext907_ICACHE_MISS_BANK2_XECORE26_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE27",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE27",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext907__icache_miss_bank2_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext907_ICACHE_MISS_BANK2_XECORE27_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE28",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE28",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext907__icache_miss_bank2_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext907_ICACHE_MISS_BANK2_XECORE28_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE29",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE29",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext907__icache_miss_bank2_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext907_ICACHE_MISS_BANK2_XECORE29_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE30",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE30",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext907__icache_miss_bank2_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext907_ICACHE_MISS_BANK2_XECORE30_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE31",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE31",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext907__icache_miss_bank2_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext907_ICACHE_MISS_BANK2_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext908_ICACHE_HIT_BANK3_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext908_ICACHE_HIT_BANK3_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext908_ICACHE_HIT_BANK3_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext908_ICACHE_HIT_BANK3_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext908_ICACHE_HIT_BANK3_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext908_ICACHE_HIT_BANK3_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext908_ICACHE_HIT_BANK3_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext908_ICACHE_HIT_BANK3_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext908_ICACHE_MISS_BANK3_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext908_ICACHE_MISS_BANK3_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext908_ICACHE_MISS_BANK3_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext908_ICACHE_MISS_BANK3_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext908_ICACHE_MISS_BANK3_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext908_ICACHE_MISS_BANK3_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext908_ICACHE_MISS_BANK3_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext908_ICACHE_MISS_BANK3_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext908_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext908";
    metric_set->symbol_name = "Ext908";
    metric_set->hw_config_guid = "9eef500b-7077-4fc2-9101-dd900833104f";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext908_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext908__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext908__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext908__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext908__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK3 XECORE0",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE0",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext908__icache_hit_bank3_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext908_ICACHE_HIT_BANK3_XECORE0_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE1",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE1",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext908__icache_hit_bank3_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext908_ICACHE_HIT_BANK3_XECORE1_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE2",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE2",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext908__icache_hit_bank3_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext908_ICACHE_HIT_BANK3_XECORE2_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE3",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE3",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext908__icache_hit_bank3_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext908_ICACHE_HIT_BANK3_XECORE3_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE4",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE4",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext908__icache_hit_bank3_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext908_ICACHE_HIT_BANK3_XECORE4_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE5",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE5",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext908__icache_hit_bank3_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext908_ICACHE_HIT_BANK3_XECORE5_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE6",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE6",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext908__icache_hit_bank3_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext908_ICACHE_HIT_BANK3_XECORE6_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE7",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE7",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext908__icache_hit_bank3_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext908_ICACHE_HIT_BANK3_XECORE7_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE0",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE0",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext908__icache_miss_bank3_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext908_ICACHE_MISS_BANK3_XECORE0_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE1",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE1",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext908__icache_miss_bank3_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext908_ICACHE_MISS_BANK3_XECORE1_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE2",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE2",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext908__icache_miss_bank3_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext908_ICACHE_MISS_BANK3_XECORE2_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE3",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE3",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext908__icache_miss_bank3_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext908_ICACHE_MISS_BANK3_XECORE3_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE4",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE4",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext908__icache_miss_bank3_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext908_ICACHE_MISS_BANK3_XECORE4_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE5",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE5",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext908__icache_miss_bank3_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext908_ICACHE_MISS_BANK3_XECORE5_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE6",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE6",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext908__icache_miss_bank3_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext908_ICACHE_MISS_BANK3_XECORE6_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE7",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE7",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext908__icache_miss_bank3_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext908_ICACHE_MISS_BANK3_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext909_ICACHE_HIT_BANK3_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext909_ICACHE_HIT_BANK3_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext909_ICACHE_HIT_BANK3_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext909_ICACHE_HIT_BANK3_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext909_ICACHE_HIT_BANK3_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext909_ICACHE_HIT_BANK3_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext909_ICACHE_HIT_BANK3_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext909_ICACHE_HIT_BANK3_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext909_ICACHE_MISS_BANK3_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext909_ICACHE_MISS_BANK3_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext909_ICACHE_MISS_BANK3_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext909_ICACHE_MISS_BANK3_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext909_ICACHE_MISS_BANK3_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext909_ICACHE_MISS_BANK3_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext909_ICACHE_MISS_BANK3_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext909_ICACHE_MISS_BANK3_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext909_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext909";
    metric_set->symbol_name = "Ext909";
    metric_set->hw_config_guid = "d1160adc-3cd3-4dd0-825b-7bc15e319191";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext909_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext909__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext909__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext909__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext909__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK3 XECORE10",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE10",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext909__icache_hit_bank3_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext909_ICACHE_HIT_BANK3_XECORE10_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE11",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE11",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext909__icache_hit_bank3_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext909_ICACHE_HIT_BANK3_XECORE11_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE12",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE12",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext909__icache_hit_bank3_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext909_ICACHE_HIT_BANK3_XECORE12_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE13",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE13",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext909__icache_hit_bank3_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext909_ICACHE_HIT_BANK3_XECORE13_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE14",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE14",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext909__icache_hit_bank3_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext909_ICACHE_HIT_BANK3_XECORE14_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE15",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE15",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext909__icache_hit_bank3_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext909_ICACHE_HIT_BANK3_XECORE15_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE8",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE8",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext909__icache_hit_bank3_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext909_ICACHE_HIT_BANK3_XECORE8_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE9",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE9",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext909__icache_hit_bank3_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext909_ICACHE_HIT_BANK3_XECORE9_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE10",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE10",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext909__icache_miss_bank3_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext909_ICACHE_MISS_BANK3_XECORE10_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE11",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE11",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext909__icache_miss_bank3_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext909_ICACHE_MISS_BANK3_XECORE11_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE12",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE12",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext909__icache_miss_bank3_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext909_ICACHE_MISS_BANK3_XECORE12_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE13",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE13",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext909__icache_miss_bank3_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext909_ICACHE_MISS_BANK3_XECORE13_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE14",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE14",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext909__icache_miss_bank3_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext909_ICACHE_MISS_BANK3_XECORE14_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE15",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE15",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext909__icache_miss_bank3_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext909_ICACHE_MISS_BANK3_XECORE15_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE8",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE8",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext909__icache_miss_bank3_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext909_ICACHE_MISS_BANK3_XECORE8_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE9",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE9",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext909__icache_miss_bank3_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext909_ICACHE_MISS_BANK3_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext910_ICACHE_HIT_BANK3_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext910_ICACHE_HIT_BANK3_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext910_ICACHE_HIT_BANK3_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext910_ICACHE_HIT_BANK3_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext910_ICACHE_HIT_BANK3_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext910_ICACHE_HIT_BANK3_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext910_ICACHE_HIT_BANK3_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext910_ICACHE_HIT_BANK3_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext910_ICACHE_MISS_BANK3_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext910_ICACHE_MISS_BANK3_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext910_ICACHE_MISS_BANK3_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext910_ICACHE_MISS_BANK3_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext910_ICACHE_MISS_BANK3_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext910_ICACHE_MISS_BANK3_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext910_ICACHE_MISS_BANK3_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext910_ICACHE_MISS_BANK3_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext910_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext910";
    metric_set->symbol_name = "Ext910";
    metric_set->hw_config_guid = "6ba0f6ff-cc07-4ba5-81c6-87e4279c9867";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext910_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext910__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext910__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext910__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext910__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK3 XECORE16",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE16",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext910__icache_hit_bank3_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext910_ICACHE_HIT_BANK3_XECORE16_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE17",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE17",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext910__icache_hit_bank3_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext910_ICACHE_HIT_BANK3_XECORE17_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE18",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE18",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext910__icache_hit_bank3_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext910_ICACHE_HIT_BANK3_XECORE18_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE19",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE19",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext910__icache_hit_bank3_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext910_ICACHE_HIT_BANK3_XECORE19_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE20",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE20",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext910__icache_hit_bank3_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext910_ICACHE_HIT_BANK3_XECORE20_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE21",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE21",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext910__icache_hit_bank3_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext910_ICACHE_HIT_BANK3_XECORE21_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE22",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE22",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext910__icache_hit_bank3_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext910_ICACHE_HIT_BANK3_XECORE22_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE23",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE23",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext910__icache_hit_bank3_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext910_ICACHE_HIT_BANK3_XECORE23_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE16",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE16",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext910__icache_miss_bank3_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext910_ICACHE_MISS_BANK3_XECORE16_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE17",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE17",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext910__icache_miss_bank3_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext910_ICACHE_MISS_BANK3_XECORE17_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE18",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE18",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext910__icache_miss_bank3_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext910_ICACHE_MISS_BANK3_XECORE18_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE19",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE19",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext910__icache_miss_bank3_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext910_ICACHE_MISS_BANK3_XECORE19_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE20",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE20",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext910__icache_miss_bank3_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext910_ICACHE_MISS_BANK3_XECORE20_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE21",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE21",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext910__icache_miss_bank3_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext910_ICACHE_MISS_BANK3_XECORE21_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE22",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE22",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext910__icache_miss_bank3_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext910_ICACHE_MISS_BANK3_XECORE22_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE23",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE23",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext910__icache_miss_bank3_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext910_ICACHE_MISS_BANK3_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext911_ICACHE_HIT_BANK3_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext911_ICACHE_HIT_BANK3_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext911_ICACHE_HIT_BANK3_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext911_ICACHE_HIT_BANK3_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext911_ICACHE_HIT_BANK3_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext911_ICACHE_HIT_BANK3_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext911_ICACHE_HIT_BANK3_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext911_ICACHE_HIT_BANK3_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext911_ICACHE_MISS_BANK3_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext911_ICACHE_MISS_BANK3_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext911_ICACHE_MISS_BANK3_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext911_ICACHE_MISS_BANK3_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext911_ICACHE_MISS_BANK3_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext911_ICACHE_MISS_BANK3_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext911_ICACHE_MISS_BANK3_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext911_ICACHE_MISS_BANK3_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext911_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext911";
    metric_set->symbol_name = "Ext911";
    metric_set->hw_config_guid = "09a68225-f72f-4750-b6f1-b7f2a7b7bf7e";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext911_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext911__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext911__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext911__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext911__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK3 XECORE24",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE24",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext911__icache_hit_bank3_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext911_ICACHE_HIT_BANK3_XECORE24_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE25",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE25",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext911__icache_hit_bank3_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext911_ICACHE_HIT_BANK3_XECORE25_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE26",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE26",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext911__icache_hit_bank3_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext911_ICACHE_HIT_BANK3_XECORE26_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE27",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE27",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext911__icache_hit_bank3_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext911_ICACHE_HIT_BANK3_XECORE27_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE28",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE28",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext911__icache_hit_bank3_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext911_ICACHE_HIT_BANK3_XECORE28_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE29",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE29",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext911__icache_hit_bank3_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext911_ICACHE_HIT_BANK3_XECORE29_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE30",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE30",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext911__icache_hit_bank3_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext911_ICACHE_HIT_BANK3_XECORE30_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE31",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE31",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext911__icache_hit_bank3_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext911_ICACHE_HIT_BANK3_XECORE31_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE24",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE24",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext911__icache_miss_bank3_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext911_ICACHE_MISS_BANK3_XECORE24_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE25",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE25",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext911__icache_miss_bank3_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext911_ICACHE_MISS_BANK3_XECORE25_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE26",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE26",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext911__icache_miss_bank3_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext911_ICACHE_MISS_BANK3_XECORE26_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE27",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE27",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext911__icache_miss_bank3_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext911_ICACHE_MISS_BANK3_XECORE27_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE28",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE28",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext911__icache_miss_bank3_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext911_ICACHE_MISS_BANK3_XECORE28_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE29",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE29",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext911__icache_miss_bank3_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext911_ICACHE_MISS_BANK3_XECORE29_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE30",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE30",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext911__icache_miss_bank3_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext911_ICACHE_MISS_BANK3_XECORE30_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE31",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE31",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext911__icache_miss_bank3_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt3_ext911_ICACHE_MISS_BANK3_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt3_ext912_SLM_BANK_CONFLICT_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext912_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext912";
    metric_set->symbol_name = "Ext912";
    metric_set->hw_config_guid = "76e4db74-d6d2-4774-80cd-702f27e15675";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext912_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext912__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext912__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext912__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext912__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE0",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE0",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext912__slm_bank_conflict_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext912_SLM_BANK_CONFLICT_COUNT_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext913_SLM_BANK_CONFLICT_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext913_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext913";
    metric_set->symbol_name = "Ext913";
    metric_set->hw_config_guid = "3506a146-a056-484d-bc76-191ba6ed5036";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext913_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext913__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext913__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext913__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext913__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE1",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE1",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext913__slm_bank_conflict_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext913_SLM_BANK_CONFLICT_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext914_SLM_BANK_CONFLICT_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext914_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext914";
    metric_set->symbol_name = "Ext914";
    metric_set->hw_config_guid = "3846aa70-3952-4ad3-af8a-6463b74c38c5";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext914_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext914__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext914__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext914__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext914__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE2",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE2",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext914__slm_bank_conflict_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext914_SLM_BANK_CONFLICT_COUNT_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext915_SLM_BANK_CONFLICT_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext915_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext915";
    metric_set->symbol_name = "Ext915";
    metric_set->hw_config_guid = "e2a3f9b4-7fc0-4229-8f7f-2f8bf4f381e5";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext915_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext915__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext915__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext915__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext915__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE3",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE3",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext915__slm_bank_conflict_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext915_SLM_BANK_CONFLICT_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext916_SLM_BANK_CONFLICT_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext916_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext916";
    metric_set->symbol_name = "Ext916";
    metric_set->hw_config_guid = "ae92f979-3dfd-4172-9fd3-6551c9c938cb";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext916_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext916__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext916__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext916__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext916__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE4",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE4",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext916__slm_bank_conflict_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext916_SLM_BANK_CONFLICT_COUNT_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext917_SLM_BANK_CONFLICT_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext917_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext917";
    metric_set->symbol_name = "Ext917";
    metric_set->hw_config_guid = "2f2acb42-910b-4312-b86d-2f3e13ea5e1c";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext917_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext917__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext917__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext917__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext917__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE5",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE5",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext917__slm_bank_conflict_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext917_SLM_BANK_CONFLICT_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext918_SLM_BANK_CONFLICT_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext918_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext918";
    metric_set->symbol_name = "Ext918";
    metric_set->hw_config_guid = "40216875-613d-4693-ba6d-1c6a37157b32";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext918_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext918__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext918__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext918__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext918__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE6",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE6",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext918__slm_bank_conflict_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext918_SLM_BANK_CONFLICT_COUNT_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext919_SLM_BANK_CONFLICT_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext919_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext919";
    metric_set->symbol_name = "Ext919";
    metric_set->hw_config_guid = "db527284-999a-4f23-b319-4ccac15c54c6";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext919_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext919__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext919__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext919__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext919__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE7",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE7",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext919__slm_bank_conflict_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext919_SLM_BANK_CONFLICT_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext920_SLM_BANK_CONFLICT_COUNT_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext920_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext920";
    metric_set->symbol_name = "Ext920";
    metric_set->hw_config_guid = "17b8db25-a815-4616-9251-caa558af0db1";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext920_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext920__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext920__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext920__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext920__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE8",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE8",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext920__slm_bank_conflict_count_xecore8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext920_SLM_BANK_CONFLICT_COUNT_XECORE8_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext921_SLM_BANK_CONFLICT_COUNT_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext921_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext921";
    metric_set->symbol_name = "Ext921";
    metric_set->hw_config_guid = "7c5214fa-e627-46dd-bf73-96b97e3b46cd";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext921_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext921__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext921__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext921__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext921__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE9",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE9",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext921__slm_bank_conflict_count_xecore9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext921_SLM_BANK_CONFLICT_COUNT_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext922_SLM_BANK_CONFLICT_COUNT_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext922_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext922";
    metric_set->symbol_name = "Ext922";
    metric_set->hw_config_guid = "044b808a-b7f2-4e2c-bcf9-34c161b9def4";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext922_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext922__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext922__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext922__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext922__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE10",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE10",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext922__slm_bank_conflict_count_xecore10__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext922_SLM_BANK_CONFLICT_COUNT_XECORE10_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext923_SLM_BANK_CONFLICT_COUNT_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext923_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext923";
    metric_set->symbol_name = "Ext923";
    metric_set->hw_config_guid = "7a09a646-9e0f-495d-b768-fd55dd0ccc75";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext923_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext923__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext923__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext923__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext923__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE11",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE11",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext923__slm_bank_conflict_count_xecore11__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext923_SLM_BANK_CONFLICT_COUNT_XECORE11_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext924_SLM_BANK_CONFLICT_COUNT_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext924_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext924";
    metric_set->symbol_name = "Ext924";
    metric_set->hw_config_guid = "5339dcea-309f-4df0-8858-c9e668536425";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext924_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext924__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext924__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext924__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext924__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE12",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE12",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext924__slm_bank_conflict_count_xecore12__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext924_SLM_BANK_CONFLICT_COUNT_XECORE12_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext925_SLM_BANK_CONFLICT_COUNT_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext925_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext925";
    metric_set->symbol_name = "Ext925";
    metric_set->hw_config_guid = "9b59db08-b7d6-4544-a8e5-486158a6377d";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext925_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext925__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext925__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext925__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext925__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE13",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE13",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext925__slm_bank_conflict_count_xecore13__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext925_SLM_BANK_CONFLICT_COUNT_XECORE13_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext926_SLM_BANK_CONFLICT_COUNT_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext926_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext926";
    metric_set->symbol_name = "Ext926";
    metric_set->hw_config_guid = "5f31c335-12b6-4e4f-abc3-cdc650168def";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext926_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext926__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext926__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext926__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext926__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE14",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE14",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext926__slm_bank_conflict_count_xecore14__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext926_SLM_BANK_CONFLICT_COUNT_XECORE14_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext927_SLM_BANK_CONFLICT_COUNT_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext927_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext927";
    metric_set->symbol_name = "Ext927";
    metric_set->hw_config_guid = "c413bffe-ef29-40b0-899a-d23dfb0718a2";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext927_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext927__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext927__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext927__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext927__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE15",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE15",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext927__slm_bank_conflict_count_xecore15__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext927_SLM_BANK_CONFLICT_COUNT_XECORE15_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext928_SLM_BANK_CONFLICT_COUNT_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext928_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext928";
    metric_set->symbol_name = "Ext928";
    metric_set->hw_config_guid = "42ae6e37-0810-46c4-8d78-b76e28e7a7f8";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext928_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext928__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext928__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext928__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext928__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE16",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE16",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext928__slm_bank_conflict_count_xecore16__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext928_SLM_BANK_CONFLICT_COUNT_XECORE16_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext929_SLM_BANK_CONFLICT_COUNT_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext929_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext929";
    metric_set->symbol_name = "Ext929";
    metric_set->hw_config_guid = "cf938b48-3aa4-4b8a-ba01-ec993f0f4c92";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext929_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext929__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext929__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext929__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext929__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE17",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE17",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext929__slm_bank_conflict_count_xecore17__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext929_SLM_BANK_CONFLICT_COUNT_XECORE17_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext930_SLM_BANK_CONFLICT_COUNT_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext930_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext930";
    metric_set->symbol_name = "Ext930";
    metric_set->hw_config_guid = "39e1edcd-5c27-4f20-b460-5b506bab2c5b";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext930_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext930__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext930__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext930__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext930__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE18",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE18",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext930__slm_bank_conflict_count_xecore18__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext930_SLM_BANK_CONFLICT_COUNT_XECORE18_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext931_SLM_BANK_CONFLICT_COUNT_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext931_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext931";
    metric_set->symbol_name = "Ext931";
    metric_set->hw_config_guid = "1e3ee19b-dfbc-483a-b1b6-8df99fa18f9a";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext931_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext931__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext931__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext931__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext931__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE19",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE19",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext931__slm_bank_conflict_count_xecore19__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext931_SLM_BANK_CONFLICT_COUNT_XECORE19_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext932_SLM_BANK_CONFLICT_COUNT_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext932_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext932";
    metric_set->symbol_name = "Ext932";
    metric_set->hw_config_guid = "8c63d2ab-71c0-4b22-b9d7-1b74ed86b77f";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext932_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext932__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext932__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext932__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext932__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE20",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE20",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext932__slm_bank_conflict_count_xecore20__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext932_SLM_BANK_CONFLICT_COUNT_XECORE20_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext933_SLM_BANK_CONFLICT_COUNT_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext933_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext933";
    metric_set->symbol_name = "Ext933";
    metric_set->hw_config_guid = "32abbaf3-3fa0-4bf2-b455-21bc065a470a";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext933_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext933__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext933__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext933__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext933__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE21",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE21",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext933__slm_bank_conflict_count_xecore21__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext933_SLM_BANK_CONFLICT_COUNT_XECORE21_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext934_SLM_BANK_CONFLICT_COUNT_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext934_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext934";
    metric_set->symbol_name = "Ext934";
    metric_set->hw_config_guid = "36ec10c5-30d6-4ed5-80fc-7fca5bfc8db2";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext934_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext934__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext934__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext934__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext934__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE22",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE22",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext934__slm_bank_conflict_count_xecore22__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext934_SLM_BANK_CONFLICT_COUNT_XECORE22_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext935_SLM_BANK_CONFLICT_COUNT_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext935_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext935";
    metric_set->symbol_name = "Ext935";
    metric_set->hw_config_guid = "93f4ca26-8eb8-45af-acc7-ade95a86bf4e";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext935_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext935__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext935__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext935__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext935__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE23",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE23",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext935__slm_bank_conflict_count_xecore23__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext935_SLM_BANK_CONFLICT_COUNT_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext936_SLM_BANK_CONFLICT_COUNT_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext936_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext936";
    metric_set->symbol_name = "Ext936";
    metric_set->hw_config_guid = "6411422a-9ae7-4d23-83b4-27a0f571daea";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext936_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext936__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext936__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext936__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext936__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE24",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE24",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext936__slm_bank_conflict_count_xecore24__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext936_SLM_BANK_CONFLICT_COUNT_XECORE24_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext937_SLM_BANK_CONFLICT_COUNT_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext937_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext937";
    metric_set->symbol_name = "Ext937";
    metric_set->hw_config_guid = "2a21eaf2-0ff9-4d72-a54b-d47b31a09202";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext937_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext937__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext937__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext937__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext937__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE25",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE25",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext937__slm_bank_conflict_count_xecore25__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext937_SLM_BANK_CONFLICT_COUNT_XECORE25_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext938_SLM_BANK_CONFLICT_COUNT_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext938_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext938";
    metric_set->symbol_name = "Ext938";
    metric_set->hw_config_guid = "13073d0f-fa11-4814-9bcd-139958585128";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext938_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext938__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext938__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext938__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext938__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE26",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE26",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext938__slm_bank_conflict_count_xecore26__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext938_SLM_BANK_CONFLICT_COUNT_XECORE26_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext939_SLM_BANK_CONFLICT_COUNT_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext939_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext939";
    metric_set->symbol_name = "Ext939";
    metric_set->hw_config_guid = "43a8b6e0-50ff-486e-812b-42a4d00ec5f7";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext939_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext939__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext939__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext939__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext939__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE27",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE27",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext939__slm_bank_conflict_count_xecore27__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext939_SLM_BANK_CONFLICT_COUNT_XECORE27_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext940_SLM_BANK_CONFLICT_COUNT_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext940_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext940";
    metric_set->symbol_name = "Ext940";
    metric_set->hw_config_guid = "61e98434-0a16-40c8-9b7d-371652eb33cd";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext940_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext940__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext940__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext940__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext940__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE28",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE28",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext940__slm_bank_conflict_count_xecore28__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext940_SLM_BANK_CONFLICT_COUNT_XECORE28_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext941_SLM_BANK_CONFLICT_COUNT_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext941_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext941";
    metric_set->symbol_name = "Ext941";
    metric_set->hw_config_guid = "1c13d9d5-c6f4-47a1-b695-8273b93037fe";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext941_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext941__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext941__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext941__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext941__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE29",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE29",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext941__slm_bank_conflict_count_xecore29__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext941_SLM_BANK_CONFLICT_COUNT_XECORE29_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext942_SLM_BANK_CONFLICT_COUNT_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext942_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext942";
    metric_set->symbol_name = "Ext942";
    metric_set->hw_config_guid = "9efa16a4-a3ae-4be2-a616-7b6164ed850b";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext942_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext942__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext942__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext942__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext942__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE30",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE30",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext942__slm_bank_conflict_count_xecore30__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext942_SLM_BANK_CONFLICT_COUNT_XECORE30_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext943_SLM_BANK_CONFLICT_COUNT_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext943_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext943";
    metric_set->symbol_name = "Ext943";
    metric_set->hw_config_guid = "e0e775d6-908a-4410-8ed1-a26b1d316700";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext943_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext943__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext943__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext943__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext943__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE31",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE31",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext943__slm_bank_conflict_count_xecore31__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext943_SLM_BANK_CONFLICT_COUNT_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt3_ext944_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext944_SLM_BYTE_READ_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext944_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext944";
    metric_set->symbol_name = "Ext944";
    metric_set->hw_config_guid = "5e825890-c584-4545-bf82-6a8ded48393c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext944_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext944__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext944__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext944__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext944__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK0 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE0",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext944__load_store_cache_byte_read_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext944_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE0_availability,
            },

            {
                .name = "SLM BYTE READ BANK0 XECORE0",
                .symbol_name = "SLM_BYTE_READ_BANK0_XECORE0",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext944__slm_byte_read_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext944_SLM_BYTE_READ_BANK0_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext945_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext945_SLM_BYTE_READ_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext945_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext945";
    metric_set->symbol_name = "Ext945";
    metric_set->hw_config_guid = "07f8b9c7-a909-4ea1-ab0e-d1a1b72fba23";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext945_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext945__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext945__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext945__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext945__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK0 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE1",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext945__load_store_cache_byte_read_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext945_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE1_availability,
            },

            {
                .name = "SLM BYTE READ BANK0 XECORE1",
                .symbol_name = "SLM_BYTE_READ_BANK0_XECORE1",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext945__slm_byte_read_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext945_SLM_BYTE_READ_BANK0_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext946_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext946_SLM_BYTE_READ_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext946_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext946";
    metric_set->symbol_name = "Ext946";
    metric_set->hw_config_guid = "01c4a3bf-e61c-459a-8eed-c736edf29117";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext946_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext946__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext946__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext946__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext946__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK0 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE2",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext946__load_store_cache_byte_read_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext946_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE2_availability,
            },

            {
                .name = "SLM BYTE READ BANK0 XECORE2",
                .symbol_name = "SLM_BYTE_READ_BANK0_XECORE2",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext946__slm_byte_read_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext946_SLM_BYTE_READ_BANK0_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext947_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext947_SLM_BYTE_READ_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext947_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext947";
    metric_set->symbol_name = "Ext947";
    metric_set->hw_config_guid = "37906cb5-0da3-49d3-875e-d11e3584e4dd";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext947_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext947__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext947__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext947__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext947__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK0 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE3",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext947__load_store_cache_byte_read_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext947_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE3_availability,
            },

            {
                .name = "SLM BYTE READ BANK0 XECORE3",
                .symbol_name = "SLM_BYTE_READ_BANK0_XECORE3",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext947__slm_byte_read_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext947_SLM_BYTE_READ_BANK0_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext948_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext948_SLM_BYTE_READ_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext948_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext948";
    metric_set->symbol_name = "Ext948";
    metric_set->hw_config_guid = "12e4baf7-6d8d-46c0-acd7-5f94223dddc8";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext948_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext948__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext948__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext948__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext948__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK1 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE0",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext948__load_store_cache_byte_read_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext948_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE0_availability,
            },

            {
                .name = "SLM BYTE READ BANK1 XECORE0",
                .symbol_name = "SLM_BYTE_READ_BANK1_XECORE0",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext948__slm_byte_read_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext948_SLM_BYTE_READ_BANK1_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext949_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext949_SLM_BYTE_READ_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext949_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext949";
    metric_set->symbol_name = "Ext949";
    metric_set->hw_config_guid = "b616fbb5-c0d3-4e63-bcff-61bcf8ba8ff9";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext949_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext949__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext949__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext949__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext949__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK1 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE1",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext949__load_store_cache_byte_read_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext949_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE1_availability,
            },

            {
                .name = "SLM BYTE READ BANK1 XECORE1",
                .symbol_name = "SLM_BYTE_READ_BANK1_XECORE1",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext949__slm_byte_read_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext949_SLM_BYTE_READ_BANK1_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext950_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext950_SLM_BYTE_READ_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext950_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext950";
    metric_set->symbol_name = "Ext950";
    metric_set->hw_config_guid = "5e7edb7d-ba9b-4574-9bac-abd4742e186e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext950_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext950__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext950__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext950__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext950__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK1 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE2",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext950__load_store_cache_byte_read_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext950_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE2_availability,
            },

            {
                .name = "SLM BYTE READ BANK1 XECORE2",
                .symbol_name = "SLM_BYTE_READ_BANK1_XECORE2",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext950__slm_byte_read_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext950_SLM_BYTE_READ_BANK1_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext951_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext951_SLM_BYTE_READ_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext951_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext951";
    metric_set->symbol_name = "Ext951";
    metric_set->hw_config_guid = "24ad6a9c-cb37-4e16-b25b-3cc444e081a5";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext951_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext951__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext951__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext951__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext951__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK1 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE3",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext951__load_store_cache_byte_read_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext951_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE3_availability,
            },

            {
                .name = "SLM BYTE READ BANK1 XECORE3",
                .symbol_name = "SLM_BYTE_READ_BANK1_XECORE3",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext951__slm_byte_read_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext951_SLM_BYTE_READ_BANK1_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext952_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext952_SLM_BYTE_READ_BANK2_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext952_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext952";
    metric_set->symbol_name = "Ext952";
    metric_set->hw_config_guid = "526b1c1e-b636-4231-9d4c-6e6987c4b24b";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext952_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext952__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext952__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext952__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext952__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK2 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE0",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext952__load_store_cache_byte_read_bank2_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext952_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE0_availability,
            },

            {
                .name = "SLM BYTE READ BANK2 XECORE0",
                .symbol_name = "SLM_BYTE_READ_BANK2_XECORE0",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext952__slm_byte_read_bank2_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext952_SLM_BYTE_READ_BANK2_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext953_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext953_SLM_BYTE_READ_BANK2_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext953_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext953";
    metric_set->symbol_name = "Ext953";
    metric_set->hw_config_guid = "da7fb135-174a-41fb-a6fd-0bdc44732d9e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext953_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext953__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext953__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext953__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext953__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK2 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE1",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext953__load_store_cache_byte_read_bank2_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext953_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE1_availability,
            },

            {
                .name = "SLM BYTE READ BANK2 XECORE1",
                .symbol_name = "SLM_BYTE_READ_BANK2_XECORE1",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext953__slm_byte_read_bank2_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext953_SLM_BYTE_READ_BANK2_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext954_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext954_SLM_BYTE_READ_BANK2_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext954_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext954";
    metric_set->symbol_name = "Ext954";
    metric_set->hw_config_guid = "7499a841-6a6a-45ce-9c27-9bf6080ea900";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext954_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext954__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext954__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext954__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext954__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK2 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE2",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext954__load_store_cache_byte_read_bank2_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext954_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE2_availability,
            },

            {
                .name = "SLM BYTE READ BANK2 XECORE2",
                .symbol_name = "SLM_BYTE_READ_BANK2_XECORE2",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext954__slm_byte_read_bank2_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext954_SLM_BYTE_READ_BANK2_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext955_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext955_SLM_BYTE_READ_BANK2_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext955_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext955";
    metric_set->symbol_name = "Ext955";
    metric_set->hw_config_guid = "4b6cce94-cbf0-4b56-9b24-6c2ebd167755";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext955_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext955__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext955__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext955__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext955__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK2 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE3",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext955__load_store_cache_byte_read_bank2_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext955_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE3_availability,
            },

            {
                .name = "SLM BYTE READ BANK2 XECORE3",
                .symbol_name = "SLM_BYTE_READ_BANK2_XECORE3",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext955__slm_byte_read_bank2_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext955_SLM_BYTE_READ_BANK2_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext956_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext956_SLM_BYTE_READ_BANK3_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext956_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext956";
    metric_set->symbol_name = "Ext956";
    metric_set->hw_config_guid = "c648eaa7-cac1-4c84-a2ea-c3448f108ab2";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext956_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext956__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext956__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext956__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext956__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK3 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE0",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext956__load_store_cache_byte_read_bank3_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext956_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE0_availability,
            },

            {
                .name = "SLM BYTE READ BANK3 XECORE0",
                .symbol_name = "SLM_BYTE_READ_BANK3_XECORE0",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext956__slm_byte_read_bank3_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext956_SLM_BYTE_READ_BANK3_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext957_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext957_SLM_BYTE_READ_BANK3_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext957_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext957";
    metric_set->symbol_name = "Ext957";
    metric_set->hw_config_guid = "37b143ab-aba8-4537-a735-14cccb02f079";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext957_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext957__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext957__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext957__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext957__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK3 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE1",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext957__load_store_cache_byte_read_bank3_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext957_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE1_availability,
            },

            {
                .name = "SLM BYTE READ BANK3 XECORE1",
                .symbol_name = "SLM_BYTE_READ_BANK3_XECORE1",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext957__slm_byte_read_bank3_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext957_SLM_BYTE_READ_BANK3_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext958_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext958_SLM_BYTE_READ_BANK3_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext958_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext958";
    metric_set->symbol_name = "Ext958";
    metric_set->hw_config_guid = "98d49ba7-236c-410e-958a-3f08c09b74c7";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext958_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext958__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext958__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext958__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext958__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK3 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE2",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext958__load_store_cache_byte_read_bank3_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext958_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE2_availability,
            },

            {
                .name = "SLM BYTE READ BANK3 XECORE2",
                .symbol_name = "SLM_BYTE_READ_BANK3_XECORE2",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext958__slm_byte_read_bank3_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext958_SLM_BYTE_READ_BANK3_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext959_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext959_SLM_BYTE_READ_BANK3_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext959_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext959";
    metric_set->symbol_name = "Ext959";
    metric_set->hw_config_guid = "5d40ca14-33f7-4fc8-a9cd-7cd5d3aa58b3";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext959_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext959__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext959__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext959__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext959__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK3 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE3",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext959__load_store_cache_byte_read_bank3_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext959_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE3_availability,
            },

            {
                .name = "SLM BYTE READ BANK3 XECORE3",
                .symbol_name = "SLM_BYTE_READ_BANK3_XECORE3",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext959__slm_byte_read_bank3_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext959_SLM_BYTE_READ_BANK3_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext960_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext960_SLM_BYTE_WRITE_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext960_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext960";
    metric_set->symbol_name = "Ext960";
    metric_set->hw_config_guid = "04f3962b-a11a-4aa4-a263-d545823df4af";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext960_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext960__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext960__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext960__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext960__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK0 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE0",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext960__load_store_cache_byte_write_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext960_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE0_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK0 XECORE0",
                .symbol_name = "SLM_BYTE_WRITE_BANK0_XECORE0",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext960__slm_byte_write_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext960_SLM_BYTE_WRITE_BANK0_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext961_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext961_SLM_BYTE_WRITE_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext961_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext961";
    metric_set->symbol_name = "Ext961";
    metric_set->hw_config_guid = "b07a3402-0c0e-4ea8-af95-738c3445e5df";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext961_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext961__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext961__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext961__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext961__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK0 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE1",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext961__load_store_cache_byte_write_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext961_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE1_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK0 XECORE1",
                .symbol_name = "SLM_BYTE_WRITE_BANK0_XECORE1",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext961__slm_byte_write_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext961_SLM_BYTE_WRITE_BANK0_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext962_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext962_SLM_BYTE_WRITE_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext962_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext962";
    metric_set->symbol_name = "Ext962";
    metric_set->hw_config_guid = "fcab665c-5dda-47b6-9052-99f992805980";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext962_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext962__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext962__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext962__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext962__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK0 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE2",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext962__load_store_cache_byte_write_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext962_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE2_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK0 XECORE2",
                .symbol_name = "SLM_BYTE_WRITE_BANK0_XECORE2",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext962__slm_byte_write_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext962_SLM_BYTE_WRITE_BANK0_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext963_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext963_SLM_BYTE_WRITE_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext963_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext963";
    metric_set->symbol_name = "Ext963";
    metric_set->hw_config_guid = "88e912b5-3333-46e1-86e2-b7c5ebfff84a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext963_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext963__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext963__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext963__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext963__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK0 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE3",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext963__load_store_cache_byte_write_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext963_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE3_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK0 XECORE3",
                .symbol_name = "SLM_BYTE_WRITE_BANK0_XECORE3",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext963__slm_byte_write_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext963_SLM_BYTE_WRITE_BANK0_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext964_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext964_SLM_BYTE_WRITE_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext964_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext964";
    metric_set->symbol_name = "Ext964";
    metric_set->hw_config_guid = "00a17d53-6cda-47b5-95fe-36770dab66c6";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext964_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext964__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext964__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext964__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext964__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK1 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE0",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext964__load_store_cache_byte_write_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext964_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE0_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK1 XECORE0",
                .symbol_name = "SLM_BYTE_WRITE_BANK1_XECORE0",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext964__slm_byte_write_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext964_SLM_BYTE_WRITE_BANK1_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext965_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext965_SLM_BYTE_WRITE_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext965_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext965";
    metric_set->symbol_name = "Ext965";
    metric_set->hw_config_guid = "3259b467-758c-42e9-a86f-a35e44003569";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext965_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext965__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext965__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext965__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext965__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK1 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE1",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext965__load_store_cache_byte_write_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext965_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE1_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK1 XECORE1",
                .symbol_name = "SLM_BYTE_WRITE_BANK1_XECORE1",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext965__slm_byte_write_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext965_SLM_BYTE_WRITE_BANK1_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext966_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext966_SLM_BYTE_WRITE_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext966_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext966";
    metric_set->symbol_name = "Ext966";
    metric_set->hw_config_guid = "a96fef9c-bc3d-4986-b2b9-d2233b157ac7";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext966_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext966__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext966__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext966__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext966__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK1 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE2",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext966__load_store_cache_byte_write_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext966_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE2_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK1 XECORE2",
                .symbol_name = "SLM_BYTE_WRITE_BANK1_XECORE2",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext966__slm_byte_write_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext966_SLM_BYTE_WRITE_BANK1_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext967_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext967_SLM_BYTE_WRITE_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext967_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext967";
    metric_set->symbol_name = "Ext967";
    metric_set->hw_config_guid = "cffa549c-1997-4b02-adfc-81fbff2971c2";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext967_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext967__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext967__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext967__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext967__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK1 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE3",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext967__load_store_cache_byte_write_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext967_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE3_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK1 XECORE3",
                .symbol_name = "SLM_BYTE_WRITE_BANK1_XECORE3",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext967__slm_byte_write_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext967_SLM_BYTE_WRITE_BANK1_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext968_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext968_SLM_BYTE_WRITE_BANK2_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext968_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext968";
    metric_set->symbol_name = "Ext968";
    metric_set->hw_config_guid = "97bb78db-526f-45e9-b302-e71bdb354a51";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext968_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext968__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext968__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext968__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext968__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK2 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE0",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext968__load_store_cache_byte_write_bank2_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext968_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE0_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK2 XECORE0",
                .symbol_name = "SLM_BYTE_WRITE_BANK2_XECORE0",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext968__slm_byte_write_bank2_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext968_SLM_BYTE_WRITE_BANK2_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext969_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext969_SLM_BYTE_WRITE_BANK2_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext969_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext969";
    metric_set->symbol_name = "Ext969";
    metric_set->hw_config_guid = "0f12e897-1e98-49e9-bd01-463aec885b06";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext969_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext969__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext969__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext969__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext969__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK2 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE1",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext969__load_store_cache_byte_write_bank2_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext969_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE1_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK2 XECORE1",
                .symbol_name = "SLM_BYTE_WRITE_BANK2_XECORE1",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext969__slm_byte_write_bank2_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext969_SLM_BYTE_WRITE_BANK2_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext970_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext970_SLM_BYTE_WRITE_BANK2_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext970_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext970";
    metric_set->symbol_name = "Ext970";
    metric_set->hw_config_guid = "742767ec-da64-414c-9f32-f59d97dd9c30";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext970_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext970__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext970__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext970__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext970__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK2 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE2",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext970__load_store_cache_byte_write_bank2_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext970_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE2_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK2 XECORE2",
                .symbol_name = "SLM_BYTE_WRITE_BANK2_XECORE2",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext970__slm_byte_write_bank2_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext970_SLM_BYTE_WRITE_BANK2_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext971_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext971_SLM_BYTE_WRITE_BANK2_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext971_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext971";
    metric_set->symbol_name = "Ext971";
    metric_set->hw_config_guid = "b8132d7c-7b59-4906-bea4-7401dd0eea38";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext971_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext971__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext971__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext971__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext971__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK2 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE3",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext971__load_store_cache_byte_write_bank2_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext971_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE3_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK2 XECORE3",
                .symbol_name = "SLM_BYTE_WRITE_BANK2_XECORE3",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext971__slm_byte_write_bank2_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext971_SLM_BYTE_WRITE_BANK2_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext972_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext972_SLM_BYTE_WRITE_BANK3_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext972_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext972";
    metric_set->symbol_name = "Ext972";
    metric_set->hw_config_guid = "cbcadae5-b72e-462b-9b5a-b06880be86c6";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext972_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext972__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext972__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext972__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext972__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK3 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE0",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext972__load_store_cache_byte_write_bank3_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext972_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE0_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK3 XECORE0",
                .symbol_name = "SLM_BYTE_WRITE_BANK3_XECORE0",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext972__slm_byte_write_bank3_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext972_SLM_BYTE_WRITE_BANK3_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext973_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext973_SLM_BYTE_WRITE_BANK3_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext973_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext973";
    metric_set->symbol_name = "Ext973";
    metric_set->hw_config_guid = "03be681d-684c-4f4d-8a09-18e0a605c864";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext973_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext973__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext973__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext973__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext973__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK3 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE1",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext973__load_store_cache_byte_write_bank3_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext973_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE1_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK3 XECORE1",
                .symbol_name = "SLM_BYTE_WRITE_BANK3_XECORE1",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext973__slm_byte_write_bank3_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext973_SLM_BYTE_WRITE_BANK3_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext974_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext974_SLM_BYTE_WRITE_BANK3_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext974_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext974";
    metric_set->symbol_name = "Ext974";
    metric_set->hw_config_guid = "acca3492-bdac-49b9-aa54-9d7033f6d46d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext974_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext974__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext974__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext974__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext974__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK3 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE2",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext974__load_store_cache_byte_write_bank3_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext974_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE2_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK3 XECORE2",
                .symbol_name = "SLM_BYTE_WRITE_BANK3_XECORE2",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext974__slm_byte_write_bank3_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext974_SLM_BYTE_WRITE_BANK3_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext975_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext975_SLM_BYTE_WRITE_BANK3_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext975_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext975";
    metric_set->symbol_name = "Ext975";
    metric_set->hw_config_guid = "2c53a11a-5077-487c-bf6d-894ac78600c7";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext975_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext975__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext975__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext975__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext975__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK3 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE3",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext975__load_store_cache_byte_write_bank3_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext975_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE3_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK3 XECORE3",
                .symbol_name = "SLM_BYTE_WRITE_BANK3_XECORE3",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt3__ext975__slm_byte_write_bank3_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt3_ext975_SLM_BYTE_WRITE_BANK3_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt3_ext976_RT_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext976_RT_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext976_RT_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext976_RT_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext976_RT_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext976_RT_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext976_RT_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext976_RT_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext976_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext976";
    metric_set->symbol_name = "Ext976";
    metric_set->hw_config_guid = "ce390b14-0e8c-4f97-afd8-d3296ca986c4";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext976_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext976__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext976__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext976__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext976__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT AVAILABLE XECORE0",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext976__rt_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext976_RT_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE1",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext976__rt_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext976_RT_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE2",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext976__rt_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext976_RT_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE3",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext976__rt_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext976_RT_INPUT_AVAILABLE_XECORE3_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE4",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext976__rt_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext976_RT_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE5",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext976__rt_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext976_RT_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE6",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext976__rt_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext976_RT_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE7",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext976__rt_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext976_RT_INPUT_AVAILABLE_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext977_RT_INPUT_AVAILABLE_XECORE10_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext977_RT_INPUT_AVAILABLE_XECORE11_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext977_RT_INPUT_AVAILABLE_XECORE12_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext977_RT_INPUT_AVAILABLE_XECORE13_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext977_RT_INPUT_AVAILABLE_XECORE14_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext977_RT_INPUT_AVAILABLE_XECORE15_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext977_RT_INPUT_AVAILABLE_XECORE8_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext977_RT_INPUT_AVAILABLE_XECORE9_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext977_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext977";
    metric_set->symbol_name = "Ext977";
    metric_set->hw_config_guid = "f638017d-bd81-4359-9f9b-daafcd5b9492";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext977_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext977__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext977__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext977__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext977__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT AVAILABLE XECORE10",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE10",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext977__rt_input_available_xecore10__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext977_RT_INPUT_AVAILABLE_XECORE10_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE11",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE11",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext977__rt_input_available_xecore11__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext977_RT_INPUT_AVAILABLE_XECORE11_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE12",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE12",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext977__rt_input_available_xecore12__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext977_RT_INPUT_AVAILABLE_XECORE12_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE13",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE13",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext977__rt_input_available_xecore13__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext977_RT_INPUT_AVAILABLE_XECORE13_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE14",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE14",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext977__rt_input_available_xecore14__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext977_RT_INPUT_AVAILABLE_XECORE14_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE15",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE15",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext977__rt_input_available_xecore15__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext977_RT_INPUT_AVAILABLE_XECORE15_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE8",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE8",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext977__rt_input_available_xecore8__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext977_RT_INPUT_AVAILABLE_XECORE8_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE9",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE9",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext977__rt_input_available_xecore9__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext977_RT_INPUT_AVAILABLE_XECORE9_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext978_RT_INPUT_AVAILABLE_XECORE16_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext978_RT_INPUT_AVAILABLE_XECORE17_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext978_RT_INPUT_AVAILABLE_XECORE18_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext978_RT_INPUT_AVAILABLE_XECORE19_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 4, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext978_RT_INPUT_AVAILABLE_XECORE20_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext978_RT_INPUT_AVAILABLE_XECORE21_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext978_RT_INPUT_AVAILABLE_XECORE22_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext978_RT_INPUT_AVAILABLE_XECORE23_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 5, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext978_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext978";
    metric_set->symbol_name = "Ext978";
    metric_set->hw_config_guid = "28b23f45-71a2-44d2-9661-423be5a6831d";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext978_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext978__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext978__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext978__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext978__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT AVAILABLE XECORE16",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE16",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext978__rt_input_available_xecore16__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext978_RT_INPUT_AVAILABLE_XECORE16_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE17",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE17",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext978__rt_input_available_xecore17__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext978_RT_INPUT_AVAILABLE_XECORE17_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE18",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE18",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext978__rt_input_available_xecore18__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext978_RT_INPUT_AVAILABLE_XECORE18_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE19",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE19",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext978__rt_input_available_xecore19__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext978_RT_INPUT_AVAILABLE_XECORE19_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE20",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE20",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext978__rt_input_available_xecore20__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext978_RT_INPUT_AVAILABLE_XECORE20_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE21",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE21",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext978__rt_input_available_xecore21__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext978_RT_INPUT_AVAILABLE_XECORE21_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE22",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE22",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext978__rt_input_available_xecore22__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext978_RT_INPUT_AVAILABLE_XECORE22_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE23",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE23",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext978__rt_input_available_xecore23__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext978_RT_INPUT_AVAILABLE_XECORE23_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt3_ext979_RT_INPUT_AVAILABLE_XECORE24_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext979_RT_INPUT_AVAILABLE_XECORE25_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext979_RT_INPUT_AVAILABLE_XECORE26_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext979_RT_INPUT_AVAILABLE_XECORE27_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 6, 3)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext979_RT_INPUT_AVAILABLE_XECORE28_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 0)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext979_RT_INPUT_AVAILABLE_XECORE29_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 1)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext979_RT_INPUT_AVAILABLE_XECORE30_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 2)) {
        return true;
    }
    return false;
}
static bool acmgt3_ext979_RT_INPUT_AVAILABLE_XECORE31_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 7, 3)) {
        return true;
    }
    return false;
}

static void
acmgt3_add_ext979_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext979";
    metric_set->symbol_name = "Ext979";
    metric_set->hw_config_guid = "88f7e719-828f-466e-8c74-61c31b885975";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext979_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext979__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext979__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext979__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext979__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT AVAILABLE XECORE24",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE24",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext979__rt_input_available_xecore24__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext979_RT_INPUT_AVAILABLE_XECORE24_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE25",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE25",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext979__rt_input_available_xecore25__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext979_RT_INPUT_AVAILABLE_XECORE25_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE26",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE26",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext979__rt_input_available_xecore26__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext979_RT_INPUT_AVAILABLE_XECORE26_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE27",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE27",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext979__rt_input_available_xecore27__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext979_RT_INPUT_AVAILABLE_XECORE27_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE28",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE28",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext979__rt_input_available_xecore28__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext979_RT_INPUT_AVAILABLE_XECORE28_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE29",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE29",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext979__rt_input_available_xecore29__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext979_RT_INPUT_AVAILABLE_XECORE29_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE30",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE30",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext979__rt_input_available_xecore30__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext979_RT_INPUT_AVAILABLE_XECORE30_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE31",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE31",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext979__rt_input_available_xecore31__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt3_ext979_RT_INPUT_AVAILABLE_XECORE31_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}


static void
acmgt3_add_ext980_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext980";
    metric_set->symbol_name = "Ext980";
    metric_set->hw_config_guid = "8ac802cf-f221-461c-aedd-7a45bcb63165";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext980_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext980__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext980__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 READ SQIDI0",
                .symbol_name = "GPU_MEMORY_L3_READ_SQIDI0",
                .desc = "Number of GTI memory reads from L3 caused by L3 Cache misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext980__gpu_memory_l3_read_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext980__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext980__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt3_add_ext981_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext981";
    metric_set->symbol_name = "Ext981";
    metric_set->hw_config_guid = "1bcb5260-ee4d-4c39-ba59-033b7bd84271";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext981_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext981__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext981__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 READ SQIDI1",
                .symbol_name = "GPU_MEMORY_L3_READ_SQIDI1",
                .desc = "Number of GTI memory reads from L3 caused by L3 Cache misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext981__gpu_memory_l3_read_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext981__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext981__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt3_add_ext982_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext982";
    metric_set->symbol_name = "Ext982";
    metric_set->hw_config_guid = "7480a976-6f5e-46e3-babb-01cc4b34cd75";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext982_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext982__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext982__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 READ SQIDI2",
                .symbol_name = "GPU_MEMORY_L3_READ_SQIDI2",
                .desc = "Number of GTI memory reads from L3 caused by L3 Cache misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext982__gpu_memory_l3_read_sqidi2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext982__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext982__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt3_add_ext983_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext983";
    metric_set->symbol_name = "Ext983";
    metric_set->hw_config_guid = "599cd4bb-5fd9-4586-b813-fcb44b53b648";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext983_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext983__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext983__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 READ SQIDI3",
                .symbol_name = "GPU_MEMORY_L3_READ_SQIDI3",
                .desc = "Number of GTI memory reads from L3 caused by L3 Cache misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext983__gpu_memory_l3_read_sqidi3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext983__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext983__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt3_add_ext984_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext984";
    metric_set->symbol_name = "Ext984";
    metric_set->hw_config_guid = "3661cc06-7370-4d4d-9838-6ba6847fb2af";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext984_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext984__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext984__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 READ SQIDI4",
                .symbol_name = "GPU_MEMORY_L3_READ_SQIDI4",
                .desc = "Number of GTI memory reads from L3 caused by L3 Cache misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext984__gpu_memory_l3_read_sqidi4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext984__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext984__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt3_add_ext985_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext985";
    metric_set->symbol_name = "Ext985";
    metric_set->hw_config_guid = "3a7100ab-0b38-4148-9fc3-15b735b80668";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext985_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext985__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext985__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 READ SQIDI5",
                .symbol_name = "GPU_MEMORY_L3_READ_SQIDI5",
                .desc = "Number of GTI memory reads from L3 caused by L3 Cache misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext985__gpu_memory_l3_read_sqidi5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext985__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext985__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt3_add_ext986_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext986";
    metric_set->symbol_name = "Ext986";
    metric_set->hw_config_guid = "ea7e1fea-e645-42b6-875a-170eadcf6716";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext986_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext986__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext986__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 READ SQIDI6",
                .symbol_name = "GPU_MEMORY_L3_READ_SQIDI6",
                .desc = "Number of GTI memory reads from L3 caused by L3 Cache misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext986__gpu_memory_l3_read_sqidi6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext986__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext986__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt3_add_ext987_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext987";
    metric_set->symbol_name = "Ext987";
    metric_set->hw_config_guid = "0cc6ded2-c760-49d1-80c2-0ecd33484aca";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext987_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext987__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext987__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 READ SQIDI7",
                .symbol_name = "GPU_MEMORY_L3_READ_SQIDI7",
                .desc = "Number of GTI memory reads from L3 caused by L3 Cache misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext987__gpu_memory_l3_read_sqidi7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext987__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext987__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt3_add_ext1000_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1000";
    metric_set->symbol_name = "Ext1000";
    metric_set->hw_config_guid = "6ed6774b-beba-4a52-baae-04188cd01cc0";
    metric_set->counters = calloc(23, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext1000_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext1000__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext1000__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext1000__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext1000__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE ACTIVE",
                .symbol_name = "XVE_ACTIVE",
                .desc = "Percentage of time in which at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1000__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE ACTIVE CYCLES",
                .symbol_name = "XVE_ACTIVE_CYCLES",
                .desc = "Number of cycles at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1000__xve_active_cycles__read,
                .max_uint64 = acmgt3__ext1000__xve_active_cycles__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ALL",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ALL",
                .desc = "Number of execution slots taken by instructions executed on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1000__xve_inst_executed_alu0_all__read,
                .max_uint64 = acmgt3__ext1000__xve_inst_executed_alu0_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1000__xve_inst_executed_alu0_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ALL",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ALL",
                .desc = "Number of execution slots taken by instructions executed on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1000__xve_inst_executed_alu1_all__read,
                .max_uint64 = acmgt3__ext1000__xve_inst_executed_alu1_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1000__xve_inst_executed_alu1_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED CONTROL ALL",
                .symbol_name = "XVE_INST_EXECUTED_CONTROL_ALL",
                .desc = "Number of instructions executed on Jump Pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1000__xve_inst_executed_control_all__read,
                .max_uint64 = acmgt3__ext1000__xve_inst_executed_control_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED CONTROL ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_CONTROL_ALL_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed on Jump Pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1000__xve_inst_executed_control_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND ALL",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ALL",
                .desc = "Number of instructions executed on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1000__xve_inst_executed_send_all__read,
                .max_uint64 = acmgt3__ext1000__xve_inst_executed_send_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ALL_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1000__xve_inst_executed_send_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX ALL",
                .symbol_name = "XVE_INST_EXECUTED_XMX_ALL",
                .desc = "Number of execution slots taken by instructions executed in XMX pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1000__xve_inst_executed_xmx_all__read,
                .max_uint64 = acmgt3__ext1000__xve_inst_executed_xmx_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_XMX_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed in XMX pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1000__xve_inst_executed_xmx_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE PIPE ALU0 AND ALU1 ACTIVE",
                .symbol_name = "XVE_PIPE_ALU0_AND_ALU1_ACTIVE",
                .desc = "Percentage of time in which ALU0 and ALU1 pipes are both actively executing a Gen ISA instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1000__xve_pipe_alu0_and_alu1_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE PIPE ALU0 AND ALU1 ACTIVE CYCLES",
                .symbol_name = "XVE_PIPE_ALU0_AND_ALU1_ACTIVE_CYCLES",
                .desc = "Number of cycles in ALU0 and ALU1 pipes are both actively executing a Gen ISA instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read,
                .max_uint64 = acmgt3__ext1000__xve_pipe_alu0_and_alu1_active_cycles__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE PIPE ALU0 AND XMX ACTIVE",
                .symbol_name = "XVE_PIPE_ALU0_AND_XMX_ACTIVE",
                .desc = "Percentage of time in which ALU0 and XMX pipes are both actively executing a Gen ISA instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1000__xve_pipe_alu0_and_xmx_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE PIPE ALU0 AND XMX ACTIVE CYCLES",
                .symbol_name = "XVE_PIPE_ALU0_AND_XMX_ACTIVE_CYCLES",
                .desc = "Number of cycles ALU0 and XMX pipes are both actively executing a Gen ISA instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1000__xve_pipe_alu0_and_xmx_active_cycles__read,
                .max_uint64 = acmgt3__ext1000__xve_pipe_alu0_and_xmx_active_cycles__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1000__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES",
                .symbol_name = "XVE_STALL_CYCLES",
                .desc = "Number of cycles any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1000__xve_stall_cycles__read,
                .max_uint64 = acmgt3__ext1000__xve_stall_cycles__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE THREADS OCCUPANCY ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_ALL",
                .desc = "Percentage of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1000__xve_threads_occupancy_all__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE THREADS OCCUPANCY CYCLES ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_CYCLES_ALL",
                .desc = "Number of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1000__xve_threads_occupancy_cycles_all__read,
                .max_uint64 = acmgt3__ext1000__xve_threads_occupancy_cycles_all__max,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 23);
}


static void
acmgt3_add_ext1001_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1001";
    metric_set->symbol_name = "Ext1001";
    metric_set->hw_config_guid = "28009d66-9dae-4325-8339-06b19af58abd";
    metric_set->counters = calloc(27, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext1001_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext1001__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext1001__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext1001__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext1001__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ASYNC CS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ASYNC_CS",
                .desc = "Number of execution slots taken by instructions executed by Async Compute Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1001__xve_inst_executed_alu0_async_cs__read,
                .max_uint64 = acmgt3__ext1001__xve_inst_executed_alu0_async_cs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ASYNC CS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ASYNC_CS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Async Compute Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1001__xve_inst_executed_alu0_async_cs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 CS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_CS",
                .desc = "Number of execution slots taken by instructions executed by Compute Shader (from Render Engine) on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1001__xve_inst_executed_alu0_cs__read,
                .max_uint64 = acmgt3__ext1001__xve_inst_executed_alu0_cs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 CS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_CS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Compute Shader (from Render Engine) on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1001__xve_inst_executed_alu0_cs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 DS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_DS",
                .desc = "Number of execution slots taken by instructions executed by Domain Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1001__xve_inst_executed_alu0_ds__read,
                .max_uint64 = acmgt3__ext1001__xve_inst_executed_alu0_ds__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 DS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_DS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Domain Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1001__xve_inst_executed_alu0_ds_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 HS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_HS",
                .desc = "Number of execution slots taken by instructions executed by Hull Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1001__xve_inst_executed_alu0_hs__read,
                .max_uint64 = acmgt3__ext1001__xve_inst_executed_alu0_hs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 HS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_HS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Hull Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1001__xve_inst_executed_alu0_hs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 FS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_PS",
                .desc = "Number of execution slots taken by instructions executed by Fragment Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1001__xve_inst_executed_alu0_ps__read,
                .max_uint64 = acmgt3__ext1001__xve_inst_executed_alu0_ps__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 FS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_PS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Fragment Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1001__xve_inst_executed_alu0_ps_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 VS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_VS",
                .desc = "Number of execution slots taken by instructions executed by Vertex Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1001__xve_inst_executed_alu0_vs__read,
                .max_uint64 = acmgt3__ext1001__xve_inst_executed_alu0_vs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 VS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_VS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Vertex Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1001__xve_inst_executed_alu0_vs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ASYNC CS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ASYNC_CS",
                .desc = "Number of execution slots taken by instructions executed by Async Compute Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1001__xve_inst_executed_alu1_async_cs__read,
                .max_uint64 = acmgt3__ext1001__xve_inst_executed_alu1_async_cs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ASYNC CS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ASYNC_CS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Async Compute Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1001__xve_inst_executed_alu1_async_cs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 CS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_CS",
                .desc = "Number of execution slots taken by instructions executed by Compute Shader (from Render Engine) on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1001__xve_inst_executed_alu1_cs__read,
                .max_uint64 = acmgt3__ext1001__xve_inst_executed_alu1_cs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 CS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_CS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Compute Shader (from Render Engine) on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1001__xve_inst_executed_alu1_cs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 DS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_DS",
                .desc = "Number of execution slots taken by instructions executed by Domain Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1001__xve_inst_executed_alu1_ds__read,
                .max_uint64 = acmgt3__ext1001__xve_inst_executed_alu1_ds__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 DS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_DS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Domain Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1001__xve_inst_executed_alu1_ds_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 HS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_HS",
                .desc = "Number of execution slots taken by instructions executed by Hull Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1001__xve_inst_executed_alu1_hs__read,
                .max_uint64 = acmgt3__ext1001__xve_inst_executed_alu1_hs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 HS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_HS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Hull Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1001__xve_inst_executed_alu1_hs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 FS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_PS",
                .desc = "Number of execution slots taken by instructions executed by Fragment Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1001__xve_inst_executed_alu1_ps__read,
                .max_uint64 = acmgt3__ext1001__xve_inst_executed_alu1_ps__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 FS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_PS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Fragment Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1001__xve_inst_executed_alu1_ps_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 VS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_VS",
                .desc = "Number of execution slots taken by instructions executed by Vertex Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1001__xve_inst_executed_alu1_vs__read,
                .max_uint64 = acmgt3__ext1001__xve_inst_executed_alu1_vs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 VS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_VS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Vertex Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1001__xve_inst_executed_alu1_vs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 27);
}


static void
acmgt3_add_ext1002_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1002";
    metric_set->symbol_name = "Ext1002";
    metric_set->hw_config_guid = "75ef7f1c-7b1f-4d06-b666-6e09a69fc16d";
    metric_set->counters = calloc(21, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext1002_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext1002__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext1002__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext1002__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext1002__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST EXECUTED ALU0 RT AHS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_RT_AHS",
                .desc = "Number of execution slots taken by instructions executed by BTD Any Hit Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1002__xve_inst_executed_alu0_rt_ahs__read,
                .max_uint64 = acmgt3__ext1002__xve_inst_executed_alu0_rt_ahs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 RT AHS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_RT_AHS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by BTD Any Hit Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1002__xve_inst_executed_alu0_rt_ahs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 RT CHS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_RT_CHS",
                .desc = "Number of execution slots taken by instructions executed by BTD Closest Hit Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1002__xve_inst_executed_alu0_rt_chs__read,
                .max_uint64 = acmgt3__ext1002__xve_inst_executed_alu0_rt_chs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 RT CHS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_RT_CHS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by BTD Closest Hit Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1002__xve_inst_executed_alu0_rt_chs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 RT MS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_RT_MS",
                .desc = "Number of execution slots taken by instructions executed by BTD Miss Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1002__xve_inst_executed_alu0_rt_ms__read,
                .max_uint64 = acmgt3__ext1002__xve_inst_executed_alu0_rt_ms__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 RT MS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_RT_MS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by BTD Miss Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1002__xve_inst_executed_alu0_rt_ms_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 RT AHS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_RT_AHS",
                .desc = "Number of execution slots taken by instructions executed by BTD Any Hit Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1002__xve_inst_executed_alu1_rt_ahs__read,
                .max_uint64 = acmgt3__ext1002__xve_inst_executed_alu1_rt_ahs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 RT AHS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_RT_AHS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by BTD Any Hit Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1002__xve_inst_executed_alu1_rt_ahs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 RT CHS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_RT_CHS",
                .desc = "Number of execution slots taken by instructions executed by BTD Closest Hit Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1002__xve_inst_executed_alu1_rt_chs__read,
                .max_uint64 = acmgt3__ext1002__xve_inst_executed_alu1_rt_chs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 RT CHS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_RT_CHS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by BTD Closest Hit Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1002__xve_inst_executed_alu1_rt_chs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 RT MS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_RT_MS",
                .desc = "Number of execution slots taken by instructions executed by BTD Miss Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1002__xve_inst_executed_alu1_rt_ms__read,
                .max_uint64 = acmgt3__ext1002__xve_inst_executed_alu1_rt_ms__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 RT MS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_RT_MS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by BTD Miss Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1002__xve_inst_executed_alu1_rt_ms_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND RT AHS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_RT_AHS",
                .desc = "Number of instructions executed by BTD Any Hit Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1002__xve_inst_executed_send_rt_ahs__read,
                .max_uint64 = acmgt3__ext1002__xve_inst_executed_send_rt_ahs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND RT AHS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_RT_AHS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by BTD Any Hit Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1002__xve_inst_executed_send_rt_ahs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND RT CHS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_RT_CHS",
                .desc = "Number of instructions executed by BTD Closest Hit Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1002__xve_inst_executed_send_rt_chs__read,
                .max_uint64 = acmgt3__ext1002__xve_inst_executed_send_rt_chs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND RT CHS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_RT_CHS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by BTD Closest Hit Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1002__xve_inst_executed_send_rt_chs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND RT MS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_RT_MS",
                .desc = "Number of instructions executed by BTD Miss Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1002__xve_inst_executed_send_rt_ms__read,
                .max_uint64 = acmgt3__ext1002__xve_inst_executed_send_rt_ms__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND RT MS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_RT_MS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by BTD Miss Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1002__xve_inst_executed_send_rt_ms_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 21);
}


static void
acmgt3_add_ext1004_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1004";
    metric_set->symbol_name = "Ext1004";
    metric_set->hw_config_guid = "4994b075-c659-48ab-b167-84cdb120c759";
    metric_set->counters = calloc(23, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext1004_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext1004__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext1004__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext1004__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext1004__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1004__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL ASYNC CS",
                .symbol_name = "XVE_STALL_ASYNC_CS",
                .desc = "Percentage of time in which there are Async Compute Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1004__xve_stall_async_cs__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CS",
                .symbol_name = "XVE_STALL_CS",
                .desc = "Percentage of time in which there are Compute Shader (from Render Engine) threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1004__xve_stall_cs__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES",
                .symbol_name = "XVE_STALL_CYCLES",
                .desc = "Number of cycles any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1004__xve_stall_cycles__read,
                .max_uint64 = acmgt3__ext1004__xve_stall_cycles__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES ASYNC CS",
                .symbol_name = "XVE_STALL_CYCLES_ASYNC_CS",
                .desc = "Number of cycles there are Async Compute Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1004__xve_stall_cycles_async_cs__read,
                .max_uint64 = acmgt3__ext1004__xve_stall_cycles_async_cs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES CS",
                .symbol_name = "XVE_STALL_CYCLES_CS",
                .desc = "Number of cycles there are Compute Shader (from Render Engine) threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1004__xve_stall_cycles_cs__read,
                .max_uint64 = acmgt3__ext1004__xve_stall_cycles_cs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES DS",
                .symbol_name = "XVE_STALL_CYCLES_DS",
                .desc = "Number of cycles there are Domain Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1004__xve_stall_cycles_ds__read,
                .max_uint64 = acmgt3__ext1004__xve_stall_cycles_ds__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES HS",
                .symbol_name = "XVE_STALL_CYCLES_HS",
                .desc = "Number of cycles there are Hull Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1004__xve_stall_cycles_hs__read,
                .max_uint64 = acmgt3__ext1004__xve_stall_cycles_hs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES MS",
                .symbol_name = "XVE_STALL_CYCLES_MS",
                .desc = "Number of cycles there are Mesh Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1004__xve_stall_cycles_ms__read,
                .max_uint64 = acmgt3__ext1004__xve_stall_cycles_ms__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES FS",
                .symbol_name = "XVE_STALL_CYCLES_PS",
                .desc = "Number of cycles there are Fragment Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1004__xve_stall_cycles_ps__read,
                .max_uint64 = acmgt3__ext1004__xve_stall_cycles_ps__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES RT",
                .symbol_name = "XVE_STALL_CYCLES_RT",
                .desc = "Number of cycles there are Ray Tracing Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1004__xve_stall_cycles_rt__read,
                .max_uint64 = acmgt3__ext1004__xve_stall_cycles_rt__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES TS",
                .symbol_name = "XVE_STALL_CYCLES_TS",
                .desc = "Number of cycles there are Task Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1004__xve_stall_cycles_ts__read,
                .max_uint64 = acmgt3__ext1004__xve_stall_cycles_ts__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES VS",
                .symbol_name = "XVE_STALL_CYCLES_VS",
                .desc = "Number of cycles there are Vertex Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1004__xve_stall_cycles_vs__read,
                .max_uint64 = acmgt3__ext1004__xve_stall_cycles_vs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL DS",
                .symbol_name = "XVE_STALL_DS",
                .desc = "Percentage of time in which there are Domain Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1004__xve_stall_ds__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL HS",
                .symbol_name = "XVE_STALL_HS",
                .desc = "Percentage of time in which there are Hull Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1004__xve_stall_hs__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL MS",
                .symbol_name = "XVE_STALL_MS",
                .desc = "Percentage of time in which there are Mesh Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1004__xve_stall_ms__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL FS",
                .symbol_name = "XVE_STALL_PS",
                .desc = "Percentage of time in which there are Fragment Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1004__xve_stall_ps__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL RT",
                .symbol_name = "XVE_STALL_RT",
                .desc = "Percentage of time in which there are Ray Tracing Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1004__xve_stall_rt__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL TS",
                .symbol_name = "XVE_STALL_TS",
                .desc = "Percentage of time in which there are Task Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1004__xve_stall_ts__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL VS",
                .symbol_name = "XVE_STALL_VS",
                .desc = "Percentage of time in which there are Vertex Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1004__xve_stall_vs__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 23);
}


static void
acmgt3_add_ext1005_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1005";
    metric_set->symbol_name = "Ext1005";
    metric_set->hw_config_guid = "b82ec6e0-2be7-4b30-a3db-21bd725849df";
    metric_set->counters = calloc(27, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext1005_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext1005__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext1005__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext1005__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext1005__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ALL",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ALL",
                .desc = "Number of execution slots taken by instructions executed on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1005__xve_inst_executed_alu0_all__read,
                .max_uint64 = acmgt3__ext1005__xve_inst_executed_alu0_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1005__xve_inst_executed_alu0_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ALL",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ALL",
                .desc = "Number of execution slots taken by instructions executed on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1005__xve_inst_executed_alu1_all__read,
                .max_uint64 = acmgt3__ext1005__xve_inst_executed_alu1_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1005__xve_inst_executed_alu1_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED FP16",
                .symbol_name = "XVE_INST_EXECUTED_FP16",
                .desc = "Number of execution slots taken by FP16 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1005__xve_inst_executed_fp16__read,
                .max_uint64 = acmgt3__ext1005__xve_inst_executed_fp16__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED FP16 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_FP16_UTILIZATION",
                .desc = "Percentage of execution slots taken by FP16 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1005__xve_inst_executed_fp16_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED FP32",
                .symbol_name = "XVE_INST_EXECUTED_FP32",
                .desc = "Number of execution slots taken by FP32 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1005__xve_inst_executed_fp32__read,
                .max_uint64 = acmgt3__ext1005__xve_inst_executed_fp32__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED FP32 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_FP32_UTILIZATION",
                .desc = "Percentage of execution slots taken by FP32 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1005__xve_inst_executed_fp32_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED FP64",
                .symbol_name = "XVE_INST_EXECUTED_FP64",
                .desc = "The number of FLT64 instructions executed in ALU0 INT64 pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1005__xve_inst_executed_fp64__read,
                .max_uint64 = acmgt3__ext1005__xve_inst_executed_fp64__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED FP64 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_FP64_UTILIZATION",
                .desc = "The percentage of time in which FLT64 instruction were processed actively on FPU INT64 pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1005__xve_inst_executed_fp64_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED INT16",
                .symbol_name = "XVE_INST_EXECUTED_INT16",
                .desc = "Number of execution slots taken by INT16 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1005__xve_inst_executed_int16__read,
                .max_uint64 = acmgt3__ext1005__xve_inst_executed_int16__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED INT16 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_INT16_UTILIZATION",
                .desc = "Percentage of execution slots taken by INT16 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1005__xve_inst_executed_int16_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED INT32",
                .symbol_name = "XVE_INST_EXECUTED_INT32",
                .desc = "Number of execution slots taken by INT32 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1005__xve_inst_executed_int32__read,
                .max_uint64 = acmgt3__ext1005__xve_inst_executed_int32__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED INT32 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_INT32_UTILIZATION",
                .desc = "Percentage of execution slots taken by INT32 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1005__xve_inst_executed_int32_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED MATH",
                .symbol_name = "XVE_INST_EXECUTED_MATH",
                .desc = "Number of execution slots taken by extended math instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1005__xve_inst_executed_math__read,
                .max_uint64 = acmgt3__ext1005__xve_inst_executed_math__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED MATH UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_MATH_UTILIZATION",
                .desc = "Percentage of execution slots taken by extended math instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1005__xve_inst_executed_math_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX ALL",
                .symbol_name = "XVE_INST_EXECUTED_XMX_ALL",
                .desc = "Number of execution slots taken by instructions executed in XMX pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1005__xve_inst_executed_xmx_all__read,
                .max_uint64 = acmgt3__ext1005__xve_inst_executed_xmx_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_XMX_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed in XMX pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1005__xve_inst_executed_xmx_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX BF16",
                .symbol_name = "XVE_INST_EXECUTED_XMX_BF16",
                .desc = "Number of execution slots taken by BF16 XMX instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1005__xve_inst_executed_xmx_bf16__read,
                .max_uint64 = acmgt3__ext1005__xve_inst_executed_xmx_bf16__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX BF16 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_XMX_BF16_UTILIZATION",
                .desc = "Percentage of execution slots taken by BF16 XMX instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1005__xve_inst_executed_xmx_bf16_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX FP16",
                .symbol_name = "XVE_INST_EXECUTED_XMX_FP16",
                .desc = "Number of execution slots taken by FP16 XMX instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1005__xve_inst_executed_xmx_fp16__read,
                .max_uint64 = acmgt3__ext1005__xve_inst_executed_xmx_fp16__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX FP16 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_XMX_FP16_UTILIZATION",
                .desc = "Percentage of execution slots taken by FP16 XMX instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1005__xve_inst_executed_xmx_fp16_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX INT8",
                .symbol_name = "XVE_INST_EXECUTED_XMX_INT8",
                .desc = "Number of execution slots taken by INT8 XMX instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1005__xve_inst_executed_xmx_int8__read,
                .max_uint64 = acmgt3__ext1005__xve_inst_executed_xmx_int8__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX INT8 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_XMX_INT8_UTILIZATION",
                .desc = "Percentage of execution slots taken by INT8 XMX instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1005__xve_inst_executed_xmx_int8_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 27);
}


static void
acmgt3_add_ext1006_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1006";
    metric_set->symbol_name = "Ext1006";
    metric_set->hw_config_guid = "a864bceb-7b38-4248-9fc8-0f0f7b8c6426";
    metric_set->counters = calloc(23, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext1006_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext1006__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext1006__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext1006__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext1006__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST EXECUTED SEND ALL",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ALL",
                .desc = "Number of instructions executed on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1006__xve_inst_executed_send_all__read,
                .max_uint64 = acmgt3__ext1006__xve_inst_executed_send_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ALL_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1006__xve_inst_executed_send_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND ASYNC CS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ASYNC_CS",
                .desc = "Number of instructions executed by Async Compute Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1006__xve_inst_executed_send_async_cs__read,
                .max_uint64 = acmgt3__ext1006__xve_inst_executed_send_async_cs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND ASYNC CS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ASYNC_CS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Async Compute Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1006__xve_inst_executed_send_async_cs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND CS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_CS",
                .desc = "Number of instructions executed by Compute Shader (from Render Engine) threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1006__xve_inst_executed_send_cs__read,
                .max_uint64 = acmgt3__ext1006__xve_inst_executed_send_cs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND CS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_CS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Compute Shader (from Render Engine) threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1006__xve_inst_executed_send_cs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND DS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_DS",
                .desc = "Number of instructions executed by Domain Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1006__xve_inst_executed_send_ds__read,
                .max_uint64 = acmgt3__ext1006__xve_inst_executed_send_ds__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND DS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_DS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Domain Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1006__xve_inst_executed_send_ds_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND GS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_GS",
                .desc = "Number of instructions executed by Geometry Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1006__xve_inst_executed_send_gs__read,
                .max_uint64 = acmgt3__ext1006__xve_inst_executed_send_gs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND GS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_GS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Geometry Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1006__xve_inst_executed_send_gs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND HS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_HS",
                .desc = "Number of instructions executed by Hull Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1006__xve_inst_executed_send_hs__read,
                .max_uint64 = acmgt3__ext1006__xve_inst_executed_send_hs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND HS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_HS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Hull Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1006__xve_inst_executed_send_hs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND MS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_MS",
                .desc = "Number of instructions executed by Mesh Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1006__xve_inst_executed_send_ms__read,
                .max_uint64 = acmgt3__ext1006__xve_inst_executed_send_ms__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND MS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_MS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Mesh Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1006__xve_inst_executed_send_ms_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND FS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_PS",
                .desc = "Number of instructions executed by Fragment Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1006__xve_inst_executed_send_ps__read,
                .max_uint64 = acmgt3__ext1006__xve_inst_executed_send_ps__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND FS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_PS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Fragment Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1006__xve_inst_executed_send_ps_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND TS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_TS",
                .desc = "Number of instructions executed by Task Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1006__xve_inst_executed_send_ts__read,
                .max_uint64 = acmgt3__ext1006__xve_inst_executed_send_ts__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND TS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_TS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Task Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1006__xve_inst_executed_send_ts_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND VS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_VS",
                .desc = "Number of instructions executed by Vertex Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1006__xve_inst_executed_send_vs__read,
                .max_uint64 = acmgt3__ext1006__xve_inst_executed_send_vs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND VS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_VS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Vertex Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1006__xve_inst_executed_send_vs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 23);
}


static void
acmgt3_add_ext1007_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1007";
    metric_set->symbol_name = "Ext1007";
    metric_set->hw_config_guid = "361fc5ef-d568-4a9b-8ca2-d34707d10575";
    metric_set->counters = calloc(17, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext1007_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext1007__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext1007__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext1007__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext1007__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST EXECUTED ALU0 GS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_GS",
                .desc = "Number of execution slots taken by instructions executed by Geometry Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1007__xve_inst_executed_alu0_gs__read,
                .max_uint64 = acmgt3__ext1007__xve_inst_executed_alu0_gs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 GS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_GS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Geometry Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1007__xve_inst_executed_alu0_gs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 MS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_MS",
                .desc = "Number of execution slots taken by instructions executed by Mesh Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1007__xve_inst_executed_alu0_ms__read,
                .max_uint64 = acmgt3__ext1007__xve_inst_executed_alu0_ms__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 MS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_MS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Mesh Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1007__xve_inst_executed_alu0_ms_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 TS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_TS",
                .desc = "Number of execution slots taken by instructions executed by Task Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1007__xve_inst_executed_alu0_ts__read,
                .max_uint64 = acmgt3__ext1007__xve_inst_executed_alu0_ts__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 TS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_TS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Task Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1007__xve_inst_executed_alu0_ts_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 GS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_GS",
                .desc = "Number of execution slots taken by instructions executed by Geometry Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1007__xve_inst_executed_alu1_gs__read,
                .max_uint64 = acmgt3__ext1007__xve_inst_executed_alu1_gs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 GS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_GS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Geometry Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1007__xve_inst_executed_alu1_gs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 MS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_MS",
                .desc = "Number of execution slots taken by instructions executed by Mesh Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1007__xve_inst_executed_alu1_ms__read,
                .max_uint64 = acmgt3__ext1007__xve_inst_executed_alu1_ms__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 MS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_MS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Mesh Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1007__xve_inst_executed_alu1_ms_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 TS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_TS",
                .desc = "Number of execution slots taken by instructions executed by Task Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1007__xve_inst_executed_alu1_ts__read,
                .max_uint64 = acmgt3__ext1007__xve_inst_executed_alu1_ts__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 TS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_TS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Task Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1007__xve_inst_executed_alu1_ts_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES GS",
                .symbol_name = "XVE_STALL_CYCLES_GS",
                .desc = "Number of cycles there are Geometry Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt3__ext1007__xve_stall_cycles_gs__read,
                .max_uint64 = acmgt3__ext1007__xve_stall_cycles_gs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL GS",
                .symbol_name = "XVE_STALL_GS",
                .desc = "Percentage of time in which there are Geometry Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt3__ext1007__xve_stall_gs__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 17);
}


static void
acmgt3_add_ext1010_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1010";
    metric_set->symbol_name = "Ext1010";
    metric_set->hw_config_guid = "b5663ed9-0a8f-4a22-a3d4-a1ab08fad60f";
    metric_set->counters = calloc(8, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt3_ext1010_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt3__ext1010__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt3__ext1010__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt3__ext1010__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt3__ext1010__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL BLEND",
                .symbol_name = "PIXEL_BLEND",
                .desc = "Number of blended 2x2 pixels written to all render targets",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt3__ext1010__pixel_blend__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
            },

            {
                .name = "PIXEL WRITE",
                .symbol_name = "PIXEL_WRITE",
                .desc = "Number of 2x2 pixels written to all render targets",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt3__ext1010__pixel_write__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
            },

            {
                .name = "POSTPS DEPTH STENCIL ALPHA TEST FAIL",
                .symbol_name = "POSTPS_DEPTH_STENCIL_ALPHA_TEST_FAIL",
                .desc = "Number of 2x2 that were lit from Rasterizer but failed the depth stencil test or alpha test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt3__ext1010__postps_depth_stencil_alpha_test_fail__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
            },

            {
                .name = "RASTERIZER SAMPLE OUTPUT",
                .symbol_name = "RASTERIZER_SAMPLE_OUTPUT",
                .desc = "Number of lit samples emitted by Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt3__ext1010__rasterizer_sample_output__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
            },

            {
                .name = "SAMPLER 2X2 READ",
                .symbol_name = "SAMPLER_2X2_READ",
                .desc = "Number of 2x2 texel block requested from Sampler",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_TEXELS,
                .read_uint64 = acmgt3__ext1010__sampler_2_x2_read__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 8);
}

void
intel_perf_load_metrics_acmgt3(struct intel_perf *perf)
{
    acmgt3_add_render_basic_metric_set(perf);
    acmgt3_add_compute_basic_metric_set(perf);
    acmgt3_add_async_compute_metric_set(perf);
    acmgt3_add_xve_activity1_metric_set(perf);
    acmgt3_add_gpu_busyness_metric_set(perf);
    acmgt3_add_test_oa_metric_set(perf);
    acmgt3_add_hdc_and_sf__slice01_metric_set(perf);
    acmgt3_add_hdc_and_sf__slice23_metric_set(perf);
    acmgt3_add_hdc_and_sf__slice45_metric_set(perf);
    acmgt3_add_hdc_and_sf__slice67_metric_set(perf);
    acmgt3_add_hdc_and_sf1_metric_set(perf);
    acmgt3_add_l3__slice01_metric_set(perf);
    acmgt3_add_l3__slice23_metric_set(perf);
    acmgt3_add_l3__slice45_metric_set(perf);
    acmgt3_add_l3__slice67_metric_set(perf);
    acmgt3_add_rasterizer_and_pixel_backend1_metric_set(perf);
    acmgt3_add_rasterizer_and_pixel_backend2_metric_set(perf);
    acmgt3_add_rasterizer_and_pixel_backend3_metric_set(perf);
    acmgt3_add_rasterizer_and_pixel_backend4_metric_set(perf);
    acmgt3_add_rasterizer_and_pixel_backend5_metric_set(perf);
    acmgt3_add_render_pipe_profile__slice0_metric_set(perf);
    acmgt3_add_render_pipe_profile__slice1_metric_set(perf);
    acmgt3_add_render_pipe_profile__slice2_metric_set(perf);
    acmgt3_add_render_pipe_profile__slice3_metric_set(perf);
    acmgt3_add_render_pipe_profile__slice4_metric_set(perf);
    acmgt3_add_render_pipe_profile__slice5_metric_set(perf);
    acmgt3_add_render_pipe_profile__slice6_metric_set(perf);
    acmgt3_add_render_pipe_profile__slice7_metric_set(perf);
    acmgt3_add_sampler__slice01_metric_set(perf);
    acmgt3_add_sampler__slice23_metric_set(perf);
    acmgt3_add_sampler__slice45_metric_set(perf);
    acmgt3_add_sampler__slice67_metric_set(perf);
    acmgt3_add_tdl__slice01_1_metric_set(perf);
    acmgt3_add_tdl__slice01_2_metric_set(perf);
    acmgt3_add_tdl__slice01_3_metric_set(perf);
    acmgt3_add_tdl__slice01_4_metric_set(perf);
    acmgt3_add_tdl__slice23_1_metric_set(perf);
    acmgt3_add_tdl__slice23_2_metric_set(perf);
    acmgt3_add_tdl__slice23_3_metric_set(perf);
    acmgt3_add_tdl__slice23_4_metric_set(perf);
    acmgt3_add_tdl__slice45_1_metric_set(perf);
    acmgt3_add_tdl__slice45_2_metric_set(perf);
    acmgt3_add_tdl__slice45_3_metric_set(perf);
    acmgt3_add_tdl__slice45_4_metric_set(perf);
    acmgt3_add_tdl__slice67_1_metric_set(perf);
    acmgt3_add_tdl__slice67_2_metric_set(perf);
    acmgt3_add_tdl__slice67_3_metric_set(perf);
    acmgt3_add_tdl__slice67_4_metric_set(perf);
    acmgt3_add_compute_overview_metric_set(perf);
    acmgt3_add_l1_profile_reads__xe_core0_metric_set(perf);
    acmgt3_add_l1_profile_reads__xe_core3_metric_set(perf);
    acmgt3_add_l1_profile_slm_bank_conflicts__xe_core0_metric_set(perf);
    acmgt3_add_l1_profile_slm_bank_conflicts__xe_core3_metric_set(perf);
    acmgt3_add_l1_profile_writes__xe_core0_metric_set(perf);
    acmgt3_add_l1_profile_writes__xe_core3_metric_set(perf);
    acmgt3_add_dataport_reads_metric_set(perf);
    acmgt3_add_dataport_writes_metric_set(perf);
    acmgt3_add_ext1_metric_set(perf);
    acmgt3_add_ext2_metric_set(perf);
    acmgt3_add_ext3_metric_set(perf);
    acmgt3_add_ext4_metric_set(perf);
    acmgt3_add_ext5_metric_set(perf);
    acmgt3_add_ext6_metric_set(perf);
    acmgt3_add_ext7_metric_set(perf);
    acmgt3_add_ext8_metric_set(perf);
    acmgt3_add_ext9_metric_set(perf);
    acmgt3_add_ext10_metric_set(perf);
    acmgt3_add_ext11_metric_set(perf);
    acmgt3_add_ext12_metric_set(perf);
    acmgt3_add_ext13_metric_set(perf);
    acmgt3_add_ext14_metric_set(perf);
    acmgt3_add_ext15_metric_set(perf);
    acmgt3_add_ext16_metric_set(perf);
    acmgt3_add_ext17_metric_set(perf);
    acmgt3_add_ext18_metric_set(perf);
    acmgt3_add_ext19_metric_set(perf);
    acmgt3_add_ext20_metric_set(perf);
    acmgt3_add_ext21_metric_set(perf);
    acmgt3_add_ext22_metric_set(perf);
    acmgt3_add_ext23_metric_set(perf);
    acmgt3_add_ext24_metric_set(perf);
    acmgt3_add_ext27_metric_set(perf);
    acmgt3_add_ext28_metric_set(perf);
    acmgt3_add_ext29_metric_set(perf);
    acmgt3_add_ext30_metric_set(perf);
    acmgt3_add_ext31_metric_set(perf);
    acmgt3_add_ext32_metric_set(perf);
    acmgt3_add_ext33_metric_set(perf);
    acmgt3_add_ext34_metric_set(perf);
    acmgt3_add_ext35_metric_set(perf);
    acmgt3_add_ext36_metric_set(perf);
    acmgt3_add_ext37_metric_set(perf);
    acmgt3_add_ext38_metric_set(perf);
    acmgt3_add_ext39_metric_set(perf);
    acmgt3_add_ext40_metric_set(perf);
    acmgt3_add_ext41_metric_set(perf);
    acmgt3_add_ext42_metric_set(perf);
    acmgt3_add_ext43_metric_set(perf);
    acmgt3_add_ext44_metric_set(perf);
    acmgt3_add_ext45_metric_set(perf);
    acmgt3_add_ext46_metric_set(perf);
    acmgt3_add_ext47_metric_set(perf);
    acmgt3_add_ext48_metric_set(perf);
    acmgt3_add_ext49_metric_set(perf);
    acmgt3_add_ext50_metric_set(perf);
    acmgt3_add_ext51_metric_set(perf);
    acmgt3_add_ext52_metric_set(perf);
    acmgt3_add_ext53_metric_set(perf);
    acmgt3_add_ext54_metric_set(perf);
    acmgt3_add_ext55_metric_set(perf);
    acmgt3_add_ext56_metric_set(perf);
    acmgt3_add_ext57_metric_set(perf);
    acmgt3_add_ext58_metric_set(perf);
    acmgt3_add_ext59_metric_set(perf);
    acmgt3_add_ext60_metric_set(perf);
    acmgt3_add_ext61_metric_set(perf);
    acmgt3_add_ext62_metric_set(perf);
    acmgt3_add_ext63_metric_set(perf);
    acmgt3_add_ext64_metric_set(perf);
    acmgt3_add_ext65_metric_set(perf);
    acmgt3_add_ext66_metric_set(perf);
    acmgt3_add_ext67_metric_set(perf);
    acmgt3_add_ext68_metric_set(perf);
    acmgt3_add_ext69_metric_set(perf);
    acmgt3_add_ext70_metric_set(perf);
    acmgt3_add_ext71_metric_set(perf);
    acmgt3_add_ext72_metric_set(perf);
    acmgt3_add_ext73_metric_set(perf);
    acmgt3_add_ext74_metric_set(perf);
    acmgt3_add_ext75_metric_set(perf);
    acmgt3_add_ext76_metric_set(perf);
    acmgt3_add_ext77_metric_set(perf);
    acmgt3_add_ext78_metric_set(perf);
    acmgt3_add_ext79_metric_set(perf);
    acmgt3_add_ext80_metric_set(perf);
    acmgt3_add_ext81_metric_set(perf);
    acmgt3_add_ext82_metric_set(perf);
    acmgt3_add_ext83_metric_set(perf);
    acmgt3_add_ext84_metric_set(perf);
    acmgt3_add_ext85_metric_set(perf);
    acmgt3_add_ext86_metric_set(perf);
    acmgt3_add_ext87_metric_set(perf);
    acmgt3_add_ext88_metric_set(perf);
    acmgt3_add_ext89_metric_set(perf);
    acmgt3_add_ext90_metric_set(perf);
    acmgt3_add_ext91_metric_set(perf);
    acmgt3_add_ext92_metric_set(perf);
    acmgt3_add_ext93_metric_set(perf);
    acmgt3_add_ext94_metric_set(perf);
    acmgt3_add_ext95_metric_set(perf);
    acmgt3_add_ext96_metric_set(perf);
    acmgt3_add_ext97_metric_set(perf);
    acmgt3_add_ext98_metric_set(perf);
    acmgt3_add_ext99_metric_set(perf);
    acmgt3_add_ext100_metric_set(perf);
    acmgt3_add_ext101_metric_set(perf);
    acmgt3_add_ext102_metric_set(perf);
    acmgt3_add_ext103_metric_set(perf);
    acmgt3_add_ext104_metric_set(perf);
    acmgt3_add_ext105_metric_set(perf);
    acmgt3_add_ext106_metric_set(perf);
    acmgt3_add_ext107_metric_set(perf);
    acmgt3_add_ext108_metric_set(perf);
    acmgt3_add_ext109_metric_set(perf);
    acmgt3_add_ext110_metric_set(perf);
    acmgt3_add_ext111_metric_set(perf);
    acmgt3_add_ext112_metric_set(perf);
    acmgt3_add_ext113_metric_set(perf);
    acmgt3_add_ext114_metric_set(perf);
    acmgt3_add_ext115_metric_set(perf);
    acmgt3_add_ext116_metric_set(perf);
    acmgt3_add_ext117_metric_set(perf);
    acmgt3_add_ext118_metric_set(perf);
    acmgt3_add_ext119_metric_set(perf);
    acmgt3_add_ext120_metric_set(perf);
    acmgt3_add_ext121_metric_set(perf);
    acmgt3_add_ext122_metric_set(perf);
    acmgt3_add_ext123_metric_set(perf);
    acmgt3_add_ext124_metric_set(perf);
    acmgt3_add_ext125_metric_set(perf);
    acmgt3_add_ext126_metric_set(perf);
    acmgt3_add_ext127_metric_set(perf);
    acmgt3_add_ext128_metric_set(perf);
    acmgt3_add_ext129_metric_set(perf);
    acmgt3_add_ext130_metric_set(perf);
    acmgt3_add_ext131_metric_set(perf);
    acmgt3_add_ext132_metric_set(perf);
    acmgt3_add_ext133_metric_set(perf);
    acmgt3_add_ext134_metric_set(perf);
    acmgt3_add_ext135_metric_set(perf);
    acmgt3_add_ext136_metric_set(perf);
    acmgt3_add_ext137_metric_set(perf);
    acmgt3_add_ext138_metric_set(perf);
    acmgt3_add_ext139_metric_set(perf);
    acmgt3_add_ext140_metric_set(perf);
    acmgt3_add_ext141_metric_set(perf);
    acmgt3_add_ext142_metric_set(perf);
    acmgt3_add_ext143_metric_set(perf);
    acmgt3_add_ext144_metric_set(perf);
    acmgt3_add_ext145_metric_set(perf);
    acmgt3_add_ext146_metric_set(perf);
    acmgt3_add_ext147_metric_set(perf);
    acmgt3_add_ext148_metric_set(perf);
    acmgt3_add_ext149_metric_set(perf);
    acmgt3_add_ext150_metric_set(perf);
    acmgt3_add_ext151_metric_set(perf);
    acmgt3_add_ext152_metric_set(perf);
    acmgt3_add_ext153_metric_set(perf);
    acmgt3_add_ext154_metric_set(perf);
    acmgt3_add_ext155_metric_set(perf);
    acmgt3_add_ext156_metric_set(perf);
    acmgt3_add_ext157_metric_set(perf);
    acmgt3_add_ext158_metric_set(perf);
    acmgt3_add_ext159_metric_set(perf);
    acmgt3_add_ext160_metric_set(perf);
    acmgt3_add_ext161_metric_set(perf);
    acmgt3_add_ext162_metric_set(perf);
    acmgt3_add_ext163_metric_set(perf);
    acmgt3_add_ext164_metric_set(perf);
    acmgt3_add_ext165_metric_set(perf);
    acmgt3_add_ext166_metric_set(perf);
    acmgt3_add_ext167_metric_set(perf);
    acmgt3_add_ext168_metric_set(perf);
    acmgt3_add_ext169_metric_set(perf);
    acmgt3_add_ext170_metric_set(perf);
    acmgt3_add_ext171_metric_set(perf);
    acmgt3_add_ext172_metric_set(perf);
    acmgt3_add_ext173_metric_set(perf);
    acmgt3_add_ext174_metric_set(perf);
    acmgt3_add_ext175_metric_set(perf);
    acmgt3_add_ext176_metric_set(perf);
    acmgt3_add_ext177_metric_set(perf);
    acmgt3_add_ext178_metric_set(perf);
    acmgt3_add_ext179_metric_set(perf);
    acmgt3_add_ext180_metric_set(perf);
    acmgt3_add_ext181_metric_set(perf);
    acmgt3_add_ext182_metric_set(perf);
    acmgt3_add_ext183_metric_set(perf);
    acmgt3_add_ext184_metric_set(perf);
    acmgt3_add_ext185_metric_set(perf);
    acmgt3_add_ext186_metric_set(perf);
    acmgt3_add_ext187_metric_set(perf);
    acmgt3_add_ext188_metric_set(perf);
    acmgt3_add_ext189_metric_set(perf);
    acmgt3_add_ext190_metric_set(perf);
    acmgt3_add_ext191_metric_set(perf);
    acmgt3_add_ext192_metric_set(perf);
    acmgt3_add_ext193_metric_set(perf);
    acmgt3_add_ext194_metric_set(perf);
    acmgt3_add_ext195_metric_set(perf);
    acmgt3_add_ext196_metric_set(perf);
    acmgt3_add_ext197_metric_set(perf);
    acmgt3_add_ext198_metric_set(perf);
    acmgt3_add_ext199_metric_set(perf);
    acmgt3_add_ext200_metric_set(perf);
    acmgt3_add_ext201_metric_set(perf);
    acmgt3_add_ext202_metric_set(perf);
    acmgt3_add_ext203_metric_set(perf);
    acmgt3_add_ext204_metric_set(perf);
    acmgt3_add_ext205_metric_set(perf);
    acmgt3_add_ext206_metric_set(perf);
    acmgt3_add_ext207_metric_set(perf);
    acmgt3_add_ext208_metric_set(perf);
    acmgt3_add_ext209_metric_set(perf);
    acmgt3_add_ext210_metric_set(perf);
    acmgt3_add_ext211_metric_set(perf);
    acmgt3_add_ext212_metric_set(perf);
    acmgt3_add_ext213_metric_set(perf);
    acmgt3_add_ext214_metric_set(perf);
    acmgt3_add_ext215_metric_set(perf);
    acmgt3_add_ext216_metric_set(perf);
    acmgt3_add_ext217_metric_set(perf);
    acmgt3_add_ext218_metric_set(perf);
    acmgt3_add_ext219_metric_set(perf);
    acmgt3_add_ext220_metric_set(perf);
    acmgt3_add_ext221_metric_set(perf);
    acmgt3_add_ext222_metric_set(perf);
    acmgt3_add_ext223_metric_set(perf);
    acmgt3_add_ext224_metric_set(perf);
    acmgt3_add_ext225_metric_set(perf);
    acmgt3_add_ext226_metric_set(perf);
    acmgt3_add_ext227_metric_set(perf);
    acmgt3_add_ext228_metric_set(perf);
    acmgt3_add_ext229_metric_set(perf);
    acmgt3_add_ext230_metric_set(perf);
    acmgt3_add_ext231_metric_set(perf);
    acmgt3_add_ext232_metric_set(perf);
    acmgt3_add_ext233_metric_set(perf);
    acmgt3_add_ext234_metric_set(perf);
    acmgt3_add_ext235_metric_set(perf);
    acmgt3_add_ext236_metric_set(perf);
    acmgt3_add_ext237_metric_set(perf);
    acmgt3_add_ext238_metric_set(perf);
    acmgt3_add_ext239_metric_set(perf);
    acmgt3_add_ext240_metric_set(perf);
    acmgt3_add_ext241_metric_set(perf);
    acmgt3_add_ext242_metric_set(perf);
    acmgt3_add_ext243_metric_set(perf);
    acmgt3_add_ext244_metric_set(perf);
    acmgt3_add_ext245_metric_set(perf);
    acmgt3_add_ext246_metric_set(perf);
    acmgt3_add_ext247_metric_set(perf);
    acmgt3_add_ext248_metric_set(perf);
    acmgt3_add_ext249_metric_set(perf);
    acmgt3_add_ext250_metric_set(perf);
    acmgt3_add_ext251_metric_set(perf);
    acmgt3_add_ext252_metric_set(perf);
    acmgt3_add_ext253_metric_set(perf);
    acmgt3_add_ext254_metric_set(perf);
    acmgt3_add_ext255_metric_set(perf);
    acmgt3_add_ext256_metric_set(perf);
    acmgt3_add_ext257_metric_set(perf);
    acmgt3_add_ext258_metric_set(perf);
    acmgt3_add_ext259_metric_set(perf);
    acmgt3_add_ext260_metric_set(perf);
    acmgt3_add_ext261_metric_set(perf);
    acmgt3_add_ext262_metric_set(perf);
    acmgt3_add_ext263_metric_set(perf);
    acmgt3_add_ext264_metric_set(perf);
    acmgt3_add_ext265_metric_set(perf);
    acmgt3_add_ext266_metric_set(perf);
    acmgt3_add_ext267_metric_set(perf);
    acmgt3_add_ext268_metric_set(perf);
    acmgt3_add_ext269_metric_set(perf);
    acmgt3_add_ext270_metric_set(perf);
    acmgt3_add_ext271_metric_set(perf);
    acmgt3_add_ext272_metric_set(perf);
    acmgt3_add_ext273_metric_set(perf);
    acmgt3_add_ext274_metric_set(perf);
    acmgt3_add_ext275_metric_set(perf);
    acmgt3_add_ext276_metric_set(perf);
    acmgt3_add_ext277_metric_set(perf);
    acmgt3_add_ext278_metric_set(perf);
    acmgt3_add_ext279_metric_set(perf);
    acmgt3_add_ext280_metric_set(perf);
    acmgt3_add_ext281_metric_set(perf);
    acmgt3_add_ext282_metric_set(perf);
    acmgt3_add_ext283_metric_set(perf);
    acmgt3_add_ext284_metric_set(perf);
    acmgt3_add_ext285_metric_set(perf);
    acmgt3_add_ext286_metric_set(perf);
    acmgt3_add_ext288_metric_set(perf);
    acmgt3_add_ext289_metric_set(perf);
    acmgt3_add_ext290_metric_set(perf);
    acmgt3_add_ext291_metric_set(perf);
    acmgt3_add_ext292_metric_set(perf);
    acmgt3_add_ext293_metric_set(perf);
    acmgt3_add_ext294_metric_set(perf);
    acmgt3_add_ext295_metric_set(perf);
    acmgt3_add_ext296_metric_set(perf);
    acmgt3_add_ext297_metric_set(perf);
    acmgt3_add_ext298_metric_set(perf);
    acmgt3_add_ext299_metric_set(perf);
    acmgt3_add_ext300_metric_set(perf);
    acmgt3_add_ext301_metric_set(perf);
    acmgt3_add_ext302_metric_set(perf);
    acmgt3_add_ext303_metric_set(perf);
    acmgt3_add_ext304_metric_set(perf);
    acmgt3_add_ext305_metric_set(perf);
    acmgt3_add_ext306_metric_set(perf);
    acmgt3_add_ext307_metric_set(perf);
    acmgt3_add_ext308_metric_set(perf);
    acmgt3_add_ext309_metric_set(perf);
    acmgt3_add_ext310_metric_set(perf);
    acmgt3_add_ext311_metric_set(perf);
    acmgt3_add_ext312_metric_set(perf);
    acmgt3_add_ext313_metric_set(perf);
    acmgt3_add_ext314_metric_set(perf);
    acmgt3_add_ext315_metric_set(perf);
    acmgt3_add_ext316_metric_set(perf);
    acmgt3_add_ext317_metric_set(perf);
    acmgt3_add_ext318_metric_set(perf);
    acmgt3_add_ext319_metric_set(perf);
    acmgt3_add_ext320_metric_set(perf);
    acmgt3_add_ext321_metric_set(perf);
    acmgt3_add_ext322_metric_set(perf);
    acmgt3_add_ext323_metric_set(perf);
    acmgt3_add_ext324_metric_set(perf);
    acmgt3_add_ext325_metric_set(perf);
    acmgt3_add_ext326_metric_set(perf);
    acmgt3_add_ext327_metric_set(perf);
    acmgt3_add_ext328_metric_set(perf);
    acmgt3_add_ext329_metric_set(perf);
    acmgt3_add_ext330_metric_set(perf);
    acmgt3_add_ext331_metric_set(perf);
    acmgt3_add_ext332_metric_set(perf);
    acmgt3_add_ext333_metric_set(perf);
    acmgt3_add_ext334_metric_set(perf);
    acmgt3_add_ext335_metric_set(perf);
    acmgt3_add_ext342_metric_set(perf);
    acmgt3_add_ext343_metric_set(perf);
    acmgt3_add_ext344_metric_set(perf);
    acmgt3_add_ext345_metric_set(perf);
    acmgt3_add_ext346_metric_set(perf);
    acmgt3_add_ext347_metric_set(perf);
    acmgt3_add_ext348_metric_set(perf);
    acmgt3_add_ext349_metric_set(perf);
    acmgt3_add_ext350_metric_set(perf);
    acmgt3_add_ext351_metric_set(perf);
    acmgt3_add_ext352_metric_set(perf);
    acmgt3_add_ext353_metric_set(perf);
    acmgt3_add_ext354_metric_set(perf);
    acmgt3_add_ext355_metric_set(perf);
    acmgt3_add_ext356_metric_set(perf);
    acmgt3_add_ext357_metric_set(perf);
    acmgt3_add_ext358_metric_set(perf);
    acmgt3_add_ext359_metric_set(perf);
    acmgt3_add_ext360_metric_set(perf);
    acmgt3_add_ext361_metric_set(perf);
    acmgt3_add_ext362_metric_set(perf);
    acmgt3_add_ext363_metric_set(perf);
    acmgt3_add_ext364_metric_set(perf);
    acmgt3_add_ext365_metric_set(perf);
    acmgt3_add_ext366_metric_set(perf);
    acmgt3_add_ext367_metric_set(perf);
    acmgt3_add_ext368_metric_set(perf);
    acmgt3_add_ext369_metric_set(perf);
    acmgt3_add_ext370_metric_set(perf);
    acmgt3_add_ext371_metric_set(perf);
    acmgt3_add_ext372_metric_set(perf);
    acmgt3_add_ext373_metric_set(perf);
    acmgt3_add_ext374_metric_set(perf);
    acmgt3_add_ext375_metric_set(perf);
    acmgt3_add_ext376_metric_set(perf);
    acmgt3_add_ext377_metric_set(perf);
    acmgt3_add_ext378_metric_set(perf);
    acmgt3_add_ext379_metric_set(perf);
    acmgt3_add_ext380_metric_set(perf);
    acmgt3_add_ext381_metric_set(perf);
    acmgt3_add_ext382_metric_set(perf);
    acmgt3_add_ext383_metric_set(perf);
    acmgt3_add_ext384_metric_set(perf);
    acmgt3_add_ext385_metric_set(perf);
    acmgt3_add_ext386_metric_set(perf);
    acmgt3_add_ext387_metric_set(perf);
    acmgt3_add_ext388_metric_set(perf);
    acmgt3_add_ext389_metric_set(perf);
    acmgt3_add_ext390_metric_set(perf);
    acmgt3_add_ext391_metric_set(perf);
    acmgt3_add_ext392_metric_set(perf);
    acmgt3_add_ext393_metric_set(perf);
    acmgt3_add_ext394_metric_set(perf);
    acmgt3_add_ext395_metric_set(perf);
    acmgt3_add_ext396_metric_set(perf);
    acmgt3_add_ext397_metric_set(perf);
    acmgt3_add_ext398_metric_set(perf);
    acmgt3_add_ext399_metric_set(perf);
    acmgt3_add_ext400_metric_set(perf);
    acmgt3_add_ext401_metric_set(perf);
    acmgt3_add_ext402_metric_set(perf);
    acmgt3_add_ext403_metric_set(perf);
    acmgt3_add_ext404_metric_set(perf);
    acmgt3_add_ext405_metric_set(perf);
    acmgt3_add_ext406_metric_set(perf);
    acmgt3_add_ext407_metric_set(perf);
    acmgt3_add_ext408_metric_set(perf);
    acmgt3_add_ext409_metric_set(perf);
    acmgt3_add_ext410_metric_set(perf);
    acmgt3_add_ext411_metric_set(perf);
    acmgt3_add_ext412_metric_set(perf);
    acmgt3_add_ext413_metric_set(perf);
    acmgt3_add_ext414_metric_set(perf);
    acmgt3_add_ext415_metric_set(perf);
    acmgt3_add_ext416_metric_set(perf);
    acmgt3_add_ext417_metric_set(perf);
    acmgt3_add_ext418_metric_set(perf);
    acmgt3_add_ext419_metric_set(perf);
    acmgt3_add_ext420_metric_set(perf);
    acmgt3_add_ext421_metric_set(perf);
    acmgt3_add_ext422_metric_set(perf);
    acmgt3_add_ext423_metric_set(perf);
    acmgt3_add_ext424_metric_set(perf);
    acmgt3_add_ext425_metric_set(perf);
    acmgt3_add_ext426_metric_set(perf);
    acmgt3_add_ext427_metric_set(perf);
    acmgt3_add_ext428_metric_set(perf);
    acmgt3_add_ext429_metric_set(perf);
    acmgt3_add_ext430_metric_set(perf);
    acmgt3_add_ext431_metric_set(perf);
    acmgt3_add_ext432_metric_set(perf);
    acmgt3_add_ext433_metric_set(perf);
    acmgt3_add_ext434_metric_set(perf);
    acmgt3_add_ext435_metric_set(perf);
    acmgt3_add_ext436_metric_set(perf);
    acmgt3_add_ext437_metric_set(perf);
    acmgt3_add_ext438_metric_set(perf);
    acmgt3_add_ext439_metric_set(perf);
    acmgt3_add_ext440_metric_set(perf);
    acmgt3_add_ext441_metric_set(perf);
    acmgt3_add_ext442_metric_set(perf);
    acmgt3_add_ext443_metric_set(perf);
    acmgt3_add_ext444_metric_set(perf);
    acmgt3_add_ext445_metric_set(perf);
    acmgt3_add_ext446_metric_set(perf);
    acmgt3_add_ext447_metric_set(perf);
    acmgt3_add_ext448_metric_set(perf);
    acmgt3_add_ext449_metric_set(perf);
    acmgt3_add_ext450_metric_set(perf);
    acmgt3_add_ext451_metric_set(perf);
    acmgt3_add_ext452_metric_set(perf);
    acmgt3_add_ext453_metric_set(perf);
    acmgt3_add_ext454_metric_set(perf);
    acmgt3_add_ext455_metric_set(perf);
    acmgt3_add_ext456_metric_set(perf);
    acmgt3_add_ext457_metric_set(perf);
    acmgt3_add_ext458_metric_set(perf);
    acmgt3_add_ext459_metric_set(perf);
    acmgt3_add_ext460_metric_set(perf);
    acmgt3_add_ext461_metric_set(perf);
    acmgt3_add_ext462_metric_set(perf);
    acmgt3_add_ext463_metric_set(perf);
    acmgt3_add_ext464_metric_set(perf);
    acmgt3_add_ext465_metric_set(perf);
    acmgt3_add_ext466_metric_set(perf);
    acmgt3_add_ext467_metric_set(perf);
    acmgt3_add_ext468_metric_set(perf);
    acmgt3_add_ext469_metric_set(perf);
    acmgt3_add_ext470_metric_set(perf);
    acmgt3_add_ext471_metric_set(perf);
    acmgt3_add_ext472_metric_set(perf);
    acmgt3_add_ext473_metric_set(perf);
    acmgt3_add_ext474_metric_set(perf);
    acmgt3_add_ext475_metric_set(perf);
    acmgt3_add_ext476_metric_set(perf);
    acmgt3_add_ext477_metric_set(perf);
    acmgt3_add_ext478_metric_set(perf);
    acmgt3_add_ext479_metric_set(perf);
    acmgt3_add_ext480_metric_set(perf);
    acmgt3_add_ext481_metric_set(perf);
    acmgt3_add_ext482_metric_set(perf);
    acmgt3_add_ext483_metric_set(perf);
    acmgt3_add_ext484_metric_set(perf);
    acmgt3_add_ext485_metric_set(perf);
    acmgt3_add_ext486_metric_set(perf);
    acmgt3_add_ext487_metric_set(perf);
    acmgt3_add_ext488_metric_set(perf);
    acmgt3_add_ext489_metric_set(perf);
    acmgt3_add_ext490_metric_set(perf);
    acmgt3_add_ext491_metric_set(perf);
    acmgt3_add_ext492_metric_set(perf);
    acmgt3_add_ext493_metric_set(perf);
    acmgt3_add_ext494_metric_set(perf);
    acmgt3_add_ext495_metric_set(perf);
    acmgt3_add_ext496_metric_set(perf);
    acmgt3_add_ext497_metric_set(perf);
    acmgt3_add_ext498_metric_set(perf);
    acmgt3_add_ext499_metric_set(perf);
    acmgt3_add_ext500_metric_set(perf);
    acmgt3_add_ext501_metric_set(perf);
    acmgt3_add_ext502_metric_set(perf);
    acmgt3_add_ext503_metric_set(perf);
    acmgt3_add_ext504_metric_set(perf);
    acmgt3_add_ext505_metric_set(perf);
    acmgt3_add_ext506_metric_set(perf);
    acmgt3_add_ext507_metric_set(perf);
    acmgt3_add_ext508_metric_set(perf);
    acmgt3_add_ext509_metric_set(perf);
    acmgt3_add_ext510_metric_set(perf);
    acmgt3_add_ext511_metric_set(perf);
    acmgt3_add_ext512_metric_set(perf);
    acmgt3_add_ext513_metric_set(perf);
    acmgt3_add_ext514_metric_set(perf);
    acmgt3_add_ext515_metric_set(perf);
    acmgt3_add_ext516_metric_set(perf);
    acmgt3_add_ext517_metric_set(perf);
    acmgt3_add_ext518_metric_set(perf);
    acmgt3_add_ext519_metric_set(perf);
    acmgt3_add_ext520_metric_set(perf);
    acmgt3_add_ext521_metric_set(perf);
    acmgt3_add_ext522_metric_set(perf);
    acmgt3_add_ext523_metric_set(perf);
    acmgt3_add_ext524_metric_set(perf);
    acmgt3_add_ext525_metric_set(perf);
    acmgt3_add_ext526_metric_set(perf);
    acmgt3_add_ext527_metric_set(perf);
    acmgt3_add_ext528_metric_set(perf);
    acmgt3_add_ext529_metric_set(perf);
    acmgt3_add_ext530_metric_set(perf);
    acmgt3_add_ext531_metric_set(perf);
    acmgt3_add_ext532_metric_set(perf);
    acmgt3_add_ext533_metric_set(perf);
    acmgt3_add_ext534_metric_set(perf);
    acmgt3_add_ext535_metric_set(perf);
    acmgt3_add_ext536_metric_set(perf);
    acmgt3_add_ext537_metric_set(perf);
    acmgt3_add_ext538_metric_set(perf);
    acmgt3_add_ext539_metric_set(perf);
    acmgt3_add_ext540_metric_set(perf);
    acmgt3_add_ext541_metric_set(perf);
    acmgt3_add_ext542_metric_set(perf);
    acmgt3_add_ext543_metric_set(perf);
    acmgt3_add_ext544_metric_set(perf);
    acmgt3_add_ext545_metric_set(perf);
    acmgt3_add_ext546_metric_set(perf);
    acmgt3_add_ext547_metric_set(perf);
    acmgt3_add_ext548_metric_set(perf);
    acmgt3_add_ext549_metric_set(perf);
    acmgt3_add_ext550_metric_set(perf);
    acmgt3_add_ext551_metric_set(perf);
    acmgt3_add_ext552_metric_set(perf);
    acmgt3_add_ext553_metric_set(perf);
    acmgt3_add_ext554_metric_set(perf);
    acmgt3_add_ext555_metric_set(perf);
    acmgt3_add_ext556_metric_set(perf);
    acmgt3_add_ext557_metric_set(perf);
    acmgt3_add_ext558_metric_set(perf);
    acmgt3_add_ext559_metric_set(perf);
    acmgt3_add_ext560_metric_set(perf);
    acmgt3_add_ext561_metric_set(perf);
    acmgt3_add_ext562_metric_set(perf);
    acmgt3_add_ext563_metric_set(perf);
    acmgt3_add_ext564_metric_set(perf);
    acmgt3_add_ext565_metric_set(perf);
    acmgt3_add_ext566_metric_set(perf);
    acmgt3_add_ext567_metric_set(perf);
    acmgt3_add_ext568_metric_set(perf);
    acmgt3_add_ext569_metric_set(perf);
    acmgt3_add_ext570_metric_set(perf);
    acmgt3_add_ext571_metric_set(perf);
    acmgt3_add_ext572_metric_set(perf);
    acmgt3_add_ext573_metric_set(perf);
    acmgt3_add_ext574_metric_set(perf);
    acmgt3_add_ext575_metric_set(perf);
    acmgt3_add_ext576_metric_set(perf);
    acmgt3_add_ext577_metric_set(perf);
    acmgt3_add_ext578_metric_set(perf);
    acmgt3_add_ext579_metric_set(perf);
    acmgt3_add_ext580_metric_set(perf);
    acmgt3_add_ext581_metric_set(perf);
    acmgt3_add_ext582_metric_set(perf);
    acmgt3_add_ext583_metric_set(perf);
    acmgt3_add_ext584_metric_set(perf);
    acmgt3_add_ext585_metric_set(perf);
    acmgt3_add_ext586_metric_set(perf);
    acmgt3_add_ext587_metric_set(perf);
    acmgt3_add_ext588_metric_set(perf);
    acmgt3_add_ext589_metric_set(perf);
    acmgt3_add_ext590_metric_set(perf);
    acmgt3_add_ext591_metric_set(perf);
    acmgt3_add_ext592_metric_set(perf);
    acmgt3_add_ext593_metric_set(perf);
    acmgt3_add_ext594_metric_set(perf);
    acmgt3_add_ext595_metric_set(perf);
    acmgt3_add_ext596_metric_set(perf);
    acmgt3_add_ext597_metric_set(perf);
    acmgt3_add_ext598_metric_set(perf);
    acmgt3_add_ext599_metric_set(perf);
    acmgt3_add_ext600_metric_set(perf);
    acmgt3_add_ext601_metric_set(perf);
    acmgt3_add_ext602_metric_set(perf);
    acmgt3_add_ext603_metric_set(perf);
    acmgt3_add_ext604_metric_set(perf);
    acmgt3_add_ext605_metric_set(perf);
    acmgt3_add_ext606_metric_set(perf);
    acmgt3_add_ext607_metric_set(perf);
    acmgt3_add_ext608_metric_set(perf);
    acmgt3_add_ext609_metric_set(perf);
    acmgt3_add_ext610_metric_set(perf);
    acmgt3_add_ext611_metric_set(perf);
    acmgt3_add_ext612_metric_set(perf);
    acmgt3_add_ext613_metric_set(perf);
    acmgt3_add_ext614_metric_set(perf);
    acmgt3_add_ext615_metric_set(perf);
    acmgt3_add_ext616_metric_set(perf);
    acmgt3_add_ext617_metric_set(perf);
    acmgt3_add_ext618_metric_set(perf);
    acmgt3_add_ext619_metric_set(perf);
    acmgt3_add_ext620_metric_set(perf);
    acmgt3_add_ext621_metric_set(perf);
    acmgt3_add_ext622_metric_set(perf);
    acmgt3_add_ext623_metric_set(perf);
    acmgt3_add_ext624_metric_set(perf);
    acmgt3_add_ext625_metric_set(perf);
    acmgt3_add_ext626_metric_set(perf);
    acmgt3_add_ext627_metric_set(perf);
    acmgt3_add_ext628_metric_set(perf);
    acmgt3_add_ext629_metric_set(perf);
    acmgt3_add_ext630_metric_set(perf);
    acmgt3_add_ext631_metric_set(perf);
    acmgt3_add_ext632_metric_set(perf);
    acmgt3_add_ext633_metric_set(perf);
    acmgt3_add_ext634_metric_set(perf);
    acmgt3_add_ext635_metric_set(perf);
    acmgt3_add_ext636_metric_set(perf);
    acmgt3_add_ext637_metric_set(perf);
    acmgt3_add_ext638_metric_set(perf);
    acmgt3_add_ext639_metric_set(perf);
    acmgt3_add_ext640_metric_set(perf);
    acmgt3_add_ext641_metric_set(perf);
    acmgt3_add_ext642_metric_set(perf);
    acmgt3_add_ext643_metric_set(perf);
    acmgt3_add_ext644_metric_set(perf);
    acmgt3_add_ext645_metric_set(perf);
    acmgt3_add_ext646_metric_set(perf);
    acmgt3_add_ext647_metric_set(perf);
    acmgt3_add_ext648_metric_set(perf);
    acmgt3_add_ext649_metric_set(perf);
    acmgt3_add_ext650_metric_set(perf);
    acmgt3_add_ext651_metric_set(perf);
    acmgt3_add_ext652_metric_set(perf);
    acmgt3_add_ext653_metric_set(perf);
    acmgt3_add_ext654_metric_set(perf);
    acmgt3_add_ext655_metric_set(perf);
    acmgt3_add_ext656_metric_set(perf);
    acmgt3_add_ext657_metric_set(perf);
    acmgt3_add_ext658_metric_set(perf);
    acmgt3_add_ext659_metric_set(perf);
    acmgt3_add_ext660_metric_set(perf);
    acmgt3_add_ext661_metric_set(perf);
    acmgt3_add_ext662_metric_set(perf);
    acmgt3_add_ext663_metric_set(perf);
    acmgt3_add_ext664_metric_set(perf);
    acmgt3_add_ext665_metric_set(perf);
    acmgt3_add_ext666_metric_set(perf);
    acmgt3_add_ext667_metric_set(perf);
    acmgt3_add_ext668_metric_set(perf);
    acmgt3_add_ext669_metric_set(perf);
    acmgt3_add_ext670_metric_set(perf);
    acmgt3_add_ext671_metric_set(perf);
    acmgt3_add_ext672_metric_set(perf);
    acmgt3_add_ext673_metric_set(perf);
    acmgt3_add_ext674_metric_set(perf);
    acmgt3_add_ext675_metric_set(perf);
    acmgt3_add_ext676_metric_set(perf);
    acmgt3_add_ext677_metric_set(perf);
    acmgt3_add_ext678_metric_set(perf);
    acmgt3_add_ext679_metric_set(perf);
    acmgt3_add_ext680_metric_set(perf);
    acmgt3_add_ext681_metric_set(perf);
    acmgt3_add_ext682_metric_set(perf);
    acmgt3_add_ext683_metric_set(perf);
    acmgt3_add_ext684_metric_set(perf);
    acmgt3_add_ext685_metric_set(perf);
    acmgt3_add_ext686_metric_set(perf);
    acmgt3_add_ext687_metric_set(perf);
    acmgt3_add_ext688_metric_set(perf);
    acmgt3_add_ext689_metric_set(perf);
    acmgt3_add_ext690_metric_set(perf);
    acmgt3_add_ext691_metric_set(perf);
    acmgt3_add_ext692_metric_set(perf);
    acmgt3_add_ext693_metric_set(perf);
    acmgt3_add_ext694_metric_set(perf);
    acmgt3_add_ext695_metric_set(perf);
    acmgt3_add_ext696_metric_set(perf);
    acmgt3_add_ext697_metric_set(perf);
    acmgt3_add_ext698_metric_set(perf);
    acmgt3_add_ext699_metric_set(perf);
    acmgt3_add_ext700_metric_set(perf);
    acmgt3_add_ext701_metric_set(perf);
    acmgt3_add_ext702_metric_set(perf);
    acmgt3_add_ext703_metric_set(perf);
    acmgt3_add_ext704_metric_set(perf);
    acmgt3_add_ext705_metric_set(perf);
    acmgt3_add_ext706_metric_set(perf);
    acmgt3_add_ext707_metric_set(perf);
    acmgt3_add_ext708_metric_set(perf);
    acmgt3_add_ext709_metric_set(perf);
    acmgt3_add_ext710_metric_set(perf);
    acmgt3_add_ext711_metric_set(perf);
    acmgt3_add_ext712_metric_set(perf);
    acmgt3_add_ext713_metric_set(perf);
    acmgt3_add_ext714_metric_set(perf);
    acmgt3_add_ext715_metric_set(perf);
    acmgt3_add_ext716_metric_set(perf);
    acmgt3_add_ext717_metric_set(perf);
    acmgt3_add_ext718_metric_set(perf);
    acmgt3_add_ext719_metric_set(perf);
    acmgt3_add_ext720_metric_set(perf);
    acmgt3_add_ext721_metric_set(perf);
    acmgt3_add_ext722_metric_set(perf);
    acmgt3_add_ext723_metric_set(perf);
    acmgt3_add_ext724_metric_set(perf);
    acmgt3_add_ext725_metric_set(perf);
    acmgt3_add_ext726_metric_set(perf);
    acmgt3_add_ext727_metric_set(perf);
    acmgt3_add_ext728_metric_set(perf);
    acmgt3_add_ext729_metric_set(perf);
    acmgt3_add_ext730_metric_set(perf);
    acmgt3_add_ext731_metric_set(perf);
    acmgt3_add_ext732_metric_set(perf);
    acmgt3_add_ext733_metric_set(perf);
    acmgt3_add_ext734_metric_set(perf);
    acmgt3_add_ext735_metric_set(perf);
    acmgt3_add_ext736_metric_set(perf);
    acmgt3_add_ext737_metric_set(perf);
    acmgt3_add_ext738_metric_set(perf);
    acmgt3_add_ext739_metric_set(perf);
    acmgt3_add_ext740_metric_set(perf);
    acmgt3_add_ext741_metric_set(perf);
    acmgt3_add_ext742_metric_set(perf);
    acmgt3_add_ext743_metric_set(perf);
    acmgt3_add_ext744_metric_set(perf);
    acmgt3_add_ext745_metric_set(perf);
    acmgt3_add_ext746_metric_set(perf);
    acmgt3_add_ext747_metric_set(perf);
    acmgt3_add_ext748_metric_set(perf);
    acmgt3_add_ext749_metric_set(perf);
    acmgt3_add_ext750_metric_set(perf);
    acmgt3_add_ext751_metric_set(perf);
    acmgt3_add_ext752_metric_set(perf);
    acmgt3_add_ext753_metric_set(perf);
    acmgt3_add_ext754_metric_set(perf);
    acmgt3_add_ext755_metric_set(perf);
    acmgt3_add_ext756_metric_set(perf);
    acmgt3_add_ext757_metric_set(perf);
    acmgt3_add_ext758_metric_set(perf);
    acmgt3_add_ext759_metric_set(perf);
    acmgt3_add_ext760_metric_set(perf);
    acmgt3_add_ext761_metric_set(perf);
    acmgt3_add_ext762_metric_set(perf);
    acmgt3_add_ext763_metric_set(perf);
    acmgt3_add_ext764_metric_set(perf);
    acmgt3_add_ext765_metric_set(perf);
    acmgt3_add_ext766_metric_set(perf);
    acmgt3_add_ext767_metric_set(perf);
    acmgt3_add_ext768_metric_set(perf);
    acmgt3_add_ext769_metric_set(perf);
    acmgt3_add_ext770_metric_set(perf);
    acmgt3_add_ext771_metric_set(perf);
    acmgt3_add_ext772_metric_set(perf);
    acmgt3_add_ext773_metric_set(perf);
    acmgt3_add_ext774_metric_set(perf);
    acmgt3_add_ext775_metric_set(perf);
    acmgt3_add_ext776_metric_set(perf);
    acmgt3_add_ext777_metric_set(perf);
    acmgt3_add_ext778_metric_set(perf);
    acmgt3_add_ext779_metric_set(perf);
    acmgt3_add_ext780_metric_set(perf);
    acmgt3_add_ext781_metric_set(perf);
    acmgt3_add_ext782_metric_set(perf);
    acmgt3_add_ext783_metric_set(perf);
    acmgt3_add_ext784_metric_set(perf);
    acmgt3_add_ext785_metric_set(perf);
    acmgt3_add_ext786_metric_set(perf);
    acmgt3_add_ext787_metric_set(perf);
    acmgt3_add_ext788_metric_set(perf);
    acmgt3_add_ext789_metric_set(perf);
    acmgt3_add_ext790_metric_set(perf);
    acmgt3_add_ext791_metric_set(perf);
    acmgt3_add_ext792_metric_set(perf);
    acmgt3_add_ext793_metric_set(perf);
    acmgt3_add_ext794_metric_set(perf);
    acmgt3_add_ext795_metric_set(perf);
    acmgt3_add_ext796_metric_set(perf);
    acmgt3_add_ext797_metric_set(perf);
    acmgt3_add_ext798_metric_set(perf);
    acmgt3_add_ext799_metric_set(perf);
    acmgt3_add_ext800_metric_set(perf);
    acmgt3_add_ext801_metric_set(perf);
    acmgt3_add_ext802_metric_set(perf);
    acmgt3_add_ext803_metric_set(perf);
    acmgt3_add_ext804_metric_set(perf);
    acmgt3_add_ext805_metric_set(perf);
    acmgt3_add_ext806_metric_set(perf);
    acmgt3_add_ext807_metric_set(perf);
    acmgt3_add_ext808_metric_set(perf);
    acmgt3_add_ext809_metric_set(perf);
    acmgt3_add_ext810_metric_set(perf);
    acmgt3_add_ext811_metric_set(perf);
    acmgt3_add_ext812_metric_set(perf);
    acmgt3_add_ext813_metric_set(perf);
    acmgt3_add_ext814_metric_set(perf);
    acmgt3_add_ext815_metric_set(perf);
    acmgt3_add_ext816_metric_set(perf);
    acmgt3_add_ext817_metric_set(perf);
    acmgt3_add_ext818_metric_set(perf);
    acmgt3_add_ext819_metric_set(perf);
    acmgt3_add_ext820_metric_set(perf);
    acmgt3_add_ext821_metric_set(perf);
    acmgt3_add_ext822_metric_set(perf);
    acmgt3_add_ext823_metric_set(perf);
    acmgt3_add_ext824_metric_set(perf);
    acmgt3_add_ext825_metric_set(perf);
    acmgt3_add_ext826_metric_set(perf);
    acmgt3_add_ext827_metric_set(perf);
    acmgt3_add_ext828_metric_set(perf);
    acmgt3_add_ext829_metric_set(perf);
    acmgt3_add_ext830_metric_set(perf);
    acmgt3_add_ext831_metric_set(perf);
    acmgt3_add_ext832_metric_set(perf);
    acmgt3_add_ext833_metric_set(perf);
    acmgt3_add_ext834_metric_set(perf);
    acmgt3_add_ext835_metric_set(perf);
    acmgt3_add_ext836_metric_set(perf);
    acmgt3_add_ext837_metric_set(perf);
    acmgt3_add_ext838_metric_set(perf);
    acmgt3_add_ext839_metric_set(perf);
    acmgt3_add_ext840_metric_set(perf);
    acmgt3_add_ext841_metric_set(perf);
    acmgt3_add_ext842_metric_set(perf);
    acmgt3_add_ext843_metric_set(perf);
    acmgt3_add_ext844_metric_set(perf);
    acmgt3_add_ext845_metric_set(perf);
    acmgt3_add_ext846_metric_set(perf);
    acmgt3_add_ext847_metric_set(perf);
    acmgt3_add_ext848_metric_set(perf);
    acmgt3_add_ext849_metric_set(perf);
    acmgt3_add_ext850_metric_set(perf);
    acmgt3_add_ext851_metric_set(perf);
    acmgt3_add_ext852_metric_set(perf);
    acmgt3_add_ext853_metric_set(perf);
    acmgt3_add_ext854_metric_set(perf);
    acmgt3_add_ext855_metric_set(perf);
    acmgt3_add_ext856_metric_set(perf);
    acmgt3_add_ext857_metric_set(perf);
    acmgt3_add_ext858_metric_set(perf);
    acmgt3_add_ext859_metric_set(perf);
    acmgt3_add_ext860_metric_set(perf);
    acmgt3_add_ext861_metric_set(perf);
    acmgt3_add_ext862_metric_set(perf);
    acmgt3_add_ext863_metric_set(perf);
    acmgt3_add_ext864_metric_set(perf);
    acmgt3_add_ext865_metric_set(perf);
    acmgt3_add_ext866_metric_set(perf);
    acmgt3_add_ext867_metric_set(perf);
    acmgt3_add_ext868_metric_set(perf);
    acmgt3_add_ext869_metric_set(perf);
    acmgt3_add_ext870_metric_set(perf);
    acmgt3_add_ext871_metric_set(perf);
    acmgt3_add_ext872_metric_set(perf);
    acmgt3_add_ext873_metric_set(perf);
    acmgt3_add_ext874_metric_set(perf);
    acmgt3_add_ext875_metric_set(perf);
    acmgt3_add_ext876_metric_set(perf);
    acmgt3_add_ext877_metric_set(perf);
    acmgt3_add_ext878_metric_set(perf);
    acmgt3_add_ext879_metric_set(perf);
    acmgt3_add_ext880_metric_set(perf);
    acmgt3_add_ext881_metric_set(perf);
    acmgt3_add_ext882_metric_set(perf);
    acmgt3_add_ext883_metric_set(perf);
    acmgt3_add_ext884_metric_set(perf);
    acmgt3_add_ext885_metric_set(perf);
    acmgt3_add_ext886_metric_set(perf);
    acmgt3_add_ext887_metric_set(perf);
    acmgt3_add_ext888_metric_set(perf);
    acmgt3_add_ext889_metric_set(perf);
    acmgt3_add_ext890_metric_set(perf);
    acmgt3_add_ext891_metric_set(perf);
    acmgt3_add_ext892_metric_set(perf);
    acmgt3_add_ext893_metric_set(perf);
    acmgt3_add_ext894_metric_set(perf);
    acmgt3_add_ext895_metric_set(perf);
    acmgt3_add_ext896_metric_set(perf);
    acmgt3_add_ext897_metric_set(perf);
    acmgt3_add_ext898_metric_set(perf);
    acmgt3_add_ext899_metric_set(perf);
    acmgt3_add_ext900_metric_set(perf);
    acmgt3_add_ext901_metric_set(perf);
    acmgt3_add_ext902_metric_set(perf);
    acmgt3_add_ext903_metric_set(perf);
    acmgt3_add_ext904_metric_set(perf);
    acmgt3_add_ext905_metric_set(perf);
    acmgt3_add_ext906_metric_set(perf);
    acmgt3_add_ext907_metric_set(perf);
    acmgt3_add_ext908_metric_set(perf);
    acmgt3_add_ext909_metric_set(perf);
    acmgt3_add_ext910_metric_set(perf);
    acmgt3_add_ext911_metric_set(perf);
    acmgt3_add_ext912_metric_set(perf);
    acmgt3_add_ext913_metric_set(perf);
    acmgt3_add_ext914_metric_set(perf);
    acmgt3_add_ext915_metric_set(perf);
    acmgt3_add_ext916_metric_set(perf);
    acmgt3_add_ext917_metric_set(perf);
    acmgt3_add_ext918_metric_set(perf);
    acmgt3_add_ext919_metric_set(perf);
    acmgt3_add_ext920_metric_set(perf);
    acmgt3_add_ext921_metric_set(perf);
    acmgt3_add_ext922_metric_set(perf);
    acmgt3_add_ext923_metric_set(perf);
    acmgt3_add_ext924_metric_set(perf);
    acmgt3_add_ext925_metric_set(perf);
    acmgt3_add_ext926_metric_set(perf);
    acmgt3_add_ext927_metric_set(perf);
    acmgt3_add_ext928_metric_set(perf);
    acmgt3_add_ext929_metric_set(perf);
    acmgt3_add_ext930_metric_set(perf);
    acmgt3_add_ext931_metric_set(perf);
    acmgt3_add_ext932_metric_set(perf);
    acmgt3_add_ext933_metric_set(perf);
    acmgt3_add_ext934_metric_set(perf);
    acmgt3_add_ext935_metric_set(perf);
    acmgt3_add_ext936_metric_set(perf);
    acmgt3_add_ext937_metric_set(perf);
    acmgt3_add_ext938_metric_set(perf);
    acmgt3_add_ext939_metric_set(perf);
    acmgt3_add_ext940_metric_set(perf);
    acmgt3_add_ext941_metric_set(perf);
    acmgt3_add_ext942_metric_set(perf);
    acmgt3_add_ext943_metric_set(perf);
    acmgt3_add_ext944_metric_set(perf);
    acmgt3_add_ext945_metric_set(perf);
    acmgt3_add_ext946_metric_set(perf);
    acmgt3_add_ext947_metric_set(perf);
    acmgt3_add_ext948_metric_set(perf);
    acmgt3_add_ext949_metric_set(perf);
    acmgt3_add_ext950_metric_set(perf);
    acmgt3_add_ext951_metric_set(perf);
    acmgt3_add_ext952_metric_set(perf);
    acmgt3_add_ext953_metric_set(perf);
    acmgt3_add_ext954_metric_set(perf);
    acmgt3_add_ext955_metric_set(perf);
    acmgt3_add_ext956_metric_set(perf);
    acmgt3_add_ext957_metric_set(perf);
    acmgt3_add_ext958_metric_set(perf);
    acmgt3_add_ext959_metric_set(perf);
    acmgt3_add_ext960_metric_set(perf);
    acmgt3_add_ext961_metric_set(perf);
    acmgt3_add_ext962_metric_set(perf);
    acmgt3_add_ext963_metric_set(perf);
    acmgt3_add_ext964_metric_set(perf);
    acmgt3_add_ext965_metric_set(perf);
    acmgt3_add_ext966_metric_set(perf);
    acmgt3_add_ext967_metric_set(perf);
    acmgt3_add_ext968_metric_set(perf);
    acmgt3_add_ext969_metric_set(perf);
    acmgt3_add_ext970_metric_set(perf);
    acmgt3_add_ext971_metric_set(perf);
    acmgt3_add_ext972_metric_set(perf);
    acmgt3_add_ext973_metric_set(perf);
    acmgt3_add_ext974_metric_set(perf);
    acmgt3_add_ext975_metric_set(perf);
    acmgt3_add_ext976_metric_set(perf);
    acmgt3_add_ext977_metric_set(perf);
    acmgt3_add_ext978_metric_set(perf);
    acmgt3_add_ext979_metric_set(perf);
    acmgt3_add_ext980_metric_set(perf);
    acmgt3_add_ext981_metric_set(perf);
    acmgt3_add_ext982_metric_set(perf);
    acmgt3_add_ext983_metric_set(perf);
    acmgt3_add_ext984_metric_set(perf);
    acmgt3_add_ext985_metric_set(perf);
    acmgt3_add_ext986_metric_set(perf);
    acmgt3_add_ext987_metric_set(perf);
    acmgt3_add_ext1000_metric_set(perf);
    acmgt3_add_ext1001_metric_set(perf);
    acmgt3_add_ext1002_metric_set(perf);
    acmgt3_add_ext1004_metric_set(perf);
    acmgt3_add_ext1005_metric_set(perf);
    acmgt3_add_ext1006_metric_set(perf);
    acmgt3_add_ext1007_metric_set(perf);
    acmgt3_add_ext1010_metric_set(perf);
}
