/* Autogenerated file, DO NOT EDIT manually! generated by oa-registers-codegen.py */
// SPDX-License-Identifier: MIT
/*
 * Copyright © 2024 Intel Corporation
 */

#ifndef __XE_OA_REGISTERS_PTL_H__
#define __XE_OA_REGISTERS_PTL_H__

struct intel_xe_perf;
struct intel_xe_perf_metric_set;

void ptl_render_basic_add_registers(struct intel_xe_perf *perf, struct intel_xe_perf_metric_set *metric_set);
void ptl_compute_basic_add_registers(struct intel_xe_perf *perf, struct intel_xe_perf_metric_set *metric_set);
void ptl_depth_profile_add_registers(struct intel_xe_perf *perf, struct intel_xe_perf_metric_set *metric_set);
void ptl_device_cache_profile_add_registers(struct intel_xe_perf *perf, struct intel_xe_perf_metric_set *metric_set);
void ptl_memory_profile_add_registers(struct intel_xe_perf *perf, struct intel_xe_perf_metric_set *metric_set);
void ptl_render_pipe_profile_add_registers(struct intel_xe_perf *perf, struct intel_xe_perf_metric_set *metric_set);
void ptl_rt_profile_add_registers(struct intel_xe_perf *perf, struct intel_xe_perf_metric_set *metric_set);
void ptl_vector_engine_profile_add_registers(struct intel_xe_perf *perf, struct intel_xe_perf_metric_set *metric_set);
void ptl_vector_engine_stalls_add_registers(struct intel_xe_perf *perf, struct intel_xe_perf_metric_set *metric_set);
void ptl_xve_pipeline_rasterization_profile_add_registers(struct intel_xe_perf *perf, struct intel_xe_perf_metric_set *metric_set);
void ptl_xve_pipeline_raytracing_profile_add_registers(struct intel_xe_perf *perf, struct intel_xe_perf_metric_set *metric_set);
void ptl_test_oa_add_registers(struct intel_xe_perf *perf, struct intel_xe_perf_metric_set *metric_set);
void ptl_media_set2_add_registers(struct intel_xe_perf *perf, struct intel_xe_perf_metric_set *metric_set);
void ptl_media_set1_add_registers(struct intel_xe_perf *perf, struct intel_xe_perf_metric_set *metric_set);

#endif /* __XE_OA_REGISTERS_PTL_H__ */
